s8iom0s8/V0.2.1/verilog/s8iom0s8_top_hvclamp_wopad.v

//Verilog HDL for "s8iom0s8", "s8iom0s8_top_hvclamp_wopad" "behavioral"


module s8iom0s8_top_hvclamp_wopad ( 
`ifdef USE_PG_PIN
  drn_hvc, ogc_hvc, src_bdy_hvc
`endif
 );

`ifdef USE_PG_PIN
  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
`else
  supply1 ogc_hvc;
  supply1 drn_hvc;
  supply0 src_bdy_hvc;
`endif

endmodule