| /// -*- c++ -*- |
| /// drc: by vun on Oct 11 10:20:39 2017 |
| /// Copyright (c) 2017 by Cypress Semiconductor |
| /// Cypress Confidential Information |
| /// s8phirs-10r drawn-DRC TDR: 001-01905 REV ER |
| /// metopLayer: "met3" Metops 1-8 are checked by drc for layer "met3". |
| /// Switches = nil |
| /// $Id: s8_drcRules 1 2018/06/18 17:29:47 GMT ssoares Exp $ |
| |
| DRC INCREMENTAL CONNECT YES |
| TVF FUNCTION CALtvfOriginCheck [/* |
| tvf::GET_LAYER_ARGS layer1 |
| set cell_Extent [ tvf::GET_LAYER_EXTENT $layer1 ] ;# cooridnates of lower-left and up-right corners |
| set x1 [lindex $cell_Extent 0] ;# x coordinate of lower-left corner |
| set y1 [lindex $cell_Extent 1] ;# y coordinate of lower-left corner |
| if {($x1!=0) || ($y1!=0)} { |
| tvf::OUTLAYER "COPY $layer1" |
| puts "OriginCheck: lower-left corner is not on (0,0), currently locat at ($x1, $y1)" |
| } |
| */] |
| |
| |
| /// Tolerance for round-off errors on skew edges |
| DRC TOLERANCE FACTOR 0.001 |
| |
| /// Unused MaskLayers: (FOM DNM NWM HVTRM TUNM ONOM LVOM P1M NPCM LDNTM NSDM PSDM LICM1 LI1M CTM1 MM1 VIM MM2 VIM2 MM3 VIM3 MM4 VIM4 MM5 NSM PDM PBO RPM CU1M PMM2) |
| LAYER nwell 1000 |
| LAYER MAP 64 DATATYPE 20 1000 // nwell drawing |
| |
| LAYER diff 1001 |
| LAYER MAP 65 DATATYPE 20 1001 // diff drawing |
| |
| LAYER dnwell 1002 |
| LAYER MAP 64 DATATYPE 18 1002 // dnwell drawing |
| |
| LAYER tap 1003 |
| LAYER MAP 65 DATATYPE 44 1003 // tap drawing |
| |
| LAYER lvtn 1004 |
| LAYER MAP 125 DATATYPE 44 1004 // lvtn drawing |
| |
| LAYER hvtp 1005 |
| LAYER MAP 78 DATATYPE 44 1005 // hvtp drawing |
| |
| LAYER hvi 1006 |
| LAYER MAP 75 DATATYPE 20 1006 // hvi drawing |
| |
| LAYER tunm 1007 |
| LAYER MAP 80 DATATYPE 20 1007 // tunm drawing |
| |
| LAYER poly 1008 |
| LAYER MAP 66 DATATYPE 20 1008 // poly drawing |
| |
| LAYER npc 1009 |
| LAYER MAP 95 DATATYPE 20 1009 // npc drawing |
| |
| LAYER nsdm 1010 |
| LAYER MAP 93 DATATYPE 44 1010 // nsdm drawing |
| |
| LAYER psdm 1011 |
| LAYER MAP 94 DATATYPE 20 1011 // psdm drawing |
| |
| LAYER licon1 1012 |
| LAYER MAP 66 DATATYPE 44 1012 // licon1 drawing |
| |
| LAYER li1 1013 |
| LAYER MAP 67 DATATYPE 20 1013 // li1 drawing |
| |
| LAYER mcon 1014 |
| LAYER MAP 67 DATATYPE 44 1014 // mcon drawing |
| |
| LAYER met1 1015 |
| LAYER MAP 68 DATATYPE 20 1015 // met1 drawing |
| |
| LAYER via 1016 |
| LAYER MAP 68 DATATYPE 44 1016 // via drawing |
| |
| LAYER met2 1017 |
| LAYER MAP 69 DATATYPE 20 1017 // met2 drawing |
| |
| LAYER vhvi 1018 |
| LAYER MAP 74 DATATYPE 21 1018 // vhvi drawing |
| |
| LAYER via2 1019 |
| LAYER MAP 69 DATATYPE 44 1019 // via2 drawing |
| |
| LAYER met3 1020 |
| LAYER MAP 70 DATATYPE 20 1020 // met3 drawing |
| |
| LAYER via3 1021 |
| LAYER MAP 70 DATATYPE 44 1021 // via3 drawing |
| |
| LAYER met4 1022 |
| LAYER MAP 71 DATATYPE 20 1022 // met4 drawing |
| |
| LAYER via4 1023 |
| LAYER MAP 71 DATATYPE 44 1023 // via4 drawing |
| |
| LAYER met5 1024 |
| LAYER MAP 72 DATATYPE 20 1024 // met5 drawing |
| |
| LAYER nsm 1025 |
| LAYER MAP 61 DATATYPE 20 1025 // nsm drawing |
| |
| LAYER pad 1026 |
| LAYER MAP 76 DATATYPE 20 1026 // pad drawing |
| |
| LAYER ldntm 1027 |
| LAYER MAP 11 DATATYPE 44 1027 // ldntm drawing |
| |
| LAYER hvntm 1028 |
| LAYER MAP 125 DATATYPE 20 1028 // hvntm drawing |
| |
| LAYER pmm 1029 |
| LAYER MAP 85 DATATYPE 44 1029 // pmm drawing |
| |
| LAYER pnp 1030 |
| LAYER MAP 82 DATATYPE 44 1030 // pnp drawing |
| |
| LAYER capacitor 1031 |
| LAYER MAP 82 DATATYPE 64 1031 // capacitor drawing |
| |
| LAYER ncm 1032 |
| LAYER MAP 92 DATATYPE 44 1032 // ncm drawing |
| |
| LAYER pmm2 1033 |
| LAYER MAP 77 DATATYPE 20 1033 // pmm2 drawing |
| |
| LAYER inductor 1034 |
| LAYER MAP 82 DATATYPE 24 1034 // inductor drawing |
| |
| LAYER rdl 1035 |
| LAYER MAP 74 DATATYPE 20 1035 // rdl drawing |
| |
| LAYER rpm 1036 |
| LAYER MAP 86 DATATYPE 20 1036 // rpm drawing |
| |
| LAYER hvtr 1037 |
| LAYER MAP 18 DATATYPE 20 1037 // hvtr drawing |
| |
| LAYER ubm 1038 |
| LAYER MAP 127 DATATYPE 21 1038 // ubm drawing |
| |
| LAYER bump 1039 |
| LAYER MAP 127 DATATYPE 22 1039 // bump drawing |
| |
| LAYER target 1040 |
| LAYER MAP 76 DATATYPE 44 1040 // target drawing |
| |
| LAYER cfom 1041 |
| LAYER MAP 22 DATATYPE 20 1041 // cfom drawing |
| |
| LAYER clvtnm 1042 |
| LAYER MAP 25 DATATYPE 44 1042 // clvtnm drawing |
| |
| LAYER chvtpm 1043 |
| LAYER MAP 88 DATATYPE 44 1043 // chvtpm drawing |
| |
| LAYER conom 1044 |
| LAYER MAP 87 DATATYPE 44 1044 // conom drawing |
| |
| LAYER clvom 1045 |
| LAYER MAP 45 DATATYPE 20 1045 // clvom drawing |
| |
| LAYER cntm 1046 |
| LAYER MAP 26 DATATYPE 20 1046 // cntm drawing |
| |
| LAYER chvntm 1047 |
| LAYER MAP 38 DATATYPE 20 1047 // chvntm drawing |
| |
| LAYER cnpc 1048 |
| LAYER MAP 44 DATATYPE 20 1048 // cnpc drawing |
| |
| LAYER cnsdm 1049 |
| LAYER MAP 29 DATATYPE 20 1049 // cnsdm drawing |
| |
| LAYER cpsdm 1050 |
| LAYER MAP 31 DATATYPE 20 1050 // cpsdm drawing |
| |
| LAYER cli1m 1051 |
| LAYER MAP 115 DATATYPE 44 1051 // cli1m drawing |
| |
| LAYER cviam3 1052 |
| LAYER MAP 112 DATATYPE 20 1052 // cviam3 drawing |
| |
| LAYER cviam4 1053 |
| LAYER MAP 117 DATATYPE 20 1053 // cviam4 drawing |
| |
| LAYER metop1 1054 |
| LAYER MAP 70 DATATYPE 32 1054 // met3 option1 |
| |
| LAYER metop2 1055 |
| LAYER MAP 70 DATATYPE 33 1055 // met3 option2 |
| |
| LAYER metop3 1056 |
| LAYER MAP 70 DATATYPE 34 1056 // met3 option3 |
| |
| LAYER metop4 1057 |
| LAYER MAP 70 DATATYPE 35 1057 // met3 option4 |
| |
| LAYER metop5 1058 |
| LAYER MAP 70 DATATYPE 36 1058 // met3 option5 |
| |
| LAYER metop6 1059 |
| LAYER MAP 70 DATATYPE 37 1059 // met3 option6 |
| |
| LAYER metop7 1060 |
| LAYER MAP 70 DATATYPE 38 1060 // met3 option7 |
| |
| LAYER metop8 1061 |
| LAYER MAP 70 DATATYPE 39 1061 // met3 option8 |
| |
| LAYER diffTap 1001 1003 |
| // 1001 -> diff drawing |
| // 1003 -> tap drawing |
| |
| LAYER moduleCutAREA 1062 |
| LAYER MAP 81 DATATYPE 10 1062 // areaid moduleCut |
| |
| LAYER ETESTID 1063 |
| LAYER MAP 81 DATATYPE 101 1063 // areaid etest |
| |
| LAYER SEALID 1064 |
| LAYER MAP 81 DATATYPE 1 1064 // areaid seal |
| |
| LAYER FRAMEID 1065 |
| LAYER MAP 81 DATATYPE 3 1065 // areaid frame |
| |
| LAYER ESDID 1066 |
| LAYER MAP 81 DATATYPE 19 1066 // areaid esd |
| |
| LAYER DIODEID 1067 |
| LAYER MAP 81 DATATYPE 23 1067 // areaid diode |
| |
| LAYER RFDIODEID 1068 |
| LAYER MAP 81 DATATYPE 125 1068 // areaid rfdiode |
| |
| LAYER COREID 1069 |
| LAYER MAP 81 DATATYPE 2 1069 // areaid core |
| |
| LAYER STDCID 1070 |
| LAYER MAP 81 DATATYPE 4 1070 // areaid standardc |
| |
| LAYER ENID 1071 |
| LAYER MAP 81 DATATYPE 57 1071 // areaid extendedDrain |
| |
| LAYER LDID 1072 |
| LAYER MAP 81 DATATYPE 14 1072 // areaid lowTapDensity |
| |
| LAYER IJID 1073 |
| LAYER MAP 81 DATATYPE 17 1073 // areaid injection |
| |
| LAYER polyGate 1074 |
| LAYER MAP 66 DATATYPE 9 1074 // poly gate |
| |
| LAYER polyModel 1075 |
| LAYER MAP 66 TEXTTYPE 83 1075 // poly model |
| |
| LAYER LVID 1076 |
| LAYER MAP 81 DATATYPE 60 1076 // areaid lvNative |
| |
| LAYER frameBndr 1077 |
| LAYER MAP 81 DATATYPE 12 1077 // areaid frameRect |
| |
| LAYER HVNID 1078 |
| LAYER MAP 81 DATATYPE 63 1078 // areaid hvnwell |
| |
| LAYER dieCut 1079 |
| LAYER MAP 81 DATATYPE 11 1079 // areaid dieCut |
| |
| LAYER photoID 1080 |
| LAYER MAP 81 DATATYPE 81 1080 // areaid photo |
| |
| LAYER ANALOGID 1081 |
| LAYER MAP 81 DATATYPE 79 1081 // areaid analog |
| |
| LAYER padCenter 1082 |
| LAYER MAP 81 DATATYPE 20 1082 // padCenter drawing |
| |
| LAYER polyres 1083 |
| LAYER MAP 66 DATATYPE 13 1083 // poly res |
| |
| LAYER diffres 1084 |
| LAYER MAP 65 DATATYPE 13 1084 // diff res |
| |
| LAYER pwres 1085 |
| LAYER MAP 64 DATATYPE 13 1085 // pwell res |
| |
| LAYER diffhvp 1086 |
| LAYER MAP 65 DATATYPE 8 1086 // diff hv |
| |
| LAYER li1res 1087 |
| LAYER MAP 67 DATATYPE 13 1087 // li1 res |
| |
| LAYER fuse 1088 |
| LAYER MAP 71 DATATYPE 17 1088 // met4 fuse |
| |
| LAYER padText 1089 |
| LAYER MAP 76 TEXTTYPE 5 1089 // pad label |
| |
| LAYER diffLabel 1090 |
| LAYER MAP 65 DATATYPE 6 1090 // diff label |
| |
| LAYER tapLabel 1091 |
| LAYER MAP 65 DATATYPE 5 1091 // tap label |
| |
| LAYER nwellLabel 1092 |
| LAYER MAP 64 DATATYPE 5 1092 // nwell label |
| |
| LAYER polyLabel 1093 |
| LAYER MAP 66 DATATYPE 5 1093 // poly label |
| |
| LAYER met1Label 1094 |
| LAYER MAP 68 DATATYPE 5 1094 // met1 label |
| |
| LAYER met2Label 1095 |
| LAYER MAP 69 DATATYPE 5 1095 // met2 label |
| |
| LAYER met3Label 1096 |
| LAYER MAP 70 DATATYPE 5 1096 // met3 label |
| |
| LAYER met4Label 1097 |
| LAYER MAP 71 DATATYPE 5 1097 // met4 label |
| |
| LAYER met5Label 1098 |
| LAYER MAP 72 DATATYPE 5 1098 // met5 label |
| |
| LAYER li1Block 1099 |
| LAYER MAP 67 DATATYPE 10 1099 // li1 blockage |
| |
| LAYER met1Block 1100 |
| LAYER MAP 68 DATATYPE 10 1100 // met1 blockage |
| |
| LAYER met2Block 1101 |
| LAYER MAP 69 DATATYPE 10 1101 // met2 blockage |
| |
| LAYER met3Block 1102 |
| LAYER MAP 70 DATATYPE 10 1102 // met3 blockage |
| |
| LAYER met4Block 1103 |
| LAYER MAP 71 DATATYPE 10 1103 // met4 blockage |
| |
| LAYER met5Block 1104 |
| LAYER MAP 72 DATATYPE 10 1104 // met5 blockage |
| |
| LAYER prBndry 1105 |
| LAYER MAP 235 DATATYPE 4 1105 // prBoundary boundary |
| |
| LAYER diffBndry 1106 |
| LAYER MAP 65 DATATYPE 4 1106 // diff boundary |
| |
| LAYER tapBndry 1107 |
| LAYER MAP 65 DATATYPE 60 1107 // tap boundary |
| |
| LAYER mconBndry 1108 |
| LAYER MAP 67 DATATYPE 60 1108 // mcon boundary |
| |
| LAYER polyBndry 1109 |
| LAYER MAP 66 DATATYPE 4 1109 // poly boundary |
| |
| LAYER viaBndry 1110 |
| LAYER MAP 68 DATATYPE 60 1110 // via boundary |
| |
| LAYER via2Bndry 1111 |
| LAYER MAP 69 DATATYPE 60 1111 // via2 boundary |
| |
| LAYER via3Bndry 1112 |
| LAYER MAP 70 DATATYPE 60 1112 // via3 boundary |
| |
| LAYER via4Bndry 1113 |
| LAYER MAP 71 DATATYPE 60 1113 // via4 boundary |
| |
| LAYER li1tt 1114 1115 1116 1117 |
| LAYER MAP 67 TEXTTYPE 20 1114 // li1 drawing |
| LAYER MAP 67 TEXTTYPE 5 1115 // li1 label |
| LAYER MAP 67 TEXTTYPE 23 1116 // li1 net |
| LAYER MAP 67 TEXTTYPE 16 1117 // li1 pin |
| |
| LAYER met1tt 1118 1119 1120 1121 |
| LAYER MAP 68 TEXTTYPE 20 1118 // met1 drawing |
| LAYER MAP 68 TEXTTYPE 5 1119 // met1 label |
| LAYER MAP 68 TEXTTYPE 23 1120 // met1 net |
| LAYER MAP 68 TEXTTYPE 16 1121 // met1 pin |
| |
| LAYER met2tt 1122 1123 1124 1125 |
| LAYER MAP 69 TEXTTYPE 20 1122 // met2 drawing |
| LAYER MAP 69 TEXTTYPE 5 1123 // met2 label |
| LAYER MAP 69 TEXTTYPE 23 1124 // met2 net |
| LAYER MAP 69 TEXTTYPE 16 1125 // met2 pin |
| |
| LAYER met3tt 1126 1127 1128 1129 |
| LAYER MAP 70 TEXTTYPE 20 1126 // met3 drawing |
| LAYER MAP 70 TEXTTYPE 5 1127 // met3 label |
| LAYER MAP 70 TEXTTYPE 23 1128 // met3 net |
| LAYER MAP 70 TEXTTYPE 16 1129 // met3 pin |
| |
| LAYER met4tt 1130 1131 1132 1133 |
| LAYER MAP 71 TEXTTYPE 20 1130 // met4 drawing |
| LAYER MAP 71 TEXTTYPE 5 1131 // met4 label |
| LAYER MAP 71 TEXTTYPE 23 1132 // met4 net |
| LAYER MAP 71 TEXTTYPE 16 1133 // met4 pin |
| |
| LAYER met5tt 1134 1135 1136 1137 |
| LAYER MAP 72 TEXTTYPE 20 1134 // met5 drawing |
| LAYER MAP 72 TEXTTYPE 5 1135 // met5 label |
| LAYER MAP 72 TEXTTYPE 23 1136 // met5 net |
| LAYER MAP 72 TEXTTYPE 16 1137 // met5 pin |
| |
| LAYER polytt 1138 1139 1140 1141 |
| LAYER MAP 66 TEXTTYPE 20 1138 // poly drawing |
| LAYER MAP 66 TEXTTYPE 5 1139 // poly label |
| LAYER MAP 66 TEXTTYPE 23 1140 // poly net |
| LAYER MAP 66 TEXTTYPE 16 1141 // poly pin |
| |
| LAYER difftt 1142 1143 1144 1145 |
| LAYER MAP 65 TEXTTYPE 20 1142 // diff drawing |
| LAYER MAP 65 TEXTTYPE 6 1143 // diff label |
| LAYER MAP 65 TEXTTYPE 23 1144 // diff net |
| LAYER MAP 65 TEXTTYPE 16 1145 // diff pin |
| |
| LAYER poly_pin 1146 |
| LAYER MAP 66 DATATYPE 16 1146 // poly pin |
| |
| LAYER li1_pin 1147 |
| LAYER MAP 67 DATATYPE 16 1147 // li1 pin |
| |
| LAYER met1_pin 1148 |
| LAYER MAP 68 DATATYPE 16 1148 // met1 pin |
| |
| LAYER met2_pin 1149 |
| LAYER MAP 69 DATATYPE 16 1149 // met2 pin |
| |
| LAYER met3_pin 1150 |
| LAYER MAP 70 DATATYPE 16 1150 // met3 pin |
| |
| LAYER met4_pin 1151 |
| LAYER MAP 71 DATATYPE 16 1151 // met4 pin |
| |
| LAYER met5_pin 1152 |
| LAYER MAP 72 DATATYPE 16 1152 // met5 pin |
| |
| LAYER nwellpt 1153 |
| LAYER MAP 64 TEXTTYPE 16 1153 // nwell pin |
| LAYER MAP 64 TEXTTYPE 0 1153 // nwell pin |
| |
| LAYER polypt 1154 |
| LAYER MAP 66 TEXTTYPE 16 1154 // poly pin |
| LAYER MAP 66 TEXTTYPE 0 1154 // poly pin |
| |
| LAYER li1pt 1155 |
| LAYER MAP 67 TEXTTYPE 16 1155 // li1 pin |
| LAYER MAP 67 TEXTTYPE 0 1155 // li1 pin |
| |
| LAYER met1pt 1156 |
| LAYER MAP 68 TEXTTYPE 16 1156 // met1 pin |
| LAYER MAP 68 TEXTTYPE 0 1156 // met1 pin |
| |
| LAYER met2pt 1157 |
| LAYER MAP 69 TEXTTYPE 16 1157 // met2 pin |
| LAYER MAP 69 TEXTTYPE 0 1157 // met2 pin |
| |
| LAYER met3pt 1158 |
| LAYER MAP 70 TEXTTYPE 16 1158 // met3 pin |
| LAYER MAP 70 TEXTTYPE 0 1158 // met3 pin |
| |
| LAYER met4pt 1159 |
| LAYER MAP 71 TEXTTYPE 16 1159 // met4 pin |
| LAYER MAP 71 TEXTTYPE 0 1159 // met4 pin |
| |
| LAYER met5pt 1160 |
| LAYER MAP 72 TEXTTYPE 16 1160 // met5 pin |
| LAYER MAP 72 TEXTTYPE 0 1160 // met5 pin |
| |
| LAYER textlabel 1161 |
| LAYER MAP 83 TEXTTYPE 44 1161 // text drawing |
| |
| LAYER ccorner 1162 |
| LAYER MAP 81 DATATYPE 51 1162 // areaid critCorner |
| |
| LAYER critside 1163 |
| LAYER MAP 81 DATATYPE 52 1163 // areaid critSid |
| |
| LAYER prune 1164 |
| LAYER MAP 84 DATATYPE 44 1164 // prune drawing |
| |
| LAYER cncmMask 1165 |
| LAYER MAP 17 DATATYPE 0 1165 // cncm mask |
| |
| LAYER cncmDrawing 1166 |
| LAYER MAP 96 DATATYPE 44 1166 // cncm drawing |
| |
| LAYER padtt 1167 1089 |
| LAYER MAP 76 TEXTTYPE 20 1167 // pad drawing |
| // 1089 -> pad label |
| |
| LAYER pad_pin 1168 |
| LAYER MAP 76 DATATYPE 16 1168 // pad pin |
| |
| LAYER padpt 1169 |
| LAYER MAP 76 TEXTTYPE 16 1169 // pad pin |
| LAYER MAP 76 TEXTTYPE 0 1169 // pad pin |
| |
| LAYER LVTNMdg 1042 |
| // 1042 -> clvtnm drawing |
| |
| LAYER HVTPMdg 1043 |
| // 1043 -> chvtpm drawing |
| |
| LAYER HVNTMdg 1047 |
| // 1047 -> chvntm drawing |
| |
| LAYER NTMdg 1046 |
| // 1046 -> cntm drawing |
| |
| LAYER NTMdrop 1170 |
| LAYER MAP 26 DATATYPE 22 1170 // cntm maskDrop |
| |
| LAYER LVTNMdrop 1171 |
| LAYER MAP 25 DATATYPE 42 1171 // clvtnm maskDrop |
| |
| LAYER HVTPMdrop 1172 |
| LAYER MAP 97 DATATYPE 42 1172 // chvtpm maskDrop |
| |
| LAYER LI1Mdrop 1173 |
| LAYER MAP 115 DATATYPE 42 1173 // cli1m maskDrop |
| |
| LAYER LICM1drop 1174 |
| LAYER MAP 106 DATATYPE 42 1174 // clicm1 maskDrop |
| |
| LAYER PSDMdrop 1175 |
| LAYER MAP 31 DATATYPE 22 1175 // cpsdm maskDrop |
| |
| LAYER NSDMdrop 1176 |
| LAYER MAP 29 DATATYPE 22 1176 // cnsdm maskDrop |
| |
| LAYER P1Mdrop 1177 |
| LAYER MAP 33 DATATYPE 42 1177 // cp1m maskDrop |
| |
| LAYER FOMdrop 1178 |
| LAYER MAP 22 DATATYPE 22 1178 // cfom maskDrop |
| |
| LAYER NTMadd 1179 |
| LAYER MAP 26 DATATYPE 21 1179 // cntm maskAdd |
| |
| LAYER LVTNMadd 1180 |
| LAYER MAP 25 DATATYPE 43 1180 // clvtnm maskAdd |
| |
| LAYER HVTPMadd 1181 |
| LAYER MAP 97 DATATYPE 43 1181 // chvtpm maskAdd |
| |
| LAYER LI1Madd 1182 |
| LAYER MAP 115 DATATYPE 43 1182 // cli1m maskAdd |
| |
| LAYER LICM1add 1183 |
| LAYER MAP 106 DATATYPE 43 1183 // clicm1 maskAdd |
| |
| LAYER PSDMadd 1184 |
| LAYER MAP 31 DATATYPE 21 1184 // cpsdm maskAdd |
| |
| LAYER NSDMadd 1185 |
| LAYER MAP 29 DATATYPE 21 1185 // cnsdm maskAdd |
| |
| LAYER P1Madd 1186 |
| LAYER MAP 33 DATATYPE 43 1186 // cp1m maskAdd |
| |
| LAYER FOMadd 1187 |
| LAYER MAP 22 DATATYPE 21 1187 // cfom maskAdd |
| |
| LAYER PMM2mk 1188 |
| LAYER MAP 94 DATATYPE 0 1188 // cpmm2 mask |
| |
| LAYER CU1Mmk 1189 |
| LAYER MAP 93 DATATYPE 0 1189 // ccu1m mask |
| |
| LAYER RPMmk 1190 |
| LAYER MAP 96 DATATYPE 0 1190 // crpm mask |
| |
| LAYER PBOmk 1191 |
| LAYER MAP 99 DATATYPE 0 1191 // cpbo mask |
| |
| LAYER PDMmk 1192 |
| LAYER MAP 37 DATATYPE 0 1192 // cpdm mask |
| |
| LAYER NSMmk 1193 |
| LAYER MAP 22 DATATYPE 0 1193 // cnsm mask |
| |
| LAYER MM5mk 1194 |
| LAYER MAP 59 DATATYPE 0 1194 // cmm5 mask |
| |
| LAYER VIM4mk 1195 |
| LAYER MAP 58 DATATYPE 0 1195 // cviam4 mask |
| |
| LAYER MM4mk 1196 |
| LAYER MAP 51 DATATYPE 0 1196 // cmm4 mask |
| |
| LAYER VIM3mk 1197 |
| LAYER MAP 50 DATATYPE 0 1197 // cviam3 mask |
| |
| LAYER MM3mk 1198 |
| LAYER MAP 34 DATATYPE 0 1198 // cmm3 mask |
| |
| LAYER VIM2mk 1199 |
| LAYER MAP 44 DATATYPE 0 1199 // cviam2 mask |
| |
| LAYER MM2mk 1200 |
| LAYER MAP 41 DATATYPE 0 1200 // cmm2 mask |
| |
| LAYER VIMmk 1201 |
| LAYER MAP 40 DATATYPE 0 1201 // cviam mask |
| |
| LAYER MM1mk 1202 |
| LAYER MAP 36 DATATYPE 0 1202 // cmm1 mask |
| |
| LAYER CTM1mk 1203 |
| LAYER MAP 35 DATATYPE 0 1203 // cctm1 mask |
| |
| LAYER LI1Mmk 1204 |
| LAYER MAP 56 DATATYPE 0 1204 // cli1m mask |
| |
| LAYER LICM1mk 1205 |
| LAYER MAP 43 DATATYPE 0 1205 // clicm1 mask |
| |
| LAYER PSDMmk 1206 |
| LAYER MAP 32 DATATYPE 0 1206 // cpsdm mask |
| |
| LAYER NSDMmk 1207 |
| LAYER MAP 30 DATATYPE 0 1207 // cnsdm mask |
| |
| LAYER LDNTMmk 1208 |
| LAYER MAP 11 DATATYPE 0 1208 // cldntm mask |
| |
| LAYER NPCMmk 1209 |
| LAYER MAP 49 DATATYPE 0 1209 // cnpc mask |
| |
| LAYER HVNTMmk 1210 |
| LAYER MAP 39 DATATYPE 0 1210 // chvntm mask |
| |
| LAYER NTMmk 1211 |
| LAYER MAP 27 DATATYPE 0 1211 // cntm mask |
| |
| LAYER P1Mmk 1212 |
| LAYER MAP 28 DATATYPE 0 1212 // cp1m mask |
| |
| LAYER LVOMmk 1213 |
| LAYER MAP 46 DATATYPE 0 1213 // clvom mask |
| |
| LAYER ONOMmk 1214 |
| LAYER MAP 88 DATATYPE 0 1214 // conom mask |
| |
| LAYER TUNMmk 1215 |
| LAYER MAP 20 DATATYPE 0 1215 // ctunm mask |
| |
| LAYER HVTRMmk 1216 |
| LAYER MAP 98 DATATYPE 0 1216 // chvtrm mask |
| |
| LAYER HVTPMmk 1217 |
| LAYER MAP 97 DATATYPE 0 1217 // chvtpm mask |
| |
| LAYER LVTNMmk 1218 |
| LAYER MAP 25 DATATYPE 0 1218 // clvtnm mask |
| |
| LAYER NWMmk 1219 |
| LAYER MAP 21 DATATYPE 0 1219 // cnwm mask |
| |
| LAYER DNMmk 1220 |
| LAYER MAP 48 DATATYPE 0 1220 // cdnm mask |
| |
| LAYER FOMmk 1221 |
| LAYER MAP 23 DATATYPE 0 1221 // cfom mask |
| |
| LAYER met5Pin 1152 |
| // 1152 -> met5 pin |
| |
| LAYER met4Pin 1151 |
| // 1151 -> met4 pin |
| |
| LAYER met3Pin 1150 |
| // 1150 -> met3 pin |
| |
| LAYER met2Pin 1149 |
| // 1149 -> met2 pin |
| |
| LAYER met1Pin 1148 |
| // 1148 -> met1 pin |
| |
| LAYER li1Pin 1147 |
| // 1147 -> li1 pin |
| |
| LAYER polyPin 1146 |
| // 1146 -> poly pin |
| |
| LAYER diffPin 1222 |
| LAYER MAP 65 DATATYPE 16 1222 // diff pin |
| |
| LAYER cmm4WaffleDrop 1223 |
| LAYER MAP 112 DATATYPE 4 1223 // cmm4 waffleDrop |
| |
| LAYER cmm3WaffleDrop 1224 |
| LAYER MAP 107 DATATYPE 24 1224 // cmm3 waffleDrop |
| |
| LAYER cmm2WaffleDrop 1225 |
| LAYER MAP 105 DATATYPE 52 1225 // cmm2 waffleDrop |
| |
| LAYER cmm1WaffleDrop 1226 |
| LAYER MAP 62 DATATYPE 24 1226 // cmm1 waffleDrop |
| |
| LAYER cp1mWaffleDrop 1227 |
| LAYER MAP 33 DATATYPE 24 1227 // cp1m waffleDrop |
| |
| LAYER cfomWaffleDrop 1228 |
| LAYER MAP 22 DATATYPE 24 1228 // cfom waffleDrop |
| |
| LAYER capm 1229 |
| LAYER MAP 89 DATATYPE 44 1229 // capm drawing |
| |
| LAYER cap2m 1230 |
| LAYER MAP 97 DATATYPE 44 1230 // cap2m drawing |
| |
| LAYER urpm 1231 |
| LAYER MAP 79 DATATYPE 20 1231 // urpm drawing |
| |
| LAYOUT BASE LAYER diff |
| LAYOUT BASE LAYER tap |
| LAYOUT BASE LAYER poly |
| LAYOUT BASE LAYER lvtn |
| LAYOUT BASE LAYER hvtp |
| LAYOUT BASE LAYER hvi |
| LAYOUT BASE LAYER npc |
| LAYOUT BASE LAYER nsdm |
| LAYOUT BASE LAYER psdm |
| LAYOUT BASE LAYER DIODEID |
| LAYOUT BASE LAYER ESDID |
| LAYOUT BASE LAYER COREID |
| LAYOUT BASE LAYER diffres |
| LAYOUT BASE LAYER polyres |
| LAYOUT BASE LAYER li1res |
| LAYOUT BASE LAYER fuse |
| LAYOUT BASE LAYER metop1 |
| LAYOUT BASE LAYER metop2 |
| LAYOUT BASE LAYER metop3 |
| LAYOUT BASE LAYER metop4 |
| LAYOUT BASE LAYER metop5 |
| LAYOUT BASE LAYER metop6 |
| LAYOUT BASE LAYER metop7 |
| LAYOUT BASE LAYER metop8 |
| /// start shared drc rules |
| metop1_met3 = metop1 OR met3 |
| metop2_met3 = metop2 OR met3 |
| metop3_met3 = metop3 OR met3 |
| metop4_met3 = metop4 OR met3 |
| metop5_met3 = metop5 OR met3 |
| metop6_met3 = metop6 OR met3 |
| metop7_met3 = metop7 OR met3 |
| metop8_met3 = metop8 OR met3 |
| PadPcell = EXTENT CELL "padPL*" |
| /// $Id: s8_drcRules 1 2018/06/18 17:29:47 GMT ssoares Exp $ |
| LAYER pwellLabel 1229 |
| LAYER MAP 64 DATATYPE 59 1229 // pwell label |
| |
| LAYER pwelltt 1230 |
| LAYER MAP 64 TEXTTYPE 59 1230 // pwell label |
| |
| LAYER pwell_pin 1231 |
| LAYER MAP 122 DATATYPE 16 1231 // pwell pin |
| |
| LAYER pwellpt 1232 |
| LAYER MAP 122 TEXTTYPE 16 1232 // pwell pin |
| LAYER MAP 122 TEXTTYPE 0 1232 // pwell pin |
| |
| LAYER fomDummyDRC 1233 |
| LAYER MAP 22 DATATYPE 23 1233 // fom dummy |
| |
| LAYER textdraw 1161 |
| // 1161 -> text drawing |
| |
| LAYER localSub 1234 |
| LAYER MAP 81 DATATYPE 53 1234 // areaid substrateCut |
| |
| uhvi = COPY 4000 |
| EXTDRAIN20 = COPY 4001 |
| ZENERID = COPY 4002 |
| LOWVTID = COPY 4003 |
| pwbm = COPY 4004 |
| pwde = COPY 4005 |
| inductor_exempt = COPY inductor |
| NTAP = tap AND nwell |
| PTAP = tap NOT nwell |
| PDIFF = diff AND nwell |
| NDIFF = diff NOT nwell |
| SRCDRN = diff NOT poly |
| POLYandDIFF = poly AND diff |
| GATE = COPY POLYandDIFF |
| GATESIDE = GATE INSIDE EDGE diff |
| GATEEND = GATE COINCIDENT INSIDE EDGE diff |
| diffTapEdge = diff COINCIDENT OUTSIDE EDGE tap |
| MOSGATE = COPY GATE |
| EMOSGATE = COPY MOSGATE |
| nDiffTap = NDIFF OR NTAP |
| pDiffTap = PDIFF OR PTAP |
| GATE_PERI = GATE NOT COREID |
| PDIFF_PERI = PDIFF NOT COREID |
| PDIFF_CORE = PDIFF AND COREID |
| NDIFF_CORE = NDIFF AND COREID |
| NDIFF_PERI = NDIFF NOT COREID |
| EMOSGATE_PERI = EMOSGATE NOT COREID |
| EMOSGATE_CORE = EMOSGATE AND COREID |
| poly_PERI = poly NOT COREID |
| poly_CORE = poly AND COREID |
| li1_PERI = li1 NOT COREID |
| li1_CORE = li1 AND COREID |
| licon1_PERI = licon1 NOT COREID |
| licon1_CORE = licon1 AND COREID |
| diff_PERI = diff NOT COREID |
| diff_CORE = diff AND COREID |
| tap_PERI = tap NOT COREID |
| tap_CORE = tap AND COREID |
| diffTap_CORE = diffTap AND COREID |
| diffTap_PERI = diffTap NOT COREID |
| mcon_PERI = mcon NOT COREID |
| mcon_CORE = mcon AND COREID |
| hvtp_PERI = hvtp NOT COREID |
| hvtp_CORE = hvtp AND COREID |
| lvtn_PERI = lvtn NOT COREID |
| lvtn_CORE = lvtn AND COREID |
| nsdm_PERI = nsdm NOT COREID |
| nsdm_CORE = nsdm AND COREID |
| psdm_PERI = psdm NOT COREID |
| psdm_CORE = psdm AND COREID |
| PTAP_PERI = PTAP NOT COREID |
| PTAP_CORE = PTAP AND COREID |
| NTAP_PERI = NTAP NOT COREID |
| NTAP_CORE = NTAP AND COREID |
| via_PERI = via NOT COREID |
| via_CORE = via AND COREID |
| via2_PERI = via2 NOT COREID |
| via2_CORE = via2 AND COREID |
| DISCONNECT |
| npccon = npc AND licon1 |
| CONNECT dnwell nwell |
| CONNECT nwell tap BY NTAP |
| CONNECT tap li1 BY licon1 |
| CONNECT poly li1 BY npccon |
| CONNECT li1 met1 BY mcon |
| CONNECT met1 met2 BY via |
| CONNECT met3 met2 BY via2 |
| CONNECT met3 met4 BY via3 |
| CONNECT met4 met5 BY via4 |
| CONNECT met5 pad |
| CONNECT rdl pad |
| ntapTouchNwell = NTAP INSIDE nwell |
| nwellTouchNtap = nwell INSIDE NTAP |
| ntapnwellInNdiff = (HOLES NDIFF) INSIDE (ntapTouchNwell OR nwellTouchNtap) |
| ESD_nwell_tap = ESDID AND (ntapTouchNwell AND ntapnwellInNdiff) |
| pSRCDRN = SRCDRN AND PDIFF |
| nSRCDRN = SRCDRN AND NDIFF |
| xfom = diffTap NOT poly |
| licon1ToXfom = INTERACT licon1 (licon1 AND xfom) |
| polyAndRes = polyres AND poly |
| diffTapButtEdge = diff COINCIDENT OUTSIDE EDGE tap |
| tapDiffButtEdge = tap COINCIDENT OUTSIDE EDGE diff |
| NTAP_nonESD_nonuhvi = NTAP_PERI NOT (ESD_nwell_tap OR uhvi) |
| diffNoTapEdge = diff OUTSIDE EDGE tap |
| tapNoDiffEdge = tap OUTSIDE EDGE diff |
| diffNotRes = diff NOT diffres |
| exempt_tech_CD = EXTENT CELL "*_tech_CD_top*" |
| tableH3rfFets = (EXTENT CELL "s8rf_plowvt_W5p0_L0p50_M4_b") OR |
| ((EXTENT CELL "s8rf_plowvt_W5p0_L0p35_M4_b") OR |
| ((EXTENT CELL "s8rf_plowvt_W3p0_L0p35_M2_b") OR |
| ((EXTENT CELL "s8rf_plowvt_W3p0_L0p50_M2_b") OR |
| ((EXTENT CELL "s8rf_plowvt_W3p0_L0p35_M4_b") OR |
| ((EXTENT CELL "s8rf_plowvt_W5p0_L0p50_M2_b") OR |
| ((EXTENT CELL "s8rf_plowvt_W5p0_L0p35_M2_b") OR (EXTENT CELL "s8rf_plowvt_W3p0_L0p50_M4_b"))))))) |
| exempt_Pdiff_Cells = (EXTENT CELL "*sr_mcell*") OR (EXTENT CELL "sr_tcell*") |
| exempt_nwell6_Cells = (EXTENT CELL "*sr_1028x128_ssa*") OR |
| ((EXTENT CELL "sr_1028x1025_ssa*") OR |
| ((EXTENT CELL "up_32x256t*") OR (EXTENT CELL "up_128x256t*"))) |
| exemptNhvnativeCell = EXTENT CELL "s8fgvr_fg2n" ORIGINAL |
| exemptDeCapCell = (EXTENT CELL "scs8*decap*" ORIGINAL) AND STDCID |
| polyLicon1 = INTERACT (licon1 NOT licon1ToXfom) ((licon1 NOT licon1ToXfom) AND poly) |
| source_diffusion = (nSRCDRN WITH EDGE (nSRCDRN COINCIDENT OUTSIDE EDGE PTAP)) OR (pSRCDRN WITH EDGE (pSRCDRN COINCIDENT OUTSIDE EDGE NTAP)) |
| licon1ToXfom_PERI = licon1ToXfom NOT COREID |
| polyLicon1_PERI = polyLicon1 NOT COREID |
| polyLicon1_CORE = polyLicon1 AND COREID |
| source_diffusion_PERI = source_diffusion NOT COREID |
| ESDID_sz = SIZE ESDID BY 0.2 |
| poly_ESD = poly AND ESDID_sz |
| poly_nonESD = poly NOT ESDID_sz |
| tap_SEAL = tap AND SEALID |
| tap_nonSEAL = tap NOT (SEALID OR ENID) |
| tap_ENID = (tap NOT SEALID) AND ENID |
| li1_SEAL = li1 AND SEALID |
| li1_PERI_nonSEAL = li1_PERI NOT SEALID |
| licon_SEAL = licon1 AND SEALID |
| licon_nonSEAL = licon1 NOT SEALID |
| mcon_SEAL = mcon AND SEALID |
| mcon_nonSEAL = mcon NOT SEALID |
| via_SEAL = via AND SEALID |
| via_nonSEAL = via NOT SEALID |
| via2_SEAL = via2 AND SEALID |
| via2_nonSEAL = via2 NOT SEALID |
| critArea = (critside OR ccorner) AND (HOLES SEALID) |
| sealRing = DONUT SEALID |
| sealHoles = HOLES SEALID |
| SEALnoHoles_ORIGIN = sealRing OR sealHoles |
| Topcell_Extent = EXTENT CELL SEALnoHoles_ORIGIN ORIGINAL |
| exemptCells = ((EXTENT CELL "*lazX_*") OR (EXTENT CELL "*lazY_*")) OR ((EXTENT CELL "*tech_CD_*") OR (EXTENT CELL "*_techCD_*")) |
| extentDie = (SEALID OR (HOLES SEALID)) NOT exemptCells |
| gated_npn = EXTENT CELL "s8rf_npn_1x1_2p0_HV" ORIGINAL |
| via3_SEAL = via3 AND SEALID |
| via3_nonSEAL = via3 NOT SEALID |
| via4_SEAL = via4 NOT SEALID |
| via4_nonSEAL = via4 NOT SEALID |
| anchLayers = INTERACT ((poly AND critArea) AND |
| ((li1 AND critArea) AND |
| ((met1 AND critArea) AND |
| ((met2 AND critArea) AND |
| ((met3 AND critArea) AND (met4 AND critArea)))))) (((poly AND critArea) AND |
| ((li1 AND critArea) AND |
| ((met1 AND critArea) AND |
| ((met2 AND critArea) AND |
| ((met3 AND critArea) AND (met4 AND critArea)))))) AND critArea) |
| amcon = mcon AND anchLayers |
| alicon1 = licon1 AND anchLayers |
| avia = via AND anchLayers |
| avia2 = via2 AND anchLayers |
| avia3 = via3 AND anchLayers |
| anchmcon = amcon OUTSIDE (avia3 OR |
| (avia2 OR |
| (avia OR alicon1))) |
| anchlicon1 = alicon1 OUTSIDE (avia3 OR |
| (avia2 OR |
| (avia OR amcon))) |
| anchvia = avia OUTSIDE (avia3 OR |
| (avia2 OR |
| (alicon1 OR amcon))) |
| anchvia2 = avia2 OUTSIDE (avia3 OR |
| (avia OR |
| (alicon1 OR amcon))) |
| anchvia3 = avia3 OUTSIDE (avia2 OR |
| (avia OR |
| (alicon1 OR amcon))) |
| acontacts = amcon OR |
| (alicon1 OR |
| (avia OR |
| (avia2 OR avia3))) |
| anchcontacts = anchmcon OR |
| (anchlicon1 OR |
| (anchvia OR |
| (anchvia2 OR anchvia3))) |
| overlapCon = acontacts NOT anchcontacts |
| anchorTmp = ((((anchLayers ENCLOSE mcon) ENCLOSE licon1) ENCLOSE via) ENCLOSE via2) ENCLOSE via3 |
| falseAnch = CUT poly anchLayers |
| anchor = anchorTmp OUTSIDE (overlapCon OR falseAnch) |
| "k_0_anchor" { |
| @ keep: anchor - anchor |
| COPY anchor |
| } |
| li1Anc = li1 AND anchor |
| li1Peri_noSEAL_noAnch = li1_PERI_nonSEAL NOT li1Anc |
| polyAnc = poly AND anchor |
| poly_noESD_noAnch = poly_nonESD NOT (polyAnc OR gated_npn) |
| "r_0_X.1b" { |
| @ X.1b: off 0.005 grid nwell vertex |
| OFFGRID nwell 5 |
| } |
| "r_1_X.1b" { |
| @ X.1b: off 0.005 grid diff vertex |
| OFFGRID diff 5 |
| } |
| "r_2_X.1b" { |
| @ X.1b: off 0.005 grid dnwell vertex |
| OFFGRID dnwell 5 |
| } |
| "r_3_X.1b" { |
| @ X.1b: off 0.005 grid tap vertex |
| OFFGRID tap 5 |
| } |
| "r_4_X.1b" { |
| @ X.1b: off 0.005 grid lvtn vertex |
| OFFGRID lvtn 5 |
| } |
| "r_5_X.1b" { |
| @ X.1b: off 0.005 grid hvtp vertex |
| OFFGRID hvtp 5 |
| } |
| "r_6_X.1b" { |
| @ X.1b: off 0.005 grid hvi vertex |
| OFFGRID hvi 5 |
| } |
| "r_7_X.1b" { |
| @ X.1b: off 0.005 grid tunm vertex |
| OFFGRID tunm 5 |
| } |
| "r_8_X.1b" { |
| @ X.1b: off 0.005 grid poly vertex |
| OFFGRID poly 5 |
| } |
| "r_9_X.1b" { |
| @ X.1b: off 0.005 grid npc vertex |
| OFFGRID npc 5 |
| } |
| "r_10_X.1b" { |
| @ X.1b: off 0.005 grid nsdm vertex |
| OFFGRID nsdm 5 |
| } |
| "r_11_X.1b" { |
| @ X.1b: off 0.005 grid psdm vertex |
| OFFGRID psdm 5 |
| } |
| "r_12_X.1b" { |
| @ X.1b: off 0.005 grid licon1 vertex |
| OFFGRID licon1 5 |
| } |
| "r_13_X.1b" { |
| @ X.1b: off 0.005 grid li1 vertex |
| OFFGRID li1 5 |
| } |
| "r_14_X.1b" { |
| @ X.1b: off 0.005 grid mcon vertex |
| OFFGRID mcon 5 |
| } |
| "r_15_X.1b" { |
| @ X.1b: off 0.005 grid met1 vertex |
| OFFGRID met1 5 |
| } |
| "r_16_X.1b" { |
| @ X.1b: off 0.005 grid via vertex |
| OFFGRID via 5 |
| } |
| "r_17_X.1b" { |
| @ X.1b: off 0.005 grid met2 vertex |
| OFFGRID met2 5 |
| } |
| "r_18_X.1b" { |
| @ X.1b: off 0.005 grid vhvi vertex |
| OFFGRID vhvi 5 |
| } |
| "r_19_X.1b" { |
| @ X.1b: off 0.005 grid via2 vertex |
| OFFGRID via2 5 |
| } |
| "r_20_X.1b" { |
| @ X.1b: off 0.005 grid met3 vertex |
| OFFGRID met3 5 |
| } |
| "r_21_X.1b" { |
| @ X.1b: off 0.005 grid via3 vertex |
| OFFGRID via3 5 |
| } |
| "r_22_X.1b" { |
| @ X.1b: off 0.005 grid met4 vertex |
| OFFGRID met4 5 |
| } |
| "r_23_X.1b" { |
| @ X.1b: off 0.005 grid via4 vertex |
| OFFGRID via4 5 |
| } |
| "r_24_X.1b" { |
| @ X.1b: off 0.005 grid met5 vertex |
| OFFGRID met5 5 |
| } |
| "r_25_X.1b" { |
| @ X.1b: off 0.005 grid nsm vertex |
| OFFGRID nsm 5 |
| } |
| "r_26_X.1b" { |
| @ X.1b: off 0.005 grid pad vertex |
| OFFGRID pad 5 |
| } |
| "r_27_X.1b" { |
| @ X.1b: off 0.005 grid ldntm vertex |
| OFFGRID ldntm 5 |
| } |
| "r_28_X.1b" { |
| @ X.1b: off 0.005 grid hvntm vertex |
| OFFGRID hvntm 5 |
| } |
| "r_29_X.1b" { |
| @ X.1b: off 0.005 grid pnp vertex |
| OFFGRID pnp 5 |
| } |
| "r_30_X.1b" { |
| @ X.1b: off 0.005 grid capacitor vertex |
| OFFGRID capacitor 5 |
| } |
| "r_31_X.1b" { |
| @ X.1b: off 0.005 grid ncm vertex |
| OFFGRID ncm 5 |
| } |
| "r_32_X.1b" { |
| @ X.1b: off 0.005 grid inductor vertex |
| OFFGRID inductor 5 |
| } |
| "r_33_X.1b" { |
| @ X.1b: off 0.005 grid rpm vertex |
| OFFGRID rpm 5 |
| } |
| "r_34_X.1b" { |
| @ X.1b: off 0.005 grid hvtr vertex |
| OFFGRID hvtr 5 |
| } |
| "r_35_X.1b" { |
| @ X.1b: off 0.005 grid metop1 vertex |
| OFFGRID metop1 5 |
| } |
| "r_36_X.1b" { |
| @ X.1b: off 0.005 grid metop2 vertex |
| OFFGRID metop2 5 |
| } |
| "r_37_X.1b" { |
| @ X.1b: off 0.005 grid metop3 vertex |
| OFFGRID metop3 5 |
| } |
| "r_38_X.1b" { |
| @ X.1b: off 0.005 grid metop4 vertex |
| OFFGRID metop4 5 |
| } |
| "r_39_X.1b" { |
| @ X.1b: off 0.005 grid metop5 vertex |
| OFFGRID metop5 5 |
| } |
| "r_40_X.1b" { |
| @ X.1b: off 0.005 grid metop6 vertex |
| OFFGRID metop6 5 |
| } |
| "r_41_X.1b" { |
| @ X.1b: off 0.005 grid metop7 vertex |
| OFFGRID metop7 5 |
| } |
| "r_42_X.1b" { |
| @ X.1b: off 0.005 grid metop8 vertex |
| OFFGRID metop8 5 |
| } |
| "r_43_X.1b" { |
| @ X.1b: off 0.005 grid NTMdrop vertex |
| OFFGRID NTMdrop 5 |
| } |
| "r_44_X.1b" { |
| @ X.1b: off 0.005 grid LVTNMdrop vertex |
| OFFGRID LVTNMdrop 5 |
| } |
| "r_45_X.1b" { |
| @ X.1b: off 0.005 grid HVTPMdrop vertex |
| OFFGRID HVTPMdrop 5 |
| } |
| "r_46_X.1b" { |
| @ X.1b: off 0.005 grid LI1Mdrop vertex |
| OFFGRID LI1Mdrop 5 |
| } |
| "r_47_X.1b" { |
| @ X.1b: off 0.005 grid LICM1drop vertex |
| OFFGRID LICM1drop 5 |
| } |
| "r_48_X.1b" { |
| @ X.1b: off 0.005 grid PSDMdrop vertex |
| OFFGRID PSDMdrop 5 |
| } |
| "r_49_X.1b" { |
| @ X.1b: off 0.005 grid NSDMdrop vertex |
| OFFGRID NSDMdrop 5 |
| } |
| "r_50_X.1b" { |
| @ X.1b: off 0.005 grid FOMdrop vertex |
| OFFGRID FOMdrop 5 |
| } |
| "r_51_X.1b" { |
| @ X.1b: off 0.005 grid NTMadd vertex |
| OFFGRID NTMadd 5 |
| } |
| "r_52_X.1b" { |
| @ X.1b: off 0.005 grid LVTNMadd vertex |
| OFFGRID LVTNMadd 5 |
| } |
| "r_53_X.1b" { |
| @ X.1b: off 0.005 grid HVTPMadd vertex |
| OFFGRID HVTPMadd 5 |
| } |
| "r_54_X.1b" { |
| @ X.1b: off 0.005 grid LI1Madd vertex |
| OFFGRID LI1Madd 5 |
| } |
| "r_55_X.1b" { |
| @ X.1b: off 0.005 grid LICM1add vertex |
| OFFGRID LICM1add 5 |
| } |
| "r_56_X.1b" { |
| @ X.1b: off 0.005 grid PSDMadd vertex |
| OFFGRID PSDMadd 5 |
| } |
| "r_57_X.1b" { |
| @ X.1b: off 0.005 grid NSDMadd vertex |
| OFFGRID NSDMadd 5 |
| } |
| "r_58_X.1b" { |
| @ X.1b: off 0.005 grid FOMadd vertex |
| OFFGRID FOMadd 5 |
| } |
| "r_59_X.1b" { |
| @ X.1b: off 0.005 grid PMM2mk vertex |
| OFFGRID PMM2mk 5 |
| } |
| "r_60_X.1b" { |
| @ X.1b: off 0.005 grid CU1Mmk vertex |
| OFFGRID CU1Mmk 5 |
| } |
| "r_61_X.1b" { |
| @ X.1b: off 0.005 grid RPMmk vertex |
| OFFGRID RPMmk 5 |
| } |
| "r_62_X.1b" { |
| @ X.1b: off 0.005 grid PBOmk vertex |
| OFFGRID PBOmk 5 |
| } |
| "r_63_X.1b" { |
| @ X.1b: off 0.005 grid PDMmk vertex |
| OFFGRID PDMmk 5 |
| } |
| "r_64_X.1b" { |
| @ X.1b: off 0.005 grid NSMmk vertex |
| OFFGRID NSMmk 5 |
| } |
| "r_65_X.1b" { |
| @ X.1b: off 0.005 grid MM5mk vertex |
| OFFGRID MM5mk 5 |
| } |
| "r_66_X.1b" { |
| @ X.1b: off 0.005 grid VIM4mk vertex |
| OFFGRID VIM4mk 5 |
| } |
| "r_67_X.1b" { |
| @ X.1b: off 0.005 grid MM4mk vertex |
| OFFGRID MM4mk 5 |
| } |
| "r_68_X.1b" { |
| @ X.1b: off 0.005 grid VIM3mk vertex |
| OFFGRID VIM3mk 5 |
| } |
| "r_69_X.1b" { |
| @ X.1b: off 0.005 grid MM3mk vertex |
| OFFGRID MM3mk 5 |
| } |
| "r_70_X.1b" { |
| @ X.1b: off 0.005 grid VIM2mk vertex |
| OFFGRID VIM2mk 5 |
| } |
| "r_71_X.1b" { |
| @ X.1b: off 0.005 grid CTM1mk vertex |
| OFFGRID CTM1mk 5 |
| } |
| "r_72_X.1b" { |
| @ X.1b: off 0.005 grid LI1Mmk vertex |
| OFFGRID LI1Mmk 5 |
| } |
| "r_73_X.1b" { |
| @ X.1b: off 0.005 grid LICM1mk vertex |
| OFFGRID LICM1mk 5 |
| } |
| "r_74_X.1b" { |
| @ X.1b: off 0.005 grid PSDMmk vertex |
| OFFGRID PSDMmk 5 |
| } |
| "r_75_X.1b" { |
| @ X.1b: off 0.005 grid NSDMmk vertex |
| OFFGRID NSDMmk 5 |
| } |
| "r_76_X.1b" { |
| @ X.1b: off 0.005 grid LDNTMmk vertex |
| OFFGRID LDNTMmk 5 |
| } |
| "r_77_X.1b" { |
| @ X.1b: off 0.005 grid NPCMmk vertex |
| OFFGRID NPCMmk 5 |
| } |
| "r_78_X.1b" { |
| @ X.1b: off 0.005 grid HVNTMmk vertex |
| OFFGRID HVNTMmk 5 |
| } |
| "r_79_X.1b" { |
| @ X.1b: off 0.005 grid NTMmk vertex |
| OFFGRID NTMmk 5 |
| } |
| "r_80_X.1b" { |
| @ X.1b: off 0.005 grid LVOMmk vertex |
| OFFGRID LVOMmk 5 |
| } |
| "r_81_X.1b" { |
| @ X.1b: off 0.005 grid ONOMmk vertex |
| OFFGRID ONOMmk 5 |
| } |
| "r_82_X.1b" { |
| @ X.1b: off 0.005 grid TUNMmk vertex |
| OFFGRID TUNMmk 5 |
| } |
| "r_83_X.1b" { |
| @ X.1b: off 0.005 grid HVTRMmk vertex |
| OFFGRID HVTRMmk 5 |
| } |
| "r_84_X.1b" { |
| @ X.1b: off 0.005 grid HVTPMmk vertex |
| OFFGRID HVTPMmk 5 |
| } |
| "r_85_X.1b" { |
| @ X.1b: off 0.005 grid LVTNMmk vertex |
| OFFGRID LVTNMmk 5 |
| } |
| "r_86_X.1b" { |
| @ X.1b: off 0.005 grid NWMmk vertex |
| OFFGRID NWMmk 5 |
| } |
| "r_87_X.1b" { |
| @ X.1b: off 0.005 grid DNMmk vertex |
| OFFGRID DNMmk 5 |
| } |
| "r_88_X.1b" { |
| @ X.1b: off 0.005 grid FOMmk vertex |
| OFFGRID FOMmk 5 |
| } |
| "r_89_X.1b" { |
| @ X.1b: off 0.005 grid cfom vertex |
| OFFGRID cfom 5 |
| } |
| "r_90_X.1b" { |
| @ X.1b: off 0.005 grid clvtnm vertex |
| OFFGRID clvtnm 5 |
| } |
| "r_91_X.1b" { |
| @ X.1b: off 0.005 grid chvtpm vertex |
| OFFGRID chvtpm 5 |
| } |
| "r_92_X.1b" { |
| @ X.1b: off 0.005 grid conom vertex |
| OFFGRID conom 5 |
| } |
| "r_93_X.1b" { |
| @ X.1b: off 0.005 grid clvom vertex |
| OFFGRID clvom 5 |
| } |
| "r_94_X.1b" { |
| @ X.1b: off 0.005 grid cntm vertex |
| OFFGRID cntm 5 |
| } |
| "r_95_X.1b" { |
| @ X.1b: off 0.005 grid chvntm vertex |
| OFFGRID chvntm 5 |
| } |
| "r_96_X.1b" { |
| @ X.1b: off 0.005 grid cnpc vertex |
| OFFGRID cnpc 5 |
| } |
| "r_97_X.1b" { |
| @ X.1b: off 0.005 grid cnsdm vertex |
| OFFGRID cnsdm 5 |
| } |
| "r_98_X.1b" { |
| @ X.1b: off 0.005 grid cpsdm vertex |
| OFFGRID cpsdm 5 |
| } |
| "r_99_X.1b" { |
| @ X.1b: off 0.005 grid cli1m vertex |
| OFFGRID cli1m 5 |
| } |
| "r_100_X.1b" { |
| @ X.1b: off 0.005 grid cviam3 vertex |
| OFFGRID cviam3 5 |
| } |
| "r_101_X.1b" { |
| @ X.1b: off 0.005 grid cviam4 vertex |
| OFFGRID cviam4 5 |
| } |
| "r_102_X.1a" { |
| @ X.1a: off 0.001 grid P1Mmk vertex |
| OFFGRID P1Mmk 1 |
| } |
| "r_103_X.1a" { |
| @ X.1a: off 0.001 grid P1Madd vertex |
| OFFGRID P1Madd 1 |
| } |
| "r_104_X.1a" { |
| @ X.1a: off 0.001 grid P1Mdrop vertex |
| OFFGRID P1Mdrop 1 |
| } |
| "r_105_X.1a" { |
| @ X.1a: off 0.001 grid VIMmk vertex |
| OFFGRID VIMmk 1 |
| } |
| "r_106_X.1a" { |
| @ X.1a: off 0.001 grid MM1mk vertex |
| OFFGRID MM1mk 1 |
| } |
| "r_107_X.1a" { |
| @ X.1a: off 0.001 grid MM2mk vertex |
| OFFGRID MM2mk 1 |
| } |
| "r_108_X.1a" { |
| @ X.1a: off 0.001 grid pmm vertex |
| OFFGRID pmm 1 |
| } |
| "r_109_X.1a" { |
| @ X.1a: off 0.001 grid rdl vertex |
| OFFGRID rdl 1 |
| } |
| "r_110_X.1a" { |
| @ X.1a: off 0.001 grid pmm2 vertex |
| OFFGRID pmm2 1 |
| } |
| "r_111_X.1a" { |
| @ X.1a: off 0.001 grid ubm vertex |
| OFFGRID ubm 1 |
| } |
| "r_112_X.1a" { |
| @ X.1a: off 0.001 grid bump vertex |
| OFFGRID bump 1 |
| } |
| //adding capm, cap2m |
| "r_113_X.1a" { |
| @ X.1: off 0.001 grid capm vertex |
| OFFGRID capm 1 |
| } |
| "r_114_X.1a" { |
| @ X.1: off 0.001 grid cap2m vertex |
| OFFGRID cap2m 1 |
| } |
| /// |
| diffNotAdvSeal6um = diff NOT (SEALID_6um OR diffRingSeal) |
| "r_113_X.2" { |
| @ X.2: non-manhattan diffNotAdvSeal6um edge |
| ANGLE diffNotAdvSeal6um > 0 < 90 |
| } |
| "r_114_X.2" { |
| @ X.2: non-manhattan tap_nonSEAL edge |
| ANGLE tap_nonSEAL > 0 < 90 |
| } |
| "r_115_X.2" { |
| @ X.2: non-manhattan poly_noESD_noAnch edge |
| ANGLE poly_noESD_noAnch > 0 < 90 |
| } |
| "r_116_X.2" { |
| @ X.2: non-manhattan li1Peri_noSEAL_noAnch edge |
| ANGLE li1Peri_noSEAL_noAnch > 0 < 90 |
| } |
| "r_117_X.2" { |
| @ X.2: non-manhattan licon_nonSEAL edge |
| ANGLE licon_nonSEAL > 0 < 90 |
| } |
| "r_118_X.2" { |
| @ X.2: non-manhattan mcon_nonSEAL edge |
| ANGLE mcon_nonSEAL > 0 < 90 |
| } |
| "r_119_X.2" { |
| @ X.2: non-manhattan via_nonSEAL edge |
| ANGLE via_nonSEAL > 0 < 90 |
| } |
| "r_120_X.2" { |
| @ X.2: non-manhattan via2_nonSEAL edge |
| ANGLE via2_nonSEAL > 0 < 90 |
| } |
| "r_121_X.2" { |
| @ X.2: non-manhattan via3_nonSEAL edge |
| ANGLE via3_nonSEAL > 0 < 90 |
| } |
| "r_122_X.2" { |
| @ X.2: non-manhattan via4_nonSEAL edge |
| ANGLE via4_nonSEAL > 0 < 90 |
| } |
| analog_difftap = diffTap INSIDE ANALOGID |
| bad_analog_difftap = NOT RECTANGLE analog_difftap |
| "r_123_X.2a" { |
| @ X.2a: difftap enclosed in areaid.analog must be rectangular |
| COPY bad_analog_difftap |
| } |
| "r_124_X.3a" { |
| @ X.3a: non-octagonal nwell edge |
| ANGLE nwell > 0 < 45 |
| ANGLE nwell > 45 < 90 |
| } |
| "r_125_X.3a" { |
| @ X.3a: non-octagonal diff edge |
| ANGLE diff > 0 < 45 |
| ANGLE diff > 45 < 90 |
| } |
| "r_126_X.3a" { |
| @ X.3a: non-octagonal dnwell edge |
| ANGLE dnwell > 0 < 45 |
| ANGLE dnwell > 45 < 90 |
| } |
| "r_127_X.3a" { |
| @ X.3a: non-octagonal lvtn edge |
| ANGLE lvtn > 0 < 45 |
| ANGLE lvtn > 45 < 90 |
| } |
| "r_128_X.3a" { |
| @ X.3a: non-octagonal hvtp edge |
| ANGLE hvtp > 0 < 45 |
| ANGLE hvtp > 45 < 90 |
| } |
| "r_129_X.3a" { |
| @ X.3a: non-octagonal hvi edge |
| ANGLE hvi > 0 < 45 |
| ANGLE hvi > 45 < 90 |
| } |
| "r_130_X.3a" { |
| @ X.3a: non-octagonal tunm edge |
| ANGLE tunm > 0 < 45 |
| ANGLE tunm > 45 < 90 |
| } |
| "r_131_X.3a" { |
| @ X.3a: non-octagonal npc edge |
| ANGLE npc > 0 < 45 |
| ANGLE npc > 45 < 90 |
| } |
| "r_132_X.3a" { |
| @ X.3a: non-octagonal nsdm edge |
| ANGLE nsdm > 0 < 45 |
| ANGLE nsdm > 45 < 90 |
| } |
| "r_133_X.3a" { |
| @ X.3a: non-octagonal psdm edge |
| ANGLE psdm > 0 < 45 |
| ANGLE psdm > 45 < 90 |
| } |
| "r_134_X.3a" { |
| @ X.3a: non-octagonal met1 edge |
| ANGLE met1 > 0 < 45 |
| ANGLE met1 > 45 < 90 |
| } |
| "r_135_X.3a" { |
| @ X.3a: non-octagonal met2 edge |
| ANGLE met2 > 0 < 45 |
| ANGLE met2 > 45 < 90 |
| } |
| "r_136_X.3a" { |
| @ X.3a: non-octagonal vhvi edge |
| ANGLE vhvi > 0 < 45 |
| ANGLE vhvi > 45 < 90 |
| } |
| "r_137_X.3a" { |
| @ X.3a: non-octagonal met3 edge |
| ANGLE met3 > 0 < 45 |
| ANGLE met3 > 45 < 90 |
| } |
| "r_138_X.3a" { |
| @ X.3a: non-octagonal met4 edge |
| ANGLE met4 > 0 < 45 |
| ANGLE met4 > 45 < 90 |
| } |
| "r_139_X.3a" { |
| @ X.3a: non-octagonal met5 edge |
| ANGLE met5 > 0 < 45 |
| ANGLE met5 > 45 < 90 |
| } |
| "r_140_X.3a" { |
| @ X.3a: non-octagonal nsm edge |
| ANGLE nsm > 0 < 45 |
| ANGLE nsm > 45 < 90 |
| } |
| "r_141_X.3a" { |
| @ X.3a: non-octagonal pad edge |
| ANGLE pad > 0 < 45 |
| ANGLE pad > 45 < 90 |
| } |
| "r_142_X.3a" { |
| @ X.3a: non-octagonal ldntm edge |
| ANGLE ldntm > 0 < 45 |
| ANGLE ldntm > 45 < 90 |
| } |
| "r_143_X.3a" { |
| @ X.3a: non-octagonal hvntm edge |
| ANGLE hvntm > 0 < 45 |
| ANGLE hvntm > 45 < 90 |
| } |
| "r_144_X.3a" { |
| @ X.3a: non-octagonal pnp edge |
| ANGLE pnp > 0 < 45 |
| ANGLE pnp > 45 < 90 |
| } |
| "r_145_X.3a" { |
| @ X.3a: non-octagonal capacitor edge |
| ANGLE capacitor > 0 < 45 |
| ANGLE capacitor > 45 < 90 |
| } |
| "r_146_X.3a" { |
| @ X.3a: non-octagonal ncm edge |
| ANGLE ncm > 0 < 45 |
| ANGLE ncm > 45 < 90 |
| } |
| "r_147_X.3a" { |
| @ X.3a: non-octagonal inductor edge |
| ANGLE inductor > 0 < 45 |
| ANGLE inductor > 45 < 90 |
| } |
| "r_148_X.3a" { |
| @ X.3a: non-octagonal rpm edge |
| ANGLE rpm > 0 < 45 |
| ANGLE rpm > 45 < 90 |
| } |
| "r_149_X.3a" { |
| @ X.3a: non-octagonal hvtr edge |
| ANGLE hvtr > 0 < 45 |
| ANGLE hvtr > 45 < 90 |
| } |
| "r_150_X.3a" { |
| @ X.3a: non-octagonal metop1 edge |
| ANGLE metop1 > 0 < 45 |
| ANGLE metop1 > 45 < 90 |
| } |
| "r_151_X.3a" { |
| @ X.3a: non-octagonal metop2 edge |
| ANGLE metop2 > 0 < 45 |
| ANGLE metop2 > 45 < 90 |
| } |
| "r_152_X.3a" { |
| @ X.3a: non-octagonal metop3 edge |
| ANGLE metop3 > 0 < 45 |
| ANGLE metop3 > 45 < 90 |
| } |
| "r_153_X.3a" { |
| @ X.3a: non-octagonal metop4 edge |
| ANGLE metop4 > 0 < 45 |
| ANGLE metop4 > 45 < 90 |
| } |
| "r_154_X.3a" { |
| @ X.3a: non-octagonal metop5 edge |
| ANGLE metop5 > 0 < 45 |
| ANGLE metop5 > 45 < 90 |
| } |
| "r_155_X.3a" { |
| @ X.3a: non-octagonal metop6 edge |
| ANGLE metop6 > 0 < 45 |
| ANGLE metop6 > 45 < 90 |
| } |
| "r_156_X.3a" { |
| @ X.3a: non-octagonal metop7 edge |
| ANGLE metop7 > 0 < 45 |
| ANGLE metop7 > 45 < 90 |
| } |
| "r_157_X.3a" { |
| @ X.3a: non-octagonal metop8 edge |
| ANGLE metop8 > 0 < 45 |
| ANGLE metop8 > 45 < 90 |
| } |
| "r_158_X.3a" { |
| @ X.3a: non-octagonal NTMdrop edge |
| ANGLE NTMdrop > 0 < 45 |
| ANGLE NTMdrop > 45 < 90 |
| } |
| "r_159_X.3a" { |
| @ X.3a: non-octagonal LVTNMdrop edge |
| ANGLE LVTNMdrop > 0 < 45 |
| ANGLE LVTNMdrop > 45 < 90 |
| } |
| "r_160_X.3a" { |
| @ X.3a: non-octagonal HVTPMdrop edge |
| ANGLE HVTPMdrop > 0 < 45 |
| ANGLE HVTPMdrop > 45 < 90 |
| } |
| "r_161_X.3a" { |
| @ X.3a: non-octagonal LI1Mdrop edge |
| ANGLE LI1Mdrop > 0 < 45 |
| ANGLE LI1Mdrop > 45 < 90 |
| } |
| "r_162_X.3a" { |
| @ X.3a: non-octagonal LICM1drop edge |
| ANGLE LICM1drop > 0 < 45 |
| ANGLE LICM1drop > 45 < 90 |
| } |
| "r_163_X.3a" { |
| @ X.3a: non-octagonal PSDMdrop edge |
| ANGLE PSDMdrop > 0 < 45 |
| ANGLE PSDMdrop > 45 < 90 |
| } |
| "r_164_X.3a" { |
| @ X.3a: non-octagonal NSDMdrop edge |
| ANGLE NSDMdrop > 0 < 45 |
| ANGLE NSDMdrop > 45 < 90 |
| } |
| "r_165_X.3a" { |
| @ X.3a: non-octagonal P1Mdrop edge |
| ANGLE P1Mdrop > 0 < 45 |
| ANGLE P1Mdrop > 45 < 90 |
| } |
| "r_166_X.3a" { |
| @ X.3a: non-octagonal FOMdrop edge |
| ANGLE FOMdrop > 0 < 45 |
| ANGLE FOMdrop > 45 < 90 |
| } |
| "r_167_X.3a" { |
| @ X.3a: non-octagonal NTMadd edge |
| ANGLE NTMadd > 0 < 45 |
| ANGLE NTMadd > 45 < 90 |
| } |
| "r_168_X.3a" { |
| @ X.3a: non-octagonal LVTNMadd edge |
| ANGLE LVTNMadd > 0 < 45 |
| ANGLE LVTNMadd > 45 < 90 |
| } |
| "r_169_X.3a" { |
| @ X.3a: non-octagonal HVTPMadd edge |
| ANGLE HVTPMadd > 0 < 45 |
| ANGLE HVTPMadd > 45 < 90 |
| } |
| "r_170_X.3a" { |
| @ X.3a: non-octagonal LI1Madd edge |
| ANGLE LI1Madd > 0 < 45 |
| ANGLE LI1Madd > 45 < 90 |
| } |
| "r_171_X.3a" { |
| @ X.3a: non-octagonal LICM1add edge |
| ANGLE LICM1add > 0 < 45 |
| ANGLE LICM1add > 45 < 90 |
| } |
| "r_172_X.3a" { |
| @ X.3a: non-octagonal PSDMadd edge |
| ANGLE PSDMadd > 0 < 45 |
| ANGLE PSDMadd > 45 < 90 |
| } |
| "r_173_X.3a" { |
| @ X.3a: non-octagonal NSDMadd edge |
| ANGLE NSDMadd > 0 < 45 |
| ANGLE NSDMadd > 45 < 90 |
| } |
| "r_174_X.3a" { |
| @ X.3a: non-octagonal P1Madd edge |
| ANGLE P1Madd > 0 < 45 |
| ANGLE P1Madd > 45 < 90 |
| } |
| "r_175_X.3a" { |
| @ X.3a: non-octagonal FOMadd edge |
| ANGLE FOMadd > 0 < 45 |
| ANGLE FOMadd > 45 < 90 |
| } |
| "r_176_X.3a" { |
| @ X.3a: non-octagonal cfom edge |
| ANGLE cfom > 0 < 45 |
| ANGLE cfom > 45 < 90 |
| } |
| "r_177_X.3a" { |
| @ X.3a: non-octagonal clvtnm edge |
| ANGLE clvtnm > 0 < 45 |
| ANGLE clvtnm > 45 < 90 |
| } |
| "r_178_X.3a" { |
| @ X.3a: non-octagonal chvtpm edge |
| ANGLE chvtpm > 0 < 45 |
| ANGLE chvtpm > 45 < 90 |
| } |
| "r_179_X.3a" { |
| @ X.3a: non-octagonal conom edge |
| ANGLE conom > 0 < 45 |
| ANGLE conom > 45 < 90 |
| } |
| "r_180_X.3a" { |
| @ X.3a: non-octagonal clvom edge |
| ANGLE clvom > 0 < 45 |
| ANGLE clvom > 45 < 90 |
| } |
| "r_181_X.3a" { |
| @ X.3a: non-octagonal cntm edge |
| ANGLE cntm > 0 < 45 |
| ANGLE cntm > 45 < 90 |
| } |
| "r_182_X.3a" { |
| @ X.3a: non-octagonal chvntm edge |
| ANGLE chvntm > 0 < 45 |
| ANGLE chvntm > 45 < 90 |
| } |
| "r_183_X.3a" { |
| @ X.3a: non-octagonal cnpc edge |
| ANGLE cnpc > 0 < 45 |
| ANGLE cnpc > 45 < 90 |
| } |
| "r_184_X.3a" { |
| @ X.3a: non-octagonal cnsdm edge |
| ANGLE cnsdm > 0 < 45 |
| ANGLE cnsdm > 45 < 90 |
| } |
| "r_185_X.3a" { |
| @ X.3a: non-octagonal cpsdm edge |
| ANGLE cpsdm > 0 < 45 |
| ANGLE cpsdm > 45 < 90 |
| } |
| "r_186_X.3a" { |
| @ X.3a: non-octagonal cli1m edge |
| ANGLE cli1m > 0 < 45 |
| ANGLE cli1m > 45 < 90 |
| } |
| "r_187_X.3a" { |
| @ X.3a: non-octagonal cviam3 edge |
| ANGLE cviam3 > 0 < 45 |
| ANGLE cviam3 > 45 < 90 |
| } |
| "r_188_X.3a" { |
| @ X.3a: non-octagonal cviam4 edge |
| ANGLE cviam4 > 0 < 45 |
| ANGLE cviam4 > 45 < 90 |
| } |
| "r_189_X.3a" { |
| @ X.3a: non-octagonal PMM2mk edge |
| ANGLE PMM2mk > 0 < 45 |
| ANGLE PMM2mk > 45 < 90 |
| } |
| "r_190_X.3a" { |
| @ X.3a: non-octagonal CU1Mmk edge |
| ANGLE CU1Mmk > 0 < 45 |
| ANGLE CU1Mmk > 45 < 90 |
| } |
| "r_191_X.3a" { |
| @ X.3a: non-octagonal RPMmk edge |
| ANGLE RPMmk > 0 < 45 |
| ANGLE RPMmk > 45 < 90 |
| } |
| "r_192_X.3a" { |
| @ X.3a: non-octagonal PBOmk edge |
| ANGLE PBOmk > 0 < 45 |
| ANGLE PBOmk > 45 < 90 |
| } |
| "r_193_X.3a" { |
| @ X.3a: non-octagonal PDMmk edge |
| ANGLE PDMmk > 0 < 45 |
| ANGLE PDMmk > 45 < 90 |
| } |
| "r_194_X.3a" { |
| @ X.3a: non-octagonal NSMmk edge |
| ANGLE NSMmk > 0 < 45 |
| ANGLE NSMmk > 45 < 90 |
| } |
| "r_195_X.3a" { |
| @ X.3a: non-octagonal MM5mk edge |
| ANGLE MM5mk > 0 < 45 |
| ANGLE MM5mk > 45 < 90 |
| } |
| "r_196_X.3a" { |
| @ X.3a: non-octagonal VIM4mk edge |
| ANGLE VIM4mk > 0 < 45 |
| ANGLE VIM4mk > 45 < 90 |
| } |
| "r_197_X.3a" { |
| @ X.3a: non-octagonal MM4mk edge |
| ANGLE MM4mk > 0 < 45 |
| ANGLE MM4mk > 45 < 90 |
| } |
| "r_198_X.3a" { |
| @ X.3a: non-octagonal VIM3mk edge |
| ANGLE VIM3mk > 0 < 45 |
| ANGLE VIM3mk > 45 < 90 |
| } |
| "r_199_X.3a" { |
| @ X.3a: non-octagonal MM3mk edge |
| ANGLE MM3mk > 0 < 45 |
| ANGLE MM3mk > 45 < 90 |
| } |
| "r_200_X.3a" { |
| @ X.3a: non-octagonal VIM2mk edge |
| ANGLE VIM2mk > 0 < 45 |
| ANGLE VIM2mk > 45 < 90 |
| } |
| "r_201_X.3a" { |
| @ X.3a: non-octagonal MM2mk edge |
| ANGLE MM2mk > 0 < 45 |
| ANGLE MM2mk > 45 < 90 |
| } |
| "r_202_X.3a" { |
| @ X.3a: non-octagonal VIMmk edge |
| ANGLE VIMmk > 0 < 45 |
| ANGLE VIMmk > 45 < 90 |
| } |
| "r_203_X.3a" { |
| @ X.3a: non-octagonal MM1mk edge |
| ANGLE MM1mk > 0 < 45 |
| ANGLE MM1mk > 45 < 90 |
| } |
| "r_204_X.3a" { |
| @ X.3a: non-octagonal CTM1mk edge |
| ANGLE CTM1mk > 0 < 45 |
| ANGLE CTM1mk > 45 < 90 |
| } |
| "r_205_X.3a" { |
| @ X.3a: non-octagonal LI1Mmk edge |
| ANGLE LI1Mmk > 0 < 45 |
| ANGLE LI1Mmk > 45 < 90 |
| } |
| "r_206_X.3a" { |
| @ X.3a: non-octagonal LICM1mk edge |
| ANGLE LICM1mk > 0 < 45 |
| ANGLE LICM1mk > 45 < 90 |
| } |
| "r_207_X.3a" { |
| @ X.3a: non-octagonal PSDMmk edge |
| ANGLE PSDMmk > 0 < 45 |
| ANGLE PSDMmk > 45 < 90 |
| } |
| "r_208_X.3a" { |
| @ X.3a: non-octagonal NSDMmk edge |
| ANGLE NSDMmk > 0 < 45 |
| ANGLE NSDMmk > 45 < 90 |
| } |
| "r_209_X.3a" { |
| @ X.3a: non-octagonal LDNTMmk edge |
| ANGLE LDNTMmk > 0 < 45 |
| ANGLE LDNTMmk > 45 < 90 |
| } |
| "r_210_X.3a" { |
| @ X.3a: non-octagonal NPCMmk edge |
| ANGLE NPCMmk > 0 < 45 |
| ANGLE NPCMmk > 45 < 90 |
| } |
| "r_211_X.3a" { |
| @ X.3a: non-octagonal HVNTMmk edge |
| ANGLE HVNTMmk > 0 < 45 |
| ANGLE HVNTMmk > 45 < 90 |
| } |
| "r_212_X.3a" { |
| @ X.3a: non-octagonal NTMmk edge |
| ANGLE NTMmk > 0 < 45 |
| ANGLE NTMmk > 45 < 90 |
| } |
| "r_213_X.3a" { |
| @ X.3a: non-octagonal P1Mmk edge |
| ANGLE P1Mmk > 0 < 45 |
| ANGLE P1Mmk > 45 < 90 |
| } |
| "r_214_X.3a" { |
| @ X.3a: non-octagonal LVOMmk edge |
| ANGLE LVOMmk > 0 < 45 |
| ANGLE LVOMmk > 45 < 90 |
| } |
| "r_215_X.3a" { |
| @ X.3a: non-octagonal ONOMmk edge |
| ANGLE ONOMmk > 0 < 45 |
| ANGLE ONOMmk > 45 < 90 |
| } |
| "r_216_X.3a" { |
| @ X.3a: non-octagonal TUNMmk edge |
| ANGLE TUNMmk > 0 < 45 |
| ANGLE TUNMmk > 45 < 90 |
| } |
| "r_217_X.3a" { |
| @ X.3a: non-octagonal HVTRMmk edge |
| ANGLE HVTRMmk > 0 < 45 |
| ANGLE HVTRMmk > 45 < 90 |
| } |
| "r_218_X.3a" { |
| @ X.3a: non-octagonal HVTPMmk edge |
| ANGLE HVTPMmk > 0 < 45 |
| ANGLE HVTPMmk > 45 < 90 |
| } |
| "r_219_X.3a" { |
| @ X.3a: non-octagonal LVTNMmk edge |
| ANGLE LVTNMmk > 0 < 45 |
| ANGLE LVTNMmk > 45 < 90 |
| } |
| "r_220_X.3a" { |
| @ X.3a: non-octagonal NWMmk edge |
| ANGLE NWMmk > 0 < 45 |
| ANGLE NWMmk > 45 < 90 |
| } |
| "r_221_X.3a" { |
| @ X.3a: non-octagonal DNMmk edge |
| ANGLE DNMmk > 0 < 45 |
| ANGLE DNMmk > 45 < 90 |
| } |
| "r_222_X.3a" { |
| @ X.3a: non-octagonal FOMmk edge |
| ANGLE FOMmk > 0 < 45 |
| ANGLE FOMmk > 45 < 90 |
| } |
| "r_223_X.3a" { |
| @ X.3a: non-octagonal tap_SEAL edge |
| ANGLE tap_SEAL > 0 < 45 |
| ANGLE tap_SEAL > 45 < 90 |
| } |
| "r_224_X.3a" { |
| @ X.3a: non-octagonal tap_ENID edge |
| ANGLE tap_ENID > 0 < 45 |
| ANGLE tap_ENID > 45 < 90 |
| } |
| "r_225_X.3a" { |
| @ X.3a: non-octagonal poly_ESD edge |
| ANGLE poly_ESD > 0 < 45 |
| ANGLE poly_ESD > 45 < 90 |
| } |
| "r_226_X.3a" { |
| @ X.3a: non-octagonal "li1" in core edge |
| ANGLE li1_CORE > 0 < 45 |
| ANGLE li1_CORE > 45 < 90 |
| } |
| "r_227_X.3a" { |
| @ X.3a: non-octagonal li1_SEAL edge |
| ANGLE li1_SEAL > 0 < 45 |
| ANGLE li1_SEAL > 45 < 90 |
| } |
| "r_228_X.3a" { |
| @ X.3a: non-octagonal licon_SEAL edge |
| ANGLE licon_SEAL > 0 < 45 |
| ANGLE licon_SEAL > 45 < 90 |
| } |
| "r_229_X.3a" { |
| @ X.3a: non-octagonal mcon_SEAL edge |
| ANGLE mcon_SEAL > 0 < 45 |
| ANGLE mcon_SEAL > 45 < 90 |
| } |
| "r_230_X.3a" { |
| @ X.3a: non-octagonal via_SEAL edge |
| ANGLE via_SEAL > 0 < 45 |
| ANGLE via_SEAL > 45 < 90 |
| } |
| "r_231_X.3a" { |
| @ X.3a: non-octagonal via2_SEAL edge |
| ANGLE via2_SEAL > 0 < 45 |
| ANGLE via2_SEAL > 45 < 90 |
| } |
| "r_232_X.3a" { |
| @ X.3a: non-octagonal via3_SEAL edge |
| ANGLE via3_SEAL > 0 < 45 |
| ANGLE via3_SEAL > 45 < 90 |
| } |
| //adding capm, cap2m |
| "r_233_X.3a" { |
| @ X.3a: non-octagonal capm edge |
| ANGLE capm > 0 < 45 |
| ANGLE capm > 45 < 90 |
| } |
| "r_234_X.3a" { |
| @ X.3a: non-octagonal cap2m edge |
| ANGLE cap2m > 0 < 45 |
| ANGLE cap2m > 45 < 90 |
| } |
| |
| /// |
| /// X.4 is not checked |
| "r_233_X.5" { |
| @ X.5: met5Pin must be enclosed by met5 |
| met5Pin NOT met5 |
| } |
| "r_234_X.5" { |
| @ X.5: met4Pin must be enclosed by met4 |
| met4Pin NOT met4 |
| } |
| "r_235_X.5" { |
| @ X.5: met3Pin must be enclosed by met3 |
| met3Pin NOT met3 |
| } |
| "r_236_X.5" { |
| @ X.5: met2Pin must be enclosed by met2 |
| met2Pin NOT met2 |
| } |
| "r_237_X.5" { |
| @ X.5: met1Pin must be enclosed by met1 |
| met1Pin NOT met1 |
| } |
| "r_238_X.5" { |
| @ X.5: li1Pin must be enclosed by li1 |
| li1Pin NOT li1 |
| } |
| "r_239_X.5" { |
| @ X.5: polyPin must be enclosed by poly |
| polyPin NOT poly |
| } |
| "r_240_X.5" { |
| @ X.5: diffPin must be enclosed by diff |
| diffPin NOT diff |
| } |
| /// X.6 is handled by SpaceNotch checks |
| /// X.7 is handled by Final mask checks (s.* rules) |
| /// X.8 is not checked |
| "r_241_X.9" { |
| @ X.9: NTMdrop must be enclosed by COREID |
| NTMdrop NOT COREID |
| } |
| "r_242_X.9" { |
| @ X.9: LVTNMdrop must be enclosed by COREID |
| LVTNMdrop NOT COREID |
| } |
| "r_243_X.9" { |
| @ X.9: HVTPMdrop must be enclosed by COREID |
| HVTPMdrop NOT COREID |
| } |
| "r_244_X.9" { |
| @ X.9: LI1Mdrop must be enclosed by COREID |
| LI1Mdrop NOT COREID |
| } |
| "r_245_X.9" { |
| @ X.9: LICM1drop must be enclosed by COREID |
| LICM1drop NOT COREID |
| } |
| "r_246_X.9" { |
| @ X.9: PSDMdrop must be enclosed by COREID |
| PSDMdrop NOT COREID |
| } |
| "r_247_X.9" { |
| @ X.9: NSDMdrop must be enclosed by COREID |
| NSDMdrop NOT COREID |
| } |
| "r_248_X.9" { |
| @ X.9: P1Mdrop must be enclosed by COREID |
| P1Mdrop NOT COREID |
| } |
| "r_249_X.9" { |
| @ X.9: NTMadd must be enclosed by COREID |
| NTMadd NOT COREID |
| } |
| "r_250_X.9" { |
| @ X.9: LVTNMadd must be enclosed by COREID |
| LVTNMadd NOT COREID |
| } |
| "r_251_X.9" { |
| @ X.9: HVTPMadd must be enclosed by COREID |
| HVTPMadd NOT COREID |
| } |
| "r_252_X.9" { |
| @ X.9: LI1Madd must be enclosed by COREID |
| LI1Madd NOT COREID |
| } |
| "r_253_X.9" { |
| @ X.9: LICM1add must be enclosed by COREID |
| LICM1add NOT COREID |
| } |
| "r_254_X.9" { |
| @ X.9: PSDMadd must be enclosed by COREID |
| PSDMadd NOT COREID |
| } |
| "r_255_X.9" { |
| @ X.9: NSDMadd must be enclosed by COREID |
| NSDMadd NOT COREID |
| } |
| "r_256_X.9" { |
| @ X.9: P1Madd must be enclosed by COREID |
| P1Madd NOT COREID |
| } |
| "r_257_X.9" { |
| @ X.9: FOMadd must be enclosed by COREID |
| FOMadd NOT COREID |
| } |
| FOMdrop_noSeal = FOMdrop NOT SEALID_6um |
| "r_258_X.9" { |
| @ X.9: FOM outside advSeal_6um must be enclosed by COREID |
| FOMdrop_noSeal NOT COREID |
| } |
| "r_259_X.10" { |
| @ X.10: diffres must not overlap licon1 |
| diffres AND licon1 |
| } |
| "r_260_X.10" { |
| @ X.10: polyres must not overlap licon1 |
| polyres AND licon1 |
| } |
| /// X.11 is handled by lvs |
| CoreidOrStdcid = COREID OR STDCID |
| mcon_NOTAreaidStdCellCore = mcon NOT CoreidOrStdcid |
| q0_mcon_NOTAreaidStdCellCore_single_via = COPY q0_mcon_NOTAreaidStdCellCore_single_via_temp2 |
| q0_mcon_NOTAreaidStdCellCore_single_via_temp1 = mcon_NOTAreaidStdCellCore AND (INTERACT (li1 AND met1) mcon_NOTAreaidStdCellCore == 1) |
| q0_mcon_NOTAreaidStdCellCore_single_via_temp2 = RECTANGLE q0_mcon_NOTAreaidStdCellCore_single_via_temp1 ORTHOGONAL ONLY |
| q0_mcon_NOTAreaidStdCellCore_lay1_enc = SIZE q0_mcon_NOTAreaidStdCellCore_single_via BY 0 |
| q0_mcon_NOTAreaidStdCellCore_lay3_enc = SIZE q0_mcon_NOTAreaidStdCellCore_single_via BY 0.06 |
| q0_mcon_NOTAreaidStdCellCore_lay1_right = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via RIGHT BY 0.36) TOP BY 0 BOTTOM BY 0) NOT q0_mcon_NOTAreaidStdCellCore_lay1_enc |
| q0_mcon_NOTAreaidStdCellCore_lay3_right = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via RIGHT BY 0.42) TOP BY 0.06 BOTTOM BY 0.06) NOT q0_mcon_NOTAreaidStdCellCore_lay3_enc |
| q0_mcon_NOTAreaidStdCellCore_lay1_top = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via TOP BY 0.36) LEFT BY 0 RIGHT BY 0) NOT q0_mcon_NOTAreaidStdCellCore_lay1_enc |
| q0_mcon_NOTAreaidStdCellCore_lay3_top = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via TOP BY 0.42) LEFT BY 0.06 RIGHT BY 0.06) NOT q0_mcon_NOTAreaidStdCellCore_lay3_enc |
| q0_mcon_NOTAreaidStdCellCore_lay1_left = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via LEFT BY 0.36) TOP BY 0 BOTTOM BY 0) NOT q0_mcon_NOTAreaidStdCellCore_lay1_enc |
| q0_mcon_NOTAreaidStdCellCore_lay3_left = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via LEFT BY 0.42) TOP BY 0.06 BOTTOM BY 0.06) NOT q0_mcon_NOTAreaidStdCellCore_lay3_enc |
| q0_mcon_NOTAreaidStdCellCore_lay1_bott = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via BOTTOM BY 0.36) LEFT BY 0 RIGHT BY 0) NOT q0_mcon_NOTAreaidStdCellCore_lay1_enc |
| q0_mcon_NOTAreaidStdCellCore_lay3_bott = (GROW (GROW q0_mcon_NOTAreaidStdCellCore_single_via BOTTOM BY 0.42) LEFT BY 0.06 RIGHT BY 0.06) NOT q0_mcon_NOTAreaidStdCellCore_lay3_enc |
| q0_mcon_NOTAreaidStdCellCore_lay1_right_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay1_right (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay1_right_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay1_right_temp] (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) < 0.17 |
| q0_mcon_NOTAreaidStdCellCore_lay1_right_good = q0_mcon_NOTAreaidStdCellCore_lay1_right_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay1_right_edge |
| q0_mcon_NOTAreaidStdCellCore_lay3_right_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay3_right (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay3_right_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay3_right_temp] (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_mcon_NOTAreaidStdCellCore_lay3_right_good = q0_mcon_NOTAreaidStdCellCore_lay3_right_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay3_right_edge |
| q0_mcon_NOTAreaidStdCellCore_lay1_top_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay1_top (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay1_top_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay1_top_temp] (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) < 0.17 |
| q0_mcon_NOTAreaidStdCellCore_lay1_top_good = q0_mcon_NOTAreaidStdCellCore_lay1_top_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay1_top_edge |
| q0_mcon_NOTAreaidStdCellCore_lay3_top_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay3_top (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay3_top_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay3_top_temp] (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_mcon_NOTAreaidStdCellCore_lay3_top_good = q0_mcon_NOTAreaidStdCellCore_lay3_top_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay3_top_edge |
| q0_mcon_NOTAreaidStdCellCore_lay1_left_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay1_left (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay1_left_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay1_left_temp] (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) < 0.17 |
| q0_mcon_NOTAreaidStdCellCore_lay1_left_good = q0_mcon_NOTAreaidStdCellCore_lay1_left_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay1_left_edge |
| q0_mcon_NOTAreaidStdCellCore_lay3_left_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay3_left (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay3_left_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay3_left_temp] (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_mcon_NOTAreaidStdCellCore_lay3_left_good = q0_mcon_NOTAreaidStdCellCore_lay3_left_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay3_left_edge |
| q0_mcon_NOTAreaidStdCellCore_lay1_bott_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay1_bott (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay1_bott_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay1_bott_temp] (li1 OR q0_mcon_NOTAreaidStdCellCore_lay1_enc) < 0.17 |
| q0_mcon_NOTAreaidStdCellCore_lay1_bott_good = q0_mcon_NOTAreaidStdCellCore_lay1_bott_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay1_bott_edge |
| q0_mcon_NOTAreaidStdCellCore_lay3_bott_temp = INTERACT q0_mcon_NOTAreaidStdCellCore_lay3_bott (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_mcon_NOTAreaidStdCellCore_lay3_bott_edge = EXTERNAL [q0_mcon_NOTAreaidStdCellCore_lay3_bott_temp] (met1 OR q0_mcon_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_mcon_NOTAreaidStdCellCore_lay3_bott_good = q0_mcon_NOTAreaidStdCellCore_lay3_bott_temp NOT WITH EDGE q0_mcon_NOTAreaidStdCellCore_lay3_bott_edge |
| q0_mcon_NOTAreaidStdCellCore_temp1b = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay1_bott_good BOTTOM BY 0.17) LEFT BY 0.17 RIGHT BY 0.17 |
| q0_mcon_NOTAreaidStdCellCore_temp1r = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay1_right_good RIGHT BY 0.17) TOP BY 0.17 BOTTOM BY 0.17 |
| q0_mcon_NOTAreaidStdCellCore_temp1t = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay1_top_good TOP BY 0.17) LEFT BY 0.17 RIGHT BY 0.17 |
| q0_mcon_NOTAreaidStdCellCore_temp1l = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay1_left_good LEFT BY 0.17) TOP BY 0.17 BOTTOM BY 0.17 |
| q0_mcon_NOTAreaidStdCellCore_temp3b = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay3_bott_good BOTTOM BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_mcon_NOTAreaidStdCellCore_temp3r = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay3_right_good RIGHT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_mcon_NOTAreaidStdCellCore_temp3t = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay3_top_good TOP BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_mcon_NOTAreaidStdCellCore_temp3l = GROW (GROW q0_mcon_NOTAreaidStdCellCore_lay3_left_good LEFT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_mcon_NOTAreaidStdCellCore_final_lay1_r = q0_mcon_NOTAreaidStdCellCore_lay1_right_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp1t OR (q0_mcon_NOTAreaidStdCellCore_temp1l OR q0_mcon_NOTAreaidStdCellCore_temp1b)) |
| q0_mcon_NOTAreaidStdCellCore_final_lay3_r = q0_mcon_NOTAreaidStdCellCore_lay3_right_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp3t OR (q0_mcon_NOTAreaidStdCellCore_temp3l OR q0_mcon_NOTAreaidStdCellCore_temp3b)) |
| q0_mcon_NOTAreaidStdCellCore_temp1r2 = GROW (GROW q0_mcon_NOTAreaidStdCellCore_final_lay1_r TOP BY 0.17 BOTTOM BY 0.17) RIGHT BY 0.17 |
| q0_mcon_NOTAreaidStdCellCore_temp3r2 = GROW (GROW q0_mcon_NOTAreaidStdCellCore_final_lay3_r TOP BY 0.14 BOTTOM BY 0.14) RIGHT BY 0.14 |
| q0_mcon_NOTAreaidStdCellCore_final_lay1_t = q0_mcon_NOTAreaidStdCellCore_lay1_top_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp1r2 OR (q0_mcon_NOTAreaidStdCellCore_temp1l OR q0_mcon_NOTAreaidStdCellCore_temp1b)) |
| q0_mcon_NOTAreaidStdCellCore_final_lay3_t = q0_mcon_NOTAreaidStdCellCore_lay3_top_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp3r2 OR (q0_mcon_NOTAreaidStdCellCore_temp3l OR q0_mcon_NOTAreaidStdCellCore_temp3b)) |
| q0_mcon_NOTAreaidStdCellCore_temp1t2 = GROW (GROW q0_mcon_NOTAreaidStdCellCore_final_lay1_t LEFT BY 0.17 RIGHT BY 0.17) TOP BY 0.17 |
| q0_mcon_NOTAreaidStdCellCore_temp3t2 = GROW (GROW q0_mcon_NOTAreaidStdCellCore_final_lay3_t LEFT BY 0.14 RIGHT BY 0.14) TOP BY 0.14 |
| q0_mcon_NOTAreaidStdCellCore_final_lay1_l = q0_mcon_NOTAreaidStdCellCore_lay1_left_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp1r2 OR (q0_mcon_NOTAreaidStdCellCore_temp1t2 OR q0_mcon_NOTAreaidStdCellCore_temp1b)) |
| q0_mcon_NOTAreaidStdCellCore_final_lay3_l = q0_mcon_NOTAreaidStdCellCore_lay3_left_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp3r2 OR (q0_mcon_NOTAreaidStdCellCore_temp3t2 OR q0_mcon_NOTAreaidStdCellCore_temp3b)) |
| q0_mcon_NOTAreaidStdCellCore_temp1l2 = GROW (GROW q0_mcon_NOTAreaidStdCellCore_final_lay1_l TOP BY 0.17 BOTTOM BY 0.17) LEFT BY 0.17 |
| q0_mcon_NOTAreaidStdCellCore_temp3l2 = GROW (GROW q0_mcon_NOTAreaidStdCellCore_final_lay3_l TOP BY 0.14 BOTTOM BY 0.14) LEFT BY 0.14 |
| q0_mcon_NOTAreaidStdCellCore_final_lay1_b = q0_mcon_NOTAreaidStdCellCore_lay1_bott_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp1r2 OR (q0_mcon_NOTAreaidStdCellCore_temp1t2 OR q0_mcon_NOTAreaidStdCellCore_temp1l2)) |
| q0_mcon_NOTAreaidStdCellCore_final_lay3_b = q0_mcon_NOTAreaidStdCellCore_lay3_bott_good OUTSIDE (q0_mcon_NOTAreaidStdCellCore_temp3r2 OR (q0_mcon_NOTAreaidStdCellCore_temp3t2 OR q0_mcon_NOTAreaidStdCellCore_temp3l2)) |
| q0_mcon_NOTAreaidStdCellCore_tmp_vias = GROW q0_mcon_NOTAreaidStdCellCore_single_via RIGHT BY 0.36 TOP BY 0.36 LEFT BY 0.36 BOTTOM BY 0.36 |
| q0_mcon_NOTAreaidStdCellCore_new_vias = q0_mcon_NOTAreaidStdCellCore_tmp_vias NOT (GROW q0_mcon_NOTAreaidStdCellCore_single_via RIGHT BY 0.19 TOP BY 0.19 LEFT BY 0.19 BOTTOM BY 0.19) |
| q0_mcon_NOTAreaidStdCellCore_added_vias = q0_mcon_NOTAreaidStdCellCore_new_vias INSIDE ((q0_mcon_NOTAreaidStdCellCore_final_lay1_r AND q0_mcon_NOTAreaidStdCellCore_final_lay3_r) OR ((q0_mcon_NOTAreaidStdCellCore_final_lay1_t AND q0_mcon_NOTAreaidStdCellCore_final_lay3_t) OR ((q0_mcon_NOTAreaidStdCellCore_final_lay1_l AND q0_mcon_NOTAreaidStdCellCore_final_lay3_l) OR (q0_mcon_NOTAreaidStdCellCore_final_lay1_b AND q0_mcon_NOTAreaidStdCellCore_final_lay3_b)))) |
| q0_mcon_NOTAreaidStdCellCore_added_below = (INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay1_r q0_mcon_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay1_t q0_mcon_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay1_l q0_mcon_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay1_b q0_mcon_NOTAreaidStdCellCore_added_vias))) |
| q0_mcon_NOTAreaidStdCellCore_added_above = (INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay3_r q0_mcon_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay3_t q0_mcon_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay3_l q0_mcon_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_mcon_NOTAreaidStdCellCore_final_lay3_b q0_mcon_NOTAreaidStdCellCore_added_vias))) |
| q0_mcon_NOTAreaidStdCellCore_doubled_vias = INTERACT q0_mcon_NOTAreaidStdCellCore_single_via (TOUCH q0_mcon_NOTAreaidStdCellCore_lay1_enc q0_mcon_NOTAreaidStdCellCore_added_below) |
| "v_0_q0_mcon_NOTAreaidStdCellCore_added_vias" { |
| @ addedViaLayer: q0_mcon_NOTAreaidStdCellCore_added_vias - q0_mcon_NOTAreaidStdCellCore_added_vias |
| @ single mcon_NOTAreaidStdCellCore that can be doubled |
| COPY q0_mcon_NOTAreaidStdCellCore_added_vias |
| } |
| "v_1_q0_mcon_NOTAreaidStdCellCore_added_below" { |
| @ addedViaLayer: q0_mcon_NOTAreaidStdCellCore_added_below - q0_mcon_NOTAreaidStdCellCore_added_below |
| @ single mcon_NOTAreaidStdCellCore that can be doubled |
| COPY q0_mcon_NOTAreaidStdCellCore_added_below |
| } |
| "v_2_q0_mcon_NOTAreaidStdCellCore_added_above" { |
| @ addedViaLayer: q0_mcon_NOTAreaidStdCellCore_added_above - q0_mcon_NOTAreaidStdCellCore_added_above |
| @ single mcon_NOTAreaidStdCellCore that can be doubled |
| COPY q0_mcon_NOTAreaidStdCellCore_added_above |
| } |
| "s_0_X.18" { |
| @ single mcon_NOTAreaidStdCellCore that can be doubled |
| COPY q0_mcon_NOTAreaidStdCellCore_doubled_vias |
| } |
| via_NOTAreaidStdCellCore = via NOT CoreidOrStdcid |
| q0_via_NOTAreaidStdCellCore_single_via = COPY q0_via_NOTAreaidStdCellCore_single_via_temp2 |
| q0_via_NOTAreaidStdCellCore_single_via_temp1 = via_NOTAreaidStdCellCore AND (INTERACT (met1 AND met2) via_NOTAreaidStdCellCore == 1) |
| q0_via_NOTAreaidStdCellCore_single_via_temp2 = RECTANGLE q0_via_NOTAreaidStdCellCore_single_via_temp1 ORTHOGONAL ONLY |
| q0_via_NOTAreaidStdCellCore_lay1_enc = SIZE q0_via_NOTAreaidStdCellCore_single_via BY 0.085 |
| q0_via_NOTAreaidStdCellCore_lay3_enc = SIZE q0_via_NOTAreaidStdCellCore_single_via BY 0.085 |
| q0_via_NOTAreaidStdCellCore_lay1_right = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via RIGHT BY 0.405) TOP BY 0.085 BOTTOM BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay1_enc |
| q0_via_NOTAreaidStdCellCore_lay3_right = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via RIGHT BY 0.405) TOP BY 0.085 BOTTOM BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay3_enc |
| q0_via_NOTAreaidStdCellCore_lay1_top = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via TOP BY 0.405) LEFT BY 0.085 RIGHT BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay1_enc |
| q0_via_NOTAreaidStdCellCore_lay3_top = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via TOP BY 0.405) LEFT BY 0.085 RIGHT BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay3_enc |
| q0_via_NOTAreaidStdCellCore_lay1_left = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via LEFT BY 0.405) TOP BY 0.085 BOTTOM BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay1_enc |
| q0_via_NOTAreaidStdCellCore_lay3_left = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via LEFT BY 0.405) TOP BY 0.085 BOTTOM BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay3_enc |
| q0_via_NOTAreaidStdCellCore_lay1_bott = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via BOTTOM BY 0.405) LEFT BY 0.085 RIGHT BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay1_enc |
| q0_via_NOTAreaidStdCellCore_lay3_bott = (GROW (GROW q0_via_NOTAreaidStdCellCore_single_via BOTTOM BY 0.405) LEFT BY 0.085 RIGHT BY 0.085) NOT q0_via_NOTAreaidStdCellCore_lay3_enc |
| q0_via_NOTAreaidStdCellCore_lay1_right_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay1_right (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay1_right_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay1_right_temp] (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay1_right_good = q0_via_NOTAreaidStdCellCore_lay1_right_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay1_right_edge |
| q0_via_NOTAreaidStdCellCore_lay3_right_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay3_right (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay3_right_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay3_right_temp] (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay3_right_good = q0_via_NOTAreaidStdCellCore_lay3_right_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay3_right_edge |
| q0_via_NOTAreaidStdCellCore_lay1_top_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay1_top (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay1_top_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay1_top_temp] (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay1_top_good = q0_via_NOTAreaidStdCellCore_lay1_top_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay1_top_edge |
| q0_via_NOTAreaidStdCellCore_lay3_top_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay3_top (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay3_top_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay3_top_temp] (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay3_top_good = q0_via_NOTAreaidStdCellCore_lay3_top_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay3_top_edge |
| q0_via_NOTAreaidStdCellCore_lay1_left_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay1_left (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay1_left_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay1_left_temp] (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay1_left_good = q0_via_NOTAreaidStdCellCore_lay1_left_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay1_left_edge |
| q0_via_NOTAreaidStdCellCore_lay3_left_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay3_left (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay3_left_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay3_left_temp] (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay3_left_good = q0_via_NOTAreaidStdCellCore_lay3_left_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay3_left_edge |
| q0_via_NOTAreaidStdCellCore_lay1_bott_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay1_bott (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay1_bott_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay1_bott_temp] (met1 OR q0_via_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay1_bott_good = q0_via_NOTAreaidStdCellCore_lay1_bott_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay1_bott_edge |
| q0_via_NOTAreaidStdCellCore_lay3_bott_temp = INTERACT q0_via_NOTAreaidStdCellCore_lay3_bott (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via_NOTAreaidStdCellCore_lay3_bott_edge = EXTERNAL [q0_via_NOTAreaidStdCellCore_lay3_bott_temp] (met2 OR q0_via_NOTAreaidStdCellCore_lay3_enc) < 0.14 |
| q0_via_NOTAreaidStdCellCore_lay3_bott_good = q0_via_NOTAreaidStdCellCore_lay3_bott_temp NOT WITH EDGE q0_via_NOTAreaidStdCellCore_lay3_bott_edge |
| q0_via_NOTAreaidStdCellCore_temp1b = GROW (GROW q0_via_NOTAreaidStdCellCore_lay1_bott_good BOTTOM BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp1r = GROW (GROW q0_via_NOTAreaidStdCellCore_lay1_right_good RIGHT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp1t = GROW (GROW q0_via_NOTAreaidStdCellCore_lay1_top_good TOP BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp1l = GROW (GROW q0_via_NOTAreaidStdCellCore_lay1_left_good LEFT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp3b = GROW (GROW q0_via_NOTAreaidStdCellCore_lay3_bott_good BOTTOM BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp3r = GROW (GROW q0_via_NOTAreaidStdCellCore_lay3_right_good RIGHT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp3t = GROW (GROW q0_via_NOTAreaidStdCellCore_lay3_top_good TOP BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp3l = GROW (GROW q0_via_NOTAreaidStdCellCore_lay3_left_good LEFT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_via_NOTAreaidStdCellCore_final_lay1_r = q0_via_NOTAreaidStdCellCore_lay1_right_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp1t OR (q0_via_NOTAreaidStdCellCore_temp1l OR q0_via_NOTAreaidStdCellCore_temp1b)) |
| q0_via_NOTAreaidStdCellCore_final_lay3_r = q0_via_NOTAreaidStdCellCore_lay3_right_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp3t OR (q0_via_NOTAreaidStdCellCore_temp3l OR q0_via_NOTAreaidStdCellCore_temp3b)) |
| q0_via_NOTAreaidStdCellCore_temp1r2 = GROW (GROW q0_via_NOTAreaidStdCellCore_final_lay1_r TOP BY 0.14 BOTTOM BY 0.14) RIGHT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp3r2 = GROW (GROW q0_via_NOTAreaidStdCellCore_final_lay3_r TOP BY 0.14 BOTTOM BY 0.14) RIGHT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_final_lay1_t = q0_via_NOTAreaidStdCellCore_lay1_top_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp1r2 OR (q0_via_NOTAreaidStdCellCore_temp1l OR q0_via_NOTAreaidStdCellCore_temp1b)) |
| q0_via_NOTAreaidStdCellCore_final_lay3_t = q0_via_NOTAreaidStdCellCore_lay3_top_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp3r2 OR (q0_via_NOTAreaidStdCellCore_temp3l OR q0_via_NOTAreaidStdCellCore_temp3b)) |
| q0_via_NOTAreaidStdCellCore_temp1t2 = GROW (GROW q0_via_NOTAreaidStdCellCore_final_lay1_t LEFT BY 0.14 RIGHT BY 0.14) TOP BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp3t2 = GROW (GROW q0_via_NOTAreaidStdCellCore_final_lay3_t LEFT BY 0.14 RIGHT BY 0.14) TOP BY 0.14 |
| q0_via_NOTAreaidStdCellCore_final_lay1_l = q0_via_NOTAreaidStdCellCore_lay1_left_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp1r2 OR (q0_via_NOTAreaidStdCellCore_temp1t2 OR q0_via_NOTAreaidStdCellCore_temp1b)) |
| q0_via_NOTAreaidStdCellCore_final_lay3_l = q0_via_NOTAreaidStdCellCore_lay3_left_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp3r2 OR (q0_via_NOTAreaidStdCellCore_temp3t2 OR q0_via_NOTAreaidStdCellCore_temp3b)) |
| q0_via_NOTAreaidStdCellCore_temp1l2 = GROW (GROW q0_via_NOTAreaidStdCellCore_final_lay1_l TOP BY 0.14 BOTTOM BY 0.14) LEFT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_temp3l2 = GROW (GROW q0_via_NOTAreaidStdCellCore_final_lay3_l TOP BY 0.14 BOTTOM BY 0.14) LEFT BY 0.14 |
| q0_via_NOTAreaidStdCellCore_final_lay1_b = q0_via_NOTAreaidStdCellCore_lay1_bott_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp1r2 OR (q0_via_NOTAreaidStdCellCore_temp1t2 OR q0_via_NOTAreaidStdCellCore_temp1l2)) |
| q0_via_NOTAreaidStdCellCore_final_lay3_b = q0_via_NOTAreaidStdCellCore_lay3_bott_good OUTSIDE (q0_via_NOTAreaidStdCellCore_temp3r2 OR (q0_via_NOTAreaidStdCellCore_temp3t2 OR q0_via_NOTAreaidStdCellCore_temp3l2)) |
| q0_via_NOTAreaidStdCellCore_tmp_vias = GROW q0_via_NOTAreaidStdCellCore_single_via RIGHT BY 0.32 TOP BY 0.32 LEFT BY 0.32 BOTTOM BY 0.32 |
| q0_via_NOTAreaidStdCellCore_new_vias = q0_via_NOTAreaidStdCellCore_tmp_vias NOT (GROW q0_via_NOTAreaidStdCellCore_single_via RIGHT BY 0.17 TOP BY 0.17 LEFT BY 0.17 BOTTOM BY 0.17) |
| q0_via_NOTAreaidStdCellCore_added_vias = q0_via_NOTAreaidStdCellCore_new_vias INSIDE ((q0_via_NOTAreaidStdCellCore_final_lay1_r AND q0_via_NOTAreaidStdCellCore_final_lay3_r) OR ((q0_via_NOTAreaidStdCellCore_final_lay1_t AND q0_via_NOTAreaidStdCellCore_final_lay3_t) OR ((q0_via_NOTAreaidStdCellCore_final_lay1_l AND q0_via_NOTAreaidStdCellCore_final_lay3_l) OR (q0_via_NOTAreaidStdCellCore_final_lay1_b AND q0_via_NOTAreaidStdCellCore_final_lay3_b)))) |
| q0_via_NOTAreaidStdCellCore_added_below = (INTERACT q0_via_NOTAreaidStdCellCore_final_lay1_r q0_via_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via_NOTAreaidStdCellCore_final_lay1_t q0_via_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via_NOTAreaidStdCellCore_final_lay1_l q0_via_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via_NOTAreaidStdCellCore_final_lay1_b q0_via_NOTAreaidStdCellCore_added_vias))) |
| q0_via_NOTAreaidStdCellCore_added_above = (INTERACT q0_via_NOTAreaidStdCellCore_final_lay3_r q0_via_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via_NOTAreaidStdCellCore_final_lay3_t q0_via_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via_NOTAreaidStdCellCore_final_lay3_l q0_via_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via_NOTAreaidStdCellCore_final_lay3_b q0_via_NOTAreaidStdCellCore_added_vias))) |
| q0_via_NOTAreaidStdCellCore_doubled_vias = INTERACT q0_via_NOTAreaidStdCellCore_single_via (TOUCH q0_via_NOTAreaidStdCellCore_lay1_enc q0_via_NOTAreaidStdCellCore_added_below) |
| "v_3_q0_via_NOTAreaidStdCellCore_added_vias" { |
| @ addedViaLayer: q0_via_NOTAreaidStdCellCore_added_vias - q0_via_NOTAreaidStdCellCore_added_vias |
| @ single via_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via_NOTAreaidStdCellCore_added_vias |
| } |
| "v_4_q0_via_NOTAreaidStdCellCore_added_below" { |
| @ addedViaLayer: q0_via_NOTAreaidStdCellCore_added_below - q0_via_NOTAreaidStdCellCore_added_below |
| @ single via_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via_NOTAreaidStdCellCore_added_below |
| } |
| "v_5_q0_via_NOTAreaidStdCellCore_added_above" { |
| @ addedViaLayer: q0_via_NOTAreaidStdCellCore_added_above - q0_via_NOTAreaidStdCellCore_added_above |
| @ single via_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via_NOTAreaidStdCellCore_added_above |
| } |
| "s_1_X.18" { |
| @ single via_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via_NOTAreaidStdCellCore_doubled_vias |
| } |
| via2_NOTAreaidStdCellCore = via2 NOT CoreidOrStdcid |
| q0_via2_NOTAreaidStdCellCore_single_via = COPY q0_via2_NOTAreaidStdCellCore_single_via_temp2 |
| q0_via2_NOTAreaidStdCellCore_single_via_temp1 = via2_NOTAreaidStdCellCore AND (INTERACT (met2 AND met3) via2_NOTAreaidStdCellCore == 1) |
| q0_via2_NOTAreaidStdCellCore_single_via_temp2 = RECTANGLE q0_via2_NOTAreaidStdCellCore_single_via_temp1 ORTHOGONAL ONLY |
| q0_via2_NOTAreaidStdCellCore_lay1_enc = SIZE q0_via2_NOTAreaidStdCellCore_single_via BY 0.04 |
| q0_via2_NOTAreaidStdCellCore_lay3_enc = SIZE q0_via2_NOTAreaidStdCellCore_single_via BY 0.065 |
| q0_via2_NOTAreaidStdCellCore_lay1_right = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via RIGHT BY 0.44) TOP BY 0.04 BOTTOM BY 0.04) NOT q0_via2_NOTAreaidStdCellCore_lay1_enc |
| q0_via2_NOTAreaidStdCellCore_lay3_right = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via RIGHT BY 0.465) TOP BY 0.065 BOTTOM BY 0.065) NOT q0_via2_NOTAreaidStdCellCore_lay3_enc |
| q0_via2_NOTAreaidStdCellCore_lay1_top = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via TOP BY 0.44) LEFT BY 0.04 RIGHT BY 0.04) NOT q0_via2_NOTAreaidStdCellCore_lay1_enc |
| q0_via2_NOTAreaidStdCellCore_lay3_top = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via TOP BY 0.465) LEFT BY 0.065 RIGHT BY 0.065) NOT q0_via2_NOTAreaidStdCellCore_lay3_enc |
| q0_via2_NOTAreaidStdCellCore_lay1_left = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via LEFT BY 0.44) TOP BY 0.04 BOTTOM BY 0.04) NOT q0_via2_NOTAreaidStdCellCore_lay1_enc |
| q0_via2_NOTAreaidStdCellCore_lay3_left = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via LEFT BY 0.465) TOP BY 0.065 BOTTOM BY 0.065) NOT q0_via2_NOTAreaidStdCellCore_lay3_enc |
| q0_via2_NOTAreaidStdCellCore_lay1_bott = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via BOTTOM BY 0.44) LEFT BY 0.04 RIGHT BY 0.04) NOT q0_via2_NOTAreaidStdCellCore_lay1_enc |
| q0_via2_NOTAreaidStdCellCore_lay3_bott = (GROW (GROW q0_via2_NOTAreaidStdCellCore_single_via BOTTOM BY 0.465) LEFT BY 0.065 RIGHT BY 0.065) NOT q0_via2_NOTAreaidStdCellCore_lay3_enc |
| q0_via2_NOTAreaidStdCellCore_lay1_right_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay1_right (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay1_right_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay1_right_temp] (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via2_NOTAreaidStdCellCore_lay1_right_good = q0_via2_NOTAreaidStdCellCore_lay1_right_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay1_right_edge |
| q0_via2_NOTAreaidStdCellCore_lay3_right_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay3_right (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay3_right_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay3_right_temp] (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via2_NOTAreaidStdCellCore_lay3_right_good = q0_via2_NOTAreaidStdCellCore_lay3_right_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay3_right_edge |
| q0_via2_NOTAreaidStdCellCore_lay1_top_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay1_top (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay1_top_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay1_top_temp] (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via2_NOTAreaidStdCellCore_lay1_top_good = q0_via2_NOTAreaidStdCellCore_lay1_top_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay1_top_edge |
| q0_via2_NOTAreaidStdCellCore_lay3_top_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay3_top (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay3_top_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay3_top_temp] (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via2_NOTAreaidStdCellCore_lay3_top_good = q0_via2_NOTAreaidStdCellCore_lay3_top_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay3_top_edge |
| q0_via2_NOTAreaidStdCellCore_lay1_left_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay1_left (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay1_left_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay1_left_temp] (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via2_NOTAreaidStdCellCore_lay1_left_good = q0_via2_NOTAreaidStdCellCore_lay1_left_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay1_left_edge |
| q0_via2_NOTAreaidStdCellCore_lay3_left_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay3_left (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay3_left_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay3_left_temp] (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via2_NOTAreaidStdCellCore_lay3_left_good = q0_via2_NOTAreaidStdCellCore_lay3_left_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay3_left_edge |
| q0_via2_NOTAreaidStdCellCore_lay1_bott_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay1_bott (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay1_bott_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay1_bott_temp] (met2 OR q0_via2_NOTAreaidStdCellCore_lay1_enc) < 0.14 |
| q0_via2_NOTAreaidStdCellCore_lay1_bott_good = q0_via2_NOTAreaidStdCellCore_lay1_bott_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay1_bott_edge |
| q0_via2_NOTAreaidStdCellCore_lay3_bott_temp = INTERACT q0_via2_NOTAreaidStdCellCore_lay3_bott (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via2_NOTAreaidStdCellCore_lay3_bott_edge = EXTERNAL [q0_via2_NOTAreaidStdCellCore_lay3_bott_temp] (met3 OR q0_via2_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via2_NOTAreaidStdCellCore_lay3_bott_good = q0_via2_NOTAreaidStdCellCore_lay3_bott_temp NOT WITH EDGE q0_via2_NOTAreaidStdCellCore_lay3_bott_edge |
| q0_via2_NOTAreaidStdCellCore_temp1b = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay1_bott_good BOTTOM BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_via2_NOTAreaidStdCellCore_temp1r = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay1_right_good RIGHT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_via2_NOTAreaidStdCellCore_temp1t = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay1_top_good TOP BY 0.14) LEFT BY 0.14 RIGHT BY 0.14 |
| q0_via2_NOTAreaidStdCellCore_temp1l = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay1_left_good LEFT BY 0.14) TOP BY 0.14 BOTTOM BY 0.14 |
| q0_via2_NOTAreaidStdCellCore_temp3b = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay3_bott_good BOTTOM BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via2_NOTAreaidStdCellCore_temp3r = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay3_right_good RIGHT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via2_NOTAreaidStdCellCore_temp3t = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay3_top_good TOP BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via2_NOTAreaidStdCellCore_temp3l = GROW (GROW q0_via2_NOTAreaidStdCellCore_lay3_left_good LEFT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via2_NOTAreaidStdCellCore_final_lay1_r = q0_via2_NOTAreaidStdCellCore_lay1_right_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp1t OR (q0_via2_NOTAreaidStdCellCore_temp1l OR q0_via2_NOTAreaidStdCellCore_temp1b)) |
| q0_via2_NOTAreaidStdCellCore_final_lay3_r = q0_via2_NOTAreaidStdCellCore_lay3_right_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp3t OR (q0_via2_NOTAreaidStdCellCore_temp3l OR q0_via2_NOTAreaidStdCellCore_temp3b)) |
| q0_via2_NOTAreaidStdCellCore_temp1r2 = GROW (GROW q0_via2_NOTAreaidStdCellCore_final_lay1_r TOP BY 0.14 BOTTOM BY 0.14) RIGHT BY 0.14 |
| q0_via2_NOTAreaidStdCellCore_temp3r2 = GROW (GROW q0_via2_NOTAreaidStdCellCore_final_lay3_r TOP BY 0.3 BOTTOM BY 0.3) RIGHT BY 0.3 |
| q0_via2_NOTAreaidStdCellCore_final_lay1_t = q0_via2_NOTAreaidStdCellCore_lay1_top_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp1r2 OR (q0_via2_NOTAreaidStdCellCore_temp1l OR q0_via2_NOTAreaidStdCellCore_temp1b)) |
| q0_via2_NOTAreaidStdCellCore_final_lay3_t = q0_via2_NOTAreaidStdCellCore_lay3_top_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp3r2 OR (q0_via2_NOTAreaidStdCellCore_temp3l OR q0_via2_NOTAreaidStdCellCore_temp3b)) |
| q0_via2_NOTAreaidStdCellCore_temp1t2 = GROW (GROW q0_via2_NOTAreaidStdCellCore_final_lay1_t LEFT BY 0.14 RIGHT BY 0.14) TOP BY 0.14 |
| q0_via2_NOTAreaidStdCellCore_temp3t2 = GROW (GROW q0_via2_NOTAreaidStdCellCore_final_lay3_t LEFT BY 0.3 RIGHT BY 0.3) TOP BY 0.3 |
| q0_via2_NOTAreaidStdCellCore_final_lay1_l = q0_via2_NOTAreaidStdCellCore_lay1_left_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp1r2 OR (q0_via2_NOTAreaidStdCellCore_temp1t2 OR q0_via2_NOTAreaidStdCellCore_temp1b)) |
| q0_via2_NOTAreaidStdCellCore_final_lay3_l = q0_via2_NOTAreaidStdCellCore_lay3_left_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp3r2 OR (q0_via2_NOTAreaidStdCellCore_temp3t2 OR q0_via2_NOTAreaidStdCellCore_temp3b)) |
| q0_via2_NOTAreaidStdCellCore_temp1l2 = GROW (GROW q0_via2_NOTAreaidStdCellCore_final_lay1_l TOP BY 0.14 BOTTOM BY 0.14) LEFT BY 0.14 |
| q0_via2_NOTAreaidStdCellCore_temp3l2 = GROW (GROW q0_via2_NOTAreaidStdCellCore_final_lay3_l TOP BY 0.3 BOTTOM BY 0.3) LEFT BY 0.3 |
| q0_via2_NOTAreaidStdCellCore_final_lay1_b = q0_via2_NOTAreaidStdCellCore_lay1_bott_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp1r2 OR (q0_via2_NOTAreaidStdCellCore_temp1t2 OR q0_via2_NOTAreaidStdCellCore_temp1l2)) |
| q0_via2_NOTAreaidStdCellCore_final_lay3_b = q0_via2_NOTAreaidStdCellCore_lay3_bott_good OUTSIDE (q0_via2_NOTAreaidStdCellCore_temp3r2 OR (q0_via2_NOTAreaidStdCellCore_temp3t2 OR q0_via2_NOTAreaidStdCellCore_temp3l2)) |
| q0_via2_NOTAreaidStdCellCore_tmp_vias = GROW q0_via2_NOTAreaidStdCellCore_single_via RIGHT BY 0.4 TOP BY 0.4 LEFT BY 0.4 BOTTOM BY 0.4 |
| q0_via2_NOTAreaidStdCellCore_new_vias = q0_via2_NOTAreaidStdCellCore_tmp_vias NOT (GROW q0_via2_NOTAreaidStdCellCore_single_via RIGHT BY 0.2 TOP BY 0.2 LEFT BY 0.2 BOTTOM BY 0.2) |
| q0_via2_NOTAreaidStdCellCore_added_vias = q0_via2_NOTAreaidStdCellCore_new_vias INSIDE ((q0_via2_NOTAreaidStdCellCore_final_lay1_r AND q0_via2_NOTAreaidStdCellCore_final_lay3_r) OR ((q0_via2_NOTAreaidStdCellCore_final_lay1_t AND q0_via2_NOTAreaidStdCellCore_final_lay3_t) OR ((q0_via2_NOTAreaidStdCellCore_final_lay1_l AND q0_via2_NOTAreaidStdCellCore_final_lay3_l) OR (q0_via2_NOTAreaidStdCellCore_final_lay1_b AND q0_via2_NOTAreaidStdCellCore_final_lay3_b)))) |
| q0_via2_NOTAreaidStdCellCore_added_below = (INTERACT q0_via2_NOTAreaidStdCellCore_final_lay1_r q0_via2_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via2_NOTAreaidStdCellCore_final_lay1_t q0_via2_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via2_NOTAreaidStdCellCore_final_lay1_l q0_via2_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via2_NOTAreaidStdCellCore_final_lay1_b q0_via2_NOTAreaidStdCellCore_added_vias))) |
| q0_via2_NOTAreaidStdCellCore_added_above = (INTERACT q0_via2_NOTAreaidStdCellCore_final_lay3_r q0_via2_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via2_NOTAreaidStdCellCore_final_lay3_t q0_via2_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via2_NOTAreaidStdCellCore_final_lay3_l q0_via2_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via2_NOTAreaidStdCellCore_final_lay3_b q0_via2_NOTAreaidStdCellCore_added_vias))) |
| q0_via2_NOTAreaidStdCellCore_doubled_vias = INTERACT q0_via2_NOTAreaidStdCellCore_single_via (TOUCH q0_via2_NOTAreaidStdCellCore_lay1_enc q0_via2_NOTAreaidStdCellCore_added_below) |
| "v_6_q0_via2_NOTAreaidStdCellCore_added_vias" { |
| @ addedViaLayer: q0_via2_NOTAreaidStdCellCore_added_vias - q0_via2_NOTAreaidStdCellCore_added_vias |
| @ single via2_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via2_NOTAreaidStdCellCore_added_vias |
| } |
| "v_7_q0_via2_NOTAreaidStdCellCore_added_below" { |
| @ addedViaLayer: q0_via2_NOTAreaidStdCellCore_added_below - q0_via2_NOTAreaidStdCellCore_added_below |
| @ single via2_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via2_NOTAreaidStdCellCore_added_below |
| } |
| "v_8_q0_via2_NOTAreaidStdCellCore_added_above" { |
| @ addedViaLayer: q0_via2_NOTAreaidStdCellCore_added_above - q0_via2_NOTAreaidStdCellCore_added_above |
| @ single via2_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via2_NOTAreaidStdCellCore_added_above |
| } |
| "s_2_X.18" { |
| @ single via2_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via2_NOTAreaidStdCellCore_doubled_vias |
| } |
| via3_NOTAreaidStdCellCore = via3 NOT CoreidOrStdcid |
| q0_via3_NOTAreaidStdCellCore_single_via = COPY q0_via3_NOTAreaidStdCellCore_single_via_temp2 |
| q0_via3_NOTAreaidStdCellCore_single_via_temp1 = via3_NOTAreaidStdCellCore AND (INTERACT (met3 AND met4) via3_NOTAreaidStdCellCore == 1) |
| q0_via3_NOTAreaidStdCellCore_single_via_temp2 = RECTANGLE q0_via3_NOTAreaidStdCellCore_single_via_temp1 ORTHOGONAL ONLY |
| q0_via3_NOTAreaidStdCellCore_lay1_enc = SIZE q0_via3_NOTAreaidStdCellCore_single_via BY 0.06 |
| q0_via3_NOTAreaidStdCellCore_lay3_enc = SIZE q0_via3_NOTAreaidStdCellCore_single_via BY 0.065 |
| q0_via3_NOTAreaidStdCellCore_lay1_right = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via RIGHT BY 0.46) TOP BY 0.06 BOTTOM BY 0.06) NOT q0_via3_NOTAreaidStdCellCore_lay1_enc |
| q0_via3_NOTAreaidStdCellCore_lay3_right = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via RIGHT BY 0.465) TOP BY 0.065 BOTTOM BY 0.065) NOT q0_via3_NOTAreaidStdCellCore_lay3_enc |
| q0_via3_NOTAreaidStdCellCore_lay1_top = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via TOP BY 0.46) LEFT BY 0.06 RIGHT BY 0.06) NOT q0_via3_NOTAreaidStdCellCore_lay1_enc |
| q0_via3_NOTAreaidStdCellCore_lay3_top = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via TOP BY 0.465) LEFT BY 0.065 RIGHT BY 0.065) NOT q0_via3_NOTAreaidStdCellCore_lay3_enc |
| q0_via3_NOTAreaidStdCellCore_lay1_left = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via LEFT BY 0.46) TOP BY 0.06 BOTTOM BY 0.06) NOT q0_via3_NOTAreaidStdCellCore_lay1_enc |
| q0_via3_NOTAreaidStdCellCore_lay3_left = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via LEFT BY 0.465) TOP BY 0.065 BOTTOM BY 0.065) NOT q0_via3_NOTAreaidStdCellCore_lay3_enc |
| q0_via3_NOTAreaidStdCellCore_lay1_bott = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via BOTTOM BY 0.46) LEFT BY 0.06 RIGHT BY 0.06) NOT q0_via3_NOTAreaidStdCellCore_lay1_enc |
| q0_via3_NOTAreaidStdCellCore_lay3_bott = (GROW (GROW q0_via3_NOTAreaidStdCellCore_single_via BOTTOM BY 0.465) LEFT BY 0.065 RIGHT BY 0.065) NOT q0_via3_NOTAreaidStdCellCore_lay3_enc |
| q0_via3_NOTAreaidStdCellCore_lay1_right_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay1_right (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay1_right_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay1_right_temp] (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay1_right_good = q0_via3_NOTAreaidStdCellCore_lay1_right_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay1_right_edge |
| q0_via3_NOTAreaidStdCellCore_lay3_right_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay3_right (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay3_right_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay3_right_temp] (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay3_right_good = q0_via3_NOTAreaidStdCellCore_lay3_right_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay3_right_edge |
| q0_via3_NOTAreaidStdCellCore_lay1_top_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay1_top (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay1_top_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay1_top_temp] (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay1_top_good = q0_via3_NOTAreaidStdCellCore_lay1_top_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay1_top_edge |
| q0_via3_NOTAreaidStdCellCore_lay3_top_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay3_top (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay3_top_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay3_top_temp] (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay3_top_good = q0_via3_NOTAreaidStdCellCore_lay3_top_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay3_top_edge |
| q0_via3_NOTAreaidStdCellCore_lay1_left_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay1_left (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay1_left_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay1_left_temp] (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay1_left_good = q0_via3_NOTAreaidStdCellCore_lay1_left_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay1_left_edge |
| q0_via3_NOTAreaidStdCellCore_lay3_left_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay3_left (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay3_left_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay3_left_temp] (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay3_left_good = q0_via3_NOTAreaidStdCellCore_lay3_left_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay3_left_edge |
| q0_via3_NOTAreaidStdCellCore_lay1_bott_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay1_bott (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay1_bott_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay1_bott_temp] (met3 OR q0_via3_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay1_bott_good = q0_via3_NOTAreaidStdCellCore_lay1_bott_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay1_bott_edge |
| q0_via3_NOTAreaidStdCellCore_lay3_bott_temp = INTERACT q0_via3_NOTAreaidStdCellCore_lay3_bott (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via3_NOTAreaidStdCellCore_lay3_bott_edge = EXTERNAL [q0_via3_NOTAreaidStdCellCore_lay3_bott_temp] (met4 OR q0_via3_NOTAreaidStdCellCore_lay3_enc) < 0.3 |
| q0_via3_NOTAreaidStdCellCore_lay3_bott_good = q0_via3_NOTAreaidStdCellCore_lay3_bott_temp NOT WITH EDGE q0_via3_NOTAreaidStdCellCore_lay3_bott_edge |
| q0_via3_NOTAreaidStdCellCore_temp1b = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay1_bott_good BOTTOM BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp1r = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay1_right_good RIGHT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp1t = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay1_top_good TOP BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp1l = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay1_left_good LEFT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp3b = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay3_bott_good BOTTOM BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp3r = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay3_right_good RIGHT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp3t = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay3_top_good TOP BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp3l = GROW (GROW q0_via3_NOTAreaidStdCellCore_lay3_left_good LEFT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_final_lay1_r = q0_via3_NOTAreaidStdCellCore_lay1_right_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp1t OR (q0_via3_NOTAreaidStdCellCore_temp1l OR q0_via3_NOTAreaidStdCellCore_temp1b)) |
| q0_via3_NOTAreaidStdCellCore_final_lay3_r = q0_via3_NOTAreaidStdCellCore_lay3_right_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp3t OR (q0_via3_NOTAreaidStdCellCore_temp3l OR q0_via3_NOTAreaidStdCellCore_temp3b)) |
| q0_via3_NOTAreaidStdCellCore_temp1r2 = GROW (GROW q0_via3_NOTAreaidStdCellCore_final_lay1_r TOP BY 0.3 BOTTOM BY 0.3) RIGHT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp3r2 = GROW (GROW q0_via3_NOTAreaidStdCellCore_final_lay3_r TOP BY 0.3 BOTTOM BY 0.3) RIGHT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_final_lay1_t = q0_via3_NOTAreaidStdCellCore_lay1_top_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp1r2 OR (q0_via3_NOTAreaidStdCellCore_temp1l OR q0_via3_NOTAreaidStdCellCore_temp1b)) |
| q0_via3_NOTAreaidStdCellCore_final_lay3_t = q0_via3_NOTAreaidStdCellCore_lay3_top_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp3r2 OR (q0_via3_NOTAreaidStdCellCore_temp3l OR q0_via3_NOTAreaidStdCellCore_temp3b)) |
| q0_via3_NOTAreaidStdCellCore_temp1t2 = GROW (GROW q0_via3_NOTAreaidStdCellCore_final_lay1_t LEFT BY 0.3 RIGHT BY 0.3) TOP BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp3t2 = GROW (GROW q0_via3_NOTAreaidStdCellCore_final_lay3_t LEFT BY 0.3 RIGHT BY 0.3) TOP BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_final_lay1_l = q0_via3_NOTAreaidStdCellCore_lay1_left_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp1r2 OR (q0_via3_NOTAreaidStdCellCore_temp1t2 OR q0_via3_NOTAreaidStdCellCore_temp1b)) |
| q0_via3_NOTAreaidStdCellCore_final_lay3_l = q0_via3_NOTAreaidStdCellCore_lay3_left_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp3r2 OR (q0_via3_NOTAreaidStdCellCore_temp3t2 OR q0_via3_NOTAreaidStdCellCore_temp3b)) |
| q0_via3_NOTAreaidStdCellCore_temp1l2 = GROW (GROW q0_via3_NOTAreaidStdCellCore_final_lay1_l TOP BY 0.3 BOTTOM BY 0.3) LEFT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_temp3l2 = GROW (GROW q0_via3_NOTAreaidStdCellCore_final_lay3_l TOP BY 0.3 BOTTOM BY 0.3) LEFT BY 0.3 |
| q0_via3_NOTAreaidStdCellCore_final_lay1_b = q0_via3_NOTAreaidStdCellCore_lay1_bott_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp1r2 OR (q0_via3_NOTAreaidStdCellCore_temp1t2 OR q0_via3_NOTAreaidStdCellCore_temp1l2)) |
| q0_via3_NOTAreaidStdCellCore_final_lay3_b = q0_via3_NOTAreaidStdCellCore_lay3_bott_good OUTSIDE (q0_via3_NOTAreaidStdCellCore_temp3r2 OR (q0_via3_NOTAreaidStdCellCore_temp3t2 OR q0_via3_NOTAreaidStdCellCore_temp3l2)) |
| q0_via3_NOTAreaidStdCellCore_tmp_vias = GROW q0_via3_NOTAreaidStdCellCore_single_via RIGHT BY 0.4 TOP BY 0.4 LEFT BY 0.4 BOTTOM BY 0.4 |
| q0_via3_NOTAreaidStdCellCore_new_vias = q0_via3_NOTAreaidStdCellCore_tmp_vias NOT (GROW q0_via3_NOTAreaidStdCellCore_single_via RIGHT BY 0.2 TOP BY 0.2 LEFT BY 0.2 BOTTOM BY 0.2) |
| q0_via3_NOTAreaidStdCellCore_added_vias = q0_via3_NOTAreaidStdCellCore_new_vias INSIDE ((q0_via3_NOTAreaidStdCellCore_final_lay1_r AND q0_via3_NOTAreaidStdCellCore_final_lay3_r) OR ((q0_via3_NOTAreaidStdCellCore_final_lay1_t AND q0_via3_NOTAreaidStdCellCore_final_lay3_t) OR ((q0_via3_NOTAreaidStdCellCore_final_lay1_l AND q0_via3_NOTAreaidStdCellCore_final_lay3_l) OR (q0_via3_NOTAreaidStdCellCore_final_lay1_b AND q0_via3_NOTAreaidStdCellCore_final_lay3_b)))) |
| q0_via3_NOTAreaidStdCellCore_added_below = (INTERACT q0_via3_NOTAreaidStdCellCore_final_lay1_r q0_via3_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via3_NOTAreaidStdCellCore_final_lay1_t q0_via3_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via3_NOTAreaidStdCellCore_final_lay1_l q0_via3_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via3_NOTAreaidStdCellCore_final_lay1_b q0_via3_NOTAreaidStdCellCore_added_vias))) |
| q0_via3_NOTAreaidStdCellCore_added_above = (INTERACT q0_via3_NOTAreaidStdCellCore_final_lay3_r q0_via3_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via3_NOTAreaidStdCellCore_final_lay3_t q0_via3_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via3_NOTAreaidStdCellCore_final_lay3_l q0_via3_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via3_NOTAreaidStdCellCore_final_lay3_b q0_via3_NOTAreaidStdCellCore_added_vias))) |
| q0_via3_NOTAreaidStdCellCore_doubled_vias = INTERACT q0_via3_NOTAreaidStdCellCore_single_via (TOUCH q0_via3_NOTAreaidStdCellCore_lay1_enc q0_via3_NOTAreaidStdCellCore_added_below) |
| "v_9_q0_via3_NOTAreaidStdCellCore_added_vias" { |
| @ addedViaLayer: q0_via3_NOTAreaidStdCellCore_added_vias - q0_via3_NOTAreaidStdCellCore_added_vias |
| @ single via3_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via3_NOTAreaidStdCellCore_added_vias |
| } |
| "v_10_q0_via3_NOTAreaidStdCellCore_added_below" { |
| @ addedViaLayer: q0_via3_NOTAreaidStdCellCore_added_below - q0_via3_NOTAreaidStdCellCore_added_below |
| @ single via3_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via3_NOTAreaidStdCellCore_added_below |
| } |
| "v_11_q0_via3_NOTAreaidStdCellCore_added_above" { |
| @ addedViaLayer: q0_via3_NOTAreaidStdCellCore_added_above - q0_via3_NOTAreaidStdCellCore_added_above |
| @ single via3_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via3_NOTAreaidStdCellCore_added_above |
| } |
| "s_3_X.18" { |
| @ single via3_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via3_NOTAreaidStdCellCore_doubled_vias |
| } |
| via4_NOTAreaidStdCellCore = via4 NOT CoreidOrStdcid |
| q0_via4_NOTAreaidStdCellCore_single_via = COPY q0_via4_NOTAreaidStdCellCore_single_via_temp2 |
| q0_via4_NOTAreaidStdCellCore_single_via_temp1 = via4_NOTAreaidStdCellCore AND (INTERACT (met4 AND met5) via4_NOTAreaidStdCellCore == 1) |
| q0_via4_NOTAreaidStdCellCore_single_via_temp2 = RECTANGLE q0_via4_NOTAreaidStdCellCore_single_via_temp1 ORTHOGONAL ONLY |
| q0_via4_NOTAreaidStdCellCore_lay1_enc = SIZE q0_via4_NOTAreaidStdCellCore_single_via BY 0.19 |
| q0_via4_NOTAreaidStdCellCore_lay3_enc = SIZE q0_via4_NOTAreaidStdCellCore_single_via BY 0.31 |
| q0_via4_NOTAreaidStdCellCore_lay1_right = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via RIGHT BY 1.79) TOP BY 0.19 BOTTOM BY 0.19) NOT q0_via4_NOTAreaidStdCellCore_lay1_enc |
| q0_via4_NOTAreaidStdCellCore_lay3_right = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via RIGHT BY 1.91) TOP BY 0.31 BOTTOM BY 0.31) NOT q0_via4_NOTAreaidStdCellCore_lay3_enc |
| q0_via4_NOTAreaidStdCellCore_lay1_top = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via TOP BY 1.79) LEFT BY 0.19 RIGHT BY 0.19) NOT q0_via4_NOTAreaidStdCellCore_lay1_enc |
| q0_via4_NOTAreaidStdCellCore_lay3_top = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via TOP BY 1.91) LEFT BY 0.31 RIGHT BY 0.31) NOT q0_via4_NOTAreaidStdCellCore_lay3_enc |
| q0_via4_NOTAreaidStdCellCore_lay1_left = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via LEFT BY 1.79) TOP BY 0.19 BOTTOM BY 0.19) NOT q0_via4_NOTAreaidStdCellCore_lay1_enc |
| q0_via4_NOTAreaidStdCellCore_lay3_left = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via LEFT BY 1.91) TOP BY 0.31 BOTTOM BY 0.31) NOT q0_via4_NOTAreaidStdCellCore_lay3_enc |
| q0_via4_NOTAreaidStdCellCore_lay1_bott = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via BOTTOM BY 1.79) LEFT BY 0.19 RIGHT BY 0.19) NOT q0_via4_NOTAreaidStdCellCore_lay1_enc |
| q0_via4_NOTAreaidStdCellCore_lay3_bott = (GROW (GROW q0_via4_NOTAreaidStdCellCore_single_via BOTTOM BY 1.91) LEFT BY 0.31 RIGHT BY 0.31) NOT q0_via4_NOTAreaidStdCellCore_lay3_enc |
| q0_via4_NOTAreaidStdCellCore_lay1_right_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay1_right (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay1_right_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay1_right_temp] (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via4_NOTAreaidStdCellCore_lay1_right_good = q0_via4_NOTAreaidStdCellCore_lay1_right_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay1_right_edge |
| q0_via4_NOTAreaidStdCellCore_lay3_right_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay3_right (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay3_right_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay3_right_temp] (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) < 1.6 |
| q0_via4_NOTAreaidStdCellCore_lay3_right_good = q0_via4_NOTAreaidStdCellCore_lay3_right_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay3_right_edge |
| q0_via4_NOTAreaidStdCellCore_lay1_top_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay1_top (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay1_top_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay1_top_temp] (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via4_NOTAreaidStdCellCore_lay1_top_good = q0_via4_NOTAreaidStdCellCore_lay1_top_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay1_top_edge |
| q0_via4_NOTAreaidStdCellCore_lay3_top_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay3_top (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay3_top_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay3_top_temp] (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) < 1.6 |
| q0_via4_NOTAreaidStdCellCore_lay3_top_good = q0_via4_NOTAreaidStdCellCore_lay3_top_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay3_top_edge |
| q0_via4_NOTAreaidStdCellCore_lay1_left_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay1_left (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay1_left_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay1_left_temp] (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via4_NOTAreaidStdCellCore_lay1_left_good = q0_via4_NOTAreaidStdCellCore_lay1_left_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay1_left_edge |
| q0_via4_NOTAreaidStdCellCore_lay3_left_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay3_left (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay3_left_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay3_left_temp] (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) < 1.6 |
| q0_via4_NOTAreaidStdCellCore_lay3_left_good = q0_via4_NOTAreaidStdCellCore_lay3_left_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay3_left_edge |
| q0_via4_NOTAreaidStdCellCore_lay1_bott_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay1_bott (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay1_bott_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay1_bott_temp] (met4 OR q0_via4_NOTAreaidStdCellCore_lay1_enc) < 0.3 |
| q0_via4_NOTAreaidStdCellCore_lay1_bott_good = q0_via4_NOTAreaidStdCellCore_lay1_bott_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay1_bott_edge |
| q0_via4_NOTAreaidStdCellCore_lay3_bott_temp = INTERACT q0_via4_NOTAreaidStdCellCore_lay3_bott (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) == 1 |
| q0_via4_NOTAreaidStdCellCore_lay3_bott_edge = EXTERNAL [q0_via4_NOTAreaidStdCellCore_lay3_bott_temp] (met5 OR q0_via4_NOTAreaidStdCellCore_lay3_enc) < 1.6 |
| q0_via4_NOTAreaidStdCellCore_lay3_bott_good = q0_via4_NOTAreaidStdCellCore_lay3_bott_temp NOT WITH EDGE q0_via4_NOTAreaidStdCellCore_lay3_bott_edge |
| q0_via4_NOTAreaidStdCellCore_temp1b = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay1_bott_good BOTTOM BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via4_NOTAreaidStdCellCore_temp1r = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay1_right_good RIGHT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via4_NOTAreaidStdCellCore_temp1t = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay1_top_good TOP BY 0.3) LEFT BY 0.3 RIGHT BY 0.3 |
| q0_via4_NOTAreaidStdCellCore_temp1l = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay1_left_good LEFT BY 0.3) TOP BY 0.3 BOTTOM BY 0.3 |
| q0_via4_NOTAreaidStdCellCore_temp3b = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay3_bott_good BOTTOM BY 1.6) LEFT BY 1.6 RIGHT BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_temp3r = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay3_right_good RIGHT BY 1.6) TOP BY 1.6 BOTTOM BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_temp3t = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay3_top_good TOP BY 1.6) LEFT BY 1.6 RIGHT BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_temp3l = GROW (GROW q0_via4_NOTAreaidStdCellCore_lay3_left_good LEFT BY 1.6) TOP BY 1.6 BOTTOM BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_final_lay1_r = q0_via4_NOTAreaidStdCellCore_lay1_right_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp1t OR (q0_via4_NOTAreaidStdCellCore_temp1l OR q0_via4_NOTAreaidStdCellCore_temp1b)) |
| q0_via4_NOTAreaidStdCellCore_final_lay3_r = q0_via4_NOTAreaidStdCellCore_lay3_right_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp3t OR (q0_via4_NOTAreaidStdCellCore_temp3l OR q0_via4_NOTAreaidStdCellCore_temp3b)) |
| q0_via4_NOTAreaidStdCellCore_temp1r2 = GROW (GROW q0_via4_NOTAreaidStdCellCore_final_lay1_r TOP BY 0.3 BOTTOM BY 0.3) RIGHT BY 0.3 |
| q0_via4_NOTAreaidStdCellCore_temp3r2 = GROW (GROW q0_via4_NOTAreaidStdCellCore_final_lay3_r TOP BY 1.6 BOTTOM BY 1.6) RIGHT BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_final_lay1_t = q0_via4_NOTAreaidStdCellCore_lay1_top_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp1r2 OR (q0_via4_NOTAreaidStdCellCore_temp1l OR q0_via4_NOTAreaidStdCellCore_temp1b)) |
| q0_via4_NOTAreaidStdCellCore_final_lay3_t = q0_via4_NOTAreaidStdCellCore_lay3_top_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp3r2 OR (q0_via4_NOTAreaidStdCellCore_temp3l OR q0_via4_NOTAreaidStdCellCore_temp3b)) |
| q0_via4_NOTAreaidStdCellCore_temp1t2 = GROW (GROW q0_via4_NOTAreaidStdCellCore_final_lay1_t LEFT BY 0.3 RIGHT BY 0.3) TOP BY 0.3 |
| q0_via4_NOTAreaidStdCellCore_temp3t2 = GROW (GROW q0_via4_NOTAreaidStdCellCore_final_lay3_t LEFT BY 1.6 RIGHT BY 1.6) TOP BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_final_lay1_l = q0_via4_NOTAreaidStdCellCore_lay1_left_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp1r2 OR (q0_via4_NOTAreaidStdCellCore_temp1t2 OR q0_via4_NOTAreaidStdCellCore_temp1b)) |
| q0_via4_NOTAreaidStdCellCore_final_lay3_l = q0_via4_NOTAreaidStdCellCore_lay3_left_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp3r2 OR (q0_via4_NOTAreaidStdCellCore_temp3t2 OR q0_via4_NOTAreaidStdCellCore_temp3b)) |
| q0_via4_NOTAreaidStdCellCore_temp1l2 = GROW (GROW q0_via4_NOTAreaidStdCellCore_final_lay1_l TOP BY 0.3 BOTTOM BY 0.3) LEFT BY 0.3 |
| q0_via4_NOTAreaidStdCellCore_temp3l2 = GROW (GROW q0_via4_NOTAreaidStdCellCore_final_lay3_l TOP BY 1.6 BOTTOM BY 1.6) LEFT BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_final_lay1_b = q0_via4_NOTAreaidStdCellCore_lay1_bott_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp1r2 OR (q0_via4_NOTAreaidStdCellCore_temp1t2 OR q0_via4_NOTAreaidStdCellCore_temp1l2)) |
| q0_via4_NOTAreaidStdCellCore_final_lay3_b = q0_via4_NOTAreaidStdCellCore_lay3_bott_good OUTSIDE (q0_via4_NOTAreaidStdCellCore_temp3r2 OR (q0_via4_NOTAreaidStdCellCore_temp3t2 OR q0_via4_NOTAreaidStdCellCore_temp3l2)) |
| q0_via4_NOTAreaidStdCellCore_tmp_vias = GROW q0_via4_NOTAreaidStdCellCore_single_via RIGHT BY 1.6 TOP BY 1.6 LEFT BY 1.6 BOTTOM BY 1.6 |
| q0_via4_NOTAreaidStdCellCore_new_vias = q0_via4_NOTAreaidStdCellCore_tmp_vias NOT (GROW q0_via4_NOTAreaidStdCellCore_single_via RIGHT BY 0.8 TOP BY 0.8 LEFT BY 0.8 BOTTOM BY 0.8) |
| q0_via4_NOTAreaidStdCellCore_added_vias = q0_via4_NOTAreaidStdCellCore_new_vias INSIDE ((q0_via4_NOTAreaidStdCellCore_final_lay1_r AND q0_via4_NOTAreaidStdCellCore_final_lay3_r) OR ((q0_via4_NOTAreaidStdCellCore_final_lay1_t AND q0_via4_NOTAreaidStdCellCore_final_lay3_t) OR ((q0_via4_NOTAreaidStdCellCore_final_lay1_l AND q0_via4_NOTAreaidStdCellCore_final_lay3_l) OR (q0_via4_NOTAreaidStdCellCore_final_lay1_b AND q0_via4_NOTAreaidStdCellCore_final_lay3_b)))) |
| q0_via4_NOTAreaidStdCellCore_added_below = (INTERACT q0_via4_NOTAreaidStdCellCore_final_lay1_r q0_via4_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via4_NOTAreaidStdCellCore_final_lay1_t q0_via4_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via4_NOTAreaidStdCellCore_final_lay1_l q0_via4_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via4_NOTAreaidStdCellCore_final_lay1_b q0_via4_NOTAreaidStdCellCore_added_vias))) |
| q0_via4_NOTAreaidStdCellCore_added_above = (INTERACT q0_via4_NOTAreaidStdCellCore_final_lay3_r q0_via4_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via4_NOTAreaidStdCellCore_final_lay3_t q0_via4_NOTAreaidStdCellCore_added_vias) OR ((INTERACT q0_via4_NOTAreaidStdCellCore_final_lay3_l q0_via4_NOTAreaidStdCellCore_added_vias) OR (INTERACT q0_via4_NOTAreaidStdCellCore_final_lay3_b q0_via4_NOTAreaidStdCellCore_added_vias))) |
| q0_via4_NOTAreaidStdCellCore_doubled_vias = INTERACT q0_via4_NOTAreaidStdCellCore_single_via (TOUCH q0_via4_NOTAreaidStdCellCore_lay1_enc q0_via4_NOTAreaidStdCellCore_added_below) |
| "v_12_q0_via4_NOTAreaidStdCellCore_added_vias" { |
| @ addedViaLayer: q0_via4_NOTAreaidStdCellCore_added_vias - q0_via4_NOTAreaidStdCellCore_added_vias |
| @ single via4_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via4_NOTAreaidStdCellCore_added_vias |
| } |
| "v_13_q0_via4_NOTAreaidStdCellCore_added_below" { |
| @ addedViaLayer: q0_via4_NOTAreaidStdCellCore_added_below - q0_via4_NOTAreaidStdCellCore_added_below |
| @ single via4_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via4_NOTAreaidStdCellCore_added_below |
| } |
| "v_14_q0_via4_NOTAreaidStdCellCore_added_above" { |
| @ addedViaLayer: q0_via4_NOTAreaidStdCellCore_added_above - q0_via4_NOTAreaidStdCellCore_added_above |
| @ single via4_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via4_NOTAreaidStdCellCore_added_above |
| } |
| "s_4_X.18" { |
| @ single via4_NOTAreaidStdCellCore that can be doubled |
| COPY q0_via4_NOTAreaidStdCellCore_doubled_vias |
| } |
| buildSpace = EXTENT CELL "*_buildspace" ORIGINAL |
| q0nwellnotBuildSpace = nwell NOT buildSpace |
| "r_261_X.12a" { |
| @ X.12a: 0.635 min. spacing of moduleCutAREA & q0nwellnotBuildSpace |
| EXTERNAL moduleCutAREA q0nwellnotBuildSpace < 0.635 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_262_X.12b" { |
| @ X.12b: 0.635 min. enclosure of q0nwellnotBuildSpace by moduleCutAREA |
| q0nwellnotBuildSpaceand = q0nwellnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0nwellnotBuildSpaceand moduleCutAREA < 0.635 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0diffnotBuildSpace = diff NOT buildSpace |
| "r_263_X.12a" { |
| @ X.12a: 0.135 min. spacing of moduleCutAREA & q0diffnotBuildSpace |
| EXTERNAL moduleCutAREA q0diffnotBuildSpace < 0.135 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_264_X.12b" { |
| @ X.12b: 0.135 min. enclosure of q0diffnotBuildSpace by moduleCutAREA |
| q0diffnotBuildSpaceand = q0diffnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0diffnotBuildSpaceand moduleCutAREA < 0.135 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0dnwellnotBuildSpace = dnwell NOT buildSpace |
| "r_265_X.12a" { |
| @ X.12a: 3.15 min. spacing of moduleCutAREA & q0dnwellnotBuildSpace |
| EXTERNAL moduleCutAREA q0dnwellnotBuildSpace < 3.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_266_X.12b" { |
| @ X.12b: 3.15 min. enclosure of q0dnwellnotBuildSpace by moduleCutAREA |
| q0dnwellnotBuildSpaceand = q0dnwellnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0dnwellnotBuildSpaceand moduleCutAREA < 3.15 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0tapnotBuildSpace = tap NOT buildSpace |
| "r_267_X.12a" { |
| @ X.12a: 0.135 min. spacing of moduleCutAREA & q0tapnotBuildSpace |
| EXTERNAL moduleCutAREA q0tapnotBuildSpace < 0.135 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_268_X.12b" { |
| @ X.12b: 0.135 min. enclosure of q0tapnotBuildSpace by moduleCutAREA |
| q0tapnotBuildSpaceand = q0tapnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0tapnotBuildSpaceand moduleCutAREA < 0.135 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0lvtnnotBuildSpace = lvtn NOT buildSpace |
| "r_269_X.12a" { |
| @ X.12a: 0.19 min. spacing of moduleCutAREA & q0lvtnnotBuildSpace |
| EXTERNAL moduleCutAREA q0lvtnnotBuildSpace < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_270_X.12b" { |
| @ X.12b: 0.19 min. enclosure of q0lvtnnotBuildSpace by moduleCutAREA |
| q0lvtnnotBuildSpaceand = q0lvtnnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0lvtnnotBuildSpaceand moduleCutAREA < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0hvtpnotBuildSpace = hvtp NOT buildSpace |
| "r_271_X.12a" { |
| @ X.12a: 0.19 min. spacing of moduleCutAREA & q0hvtpnotBuildSpace |
| EXTERNAL moduleCutAREA q0hvtpnotBuildSpace < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_272_X.12b" { |
| @ X.12b: 0.19 min. enclosure of q0hvtpnotBuildSpace by moduleCutAREA |
| q0hvtpnotBuildSpaceand = q0hvtpnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0hvtpnotBuildSpaceand moduleCutAREA < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0hvinotBuildSpace = hvi NOT buildSpace |
| "r_273_X.12a" { |
| @ X.12a: 0.35 min. spacing of moduleCutAREA & q0hvinotBuildSpace |
| EXTERNAL moduleCutAREA q0hvinotBuildSpace < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_274_X.12b" { |
| @ X.12b: 0.35 min. enclosure of q0hvinotBuildSpace by moduleCutAREA |
| q0hvinotBuildSpaceand = q0hvinotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0hvinotBuildSpaceand moduleCutAREA < 0.35 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0tunmnotBuildSpace = tunm NOT buildSpace |
| "r_275_X.12a" { |
| @ X.12a: 0.25 min. spacing of moduleCutAREA & q0tunmnotBuildSpace |
| EXTERNAL moduleCutAREA q0tunmnotBuildSpace < 0.25 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_276_X.12b" { |
| @ X.12b: 0.25 min. enclosure of q0tunmnotBuildSpace by moduleCutAREA |
| q0tunmnotBuildSpaceand = q0tunmnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0tunmnotBuildSpaceand moduleCutAREA < 0.25 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0polynotBuildSpace = poly NOT buildSpace |
| "r_277_X.12a" { |
| @ X.12a: 0.105 min. spacing of moduleCutAREA & q0polynotBuildSpace |
| EXTERNAL moduleCutAREA q0polynotBuildSpace < 0.105 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_278_X.12b" { |
| @ X.12b: 0.105 min. enclosure of q0polynotBuildSpace by moduleCutAREA |
| q0polynotBuildSpaceand = q0polynotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0polynotBuildSpaceand moduleCutAREA < 0.105 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0npcnotBuildSpace = npc NOT buildSpace |
| "r_279_X.12a" { |
| @ X.12a: 0.135 min. spacing of moduleCutAREA & q0npcnotBuildSpace |
| EXTERNAL moduleCutAREA q0npcnotBuildSpace < 0.135 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_280_X.12b" { |
| @ X.12b: 0.135 min. enclosure of q0npcnotBuildSpace by moduleCutAREA |
| q0npcnotBuildSpaceand = q0npcnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0npcnotBuildSpaceand moduleCutAREA < 0.135 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0nsdmnotBuildSpace = nsdm NOT buildSpace |
| "r_281_X.12a" { |
| @ X.12a: 0.19 min. spacing of moduleCutAREA & q0nsdmnotBuildSpace |
| EXTERNAL moduleCutAREA q0nsdmnotBuildSpace < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_282_X.12b" { |
| @ X.12b: 0.19 min. enclosure of q0nsdmnotBuildSpace by moduleCutAREA |
| q0nsdmnotBuildSpaceand = q0nsdmnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0nsdmnotBuildSpaceand moduleCutAREA < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0psdmnotBuildSpace = psdm NOT buildSpace |
| "r_283_X.12a" { |
| @ X.12a: 0.19 min. spacing of moduleCutAREA & q0psdmnotBuildSpace |
| EXTERNAL moduleCutAREA q0psdmnotBuildSpace < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_284_X.12b" { |
| @ X.12b: 0.19 min. enclosure of q0psdmnotBuildSpace by moduleCutAREA |
| q0psdmnotBuildSpaceand = q0psdmnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0psdmnotBuildSpaceand moduleCutAREA < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0licon1notBuildSpace = licon1 NOT buildSpace |
| "r_285_X.12a" { |
| @ X.12a: 0.085 min. spacing of moduleCutAREA & q0licon1notBuildSpace |
| EXTERNAL moduleCutAREA q0licon1notBuildSpace < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_286_X.12b" { |
| @ X.12b: 0.085 min. enclosure of q0licon1notBuildSpace by moduleCutAREA |
| q0licon1notBuildSpaceand = q0licon1notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0licon1notBuildSpaceand moduleCutAREA < 0.085 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0li1notBuildSpace = li1 NOT buildSpace |
| "r_287_X.12a" { |
| @ X.12a: 0.085 min. spacing of moduleCutAREA & q0li1notBuildSpace |
| EXTERNAL moduleCutAREA q0li1notBuildSpace < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_288_X.12b" { |
| @ X.12b: 0.085 min. enclosure of q0li1notBuildSpace by moduleCutAREA |
| q0li1notBuildSpaceand = q0li1notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0li1notBuildSpaceand moduleCutAREA < 0.085 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0mconnotBuildSpace = mcon NOT buildSpace |
| "r_289_X.12a" { |
| @ X.12a: 0.095 min. spacing of moduleCutAREA & q0mconnotBuildSpace |
| EXTERNAL moduleCutAREA q0mconnotBuildSpace < 0.095 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_290_X.12b" { |
| @ X.12b: 0.095 min. enclosure of q0mconnotBuildSpace by moduleCutAREA |
| q0mconnotBuildSpaceand = q0mconnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0mconnotBuildSpaceand moduleCutAREA < 0.095 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0met1notBuildSpace = met1 NOT buildSpace |
| "r_291_X.12a" { |
| @ X.12a: 0.07 min. spacing of moduleCutAREA & q0met1notBuildSpace |
| EXTERNAL moduleCutAREA q0met1notBuildSpace < 0.07 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_292_X.12b" { |
| @ X.12b: 0.07 min. enclosure of q0met1notBuildSpace by moduleCutAREA |
| q0met1notBuildSpaceand = q0met1notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0met1notBuildSpaceand moduleCutAREA < 0.07 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0vianotBuildSpace = via NOT buildSpace |
| "r_293_X.12a" { |
| @ X.12a: 0.085 min. spacing of moduleCutAREA & q0vianotBuildSpace |
| EXTERNAL moduleCutAREA q0vianotBuildSpace < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_294_X.12b" { |
| @ X.12b: 0.085 min. enclosure of q0vianotBuildSpace by moduleCutAREA |
| q0vianotBuildSpaceand = q0vianotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0vianotBuildSpaceand moduleCutAREA < 0.085 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0met2notBuildSpace = met2 NOT buildSpace |
| "r_295_X.12a" { |
| @ X.12a: 0.07 min. spacing of moduleCutAREA & q0met2notBuildSpace |
| EXTERNAL moduleCutAREA q0met2notBuildSpace < 0.07 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_296_X.12b" { |
| @ X.12b: 0.07 min. enclosure of q0met2notBuildSpace by moduleCutAREA |
| q0met2notBuildSpaceand = q0met2notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0met2notBuildSpaceand moduleCutAREA < 0.07 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0via2notBuildSpace = via2 NOT buildSpace |
| "r_297_X.12a" { |
| @ X.12a: 0.1 min. spacing of moduleCutAREA & q0via2notBuildSpace |
| EXTERNAL moduleCutAREA q0via2notBuildSpace < 0.1 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_298_X.12b" { |
| @ X.12b: 0.1 min. enclosure of q0via2notBuildSpace by moduleCutAREA |
| q0via2notBuildSpaceand = q0via2notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0via2notBuildSpaceand moduleCutAREA < 0.1 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0met3notBuildSpace = met3 NOT buildSpace |
| "r_299_X.12a" { |
| @ X.12a: 0.15 min. spacing of moduleCutAREA & q0met3notBuildSpace |
| EXTERNAL moduleCutAREA q0met3notBuildSpace < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_300_X.12b" { |
| @ X.12b: 0.15 min. enclosure of q0met3notBuildSpace by moduleCutAREA |
| q0met3notBuildSpaceand = q0met3notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0met3notBuildSpaceand moduleCutAREA < 0.15 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0via3notBuildSpace = via3 NOT buildSpace |
| "r_301_X.12a" { |
| @ X.12a: 0.1 min. spacing of moduleCutAREA & q0via3notBuildSpace |
| EXTERNAL moduleCutAREA q0via3notBuildSpace < 0.1 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_302_X.12b" { |
| @ X.12b: 0.1 min. enclosure of q0via3notBuildSpace by moduleCutAREA |
| q0via3notBuildSpaceand = q0via3notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0via3notBuildSpaceand moduleCutAREA < 0.1 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0met4notBuildSpace = met4 NOT buildSpace |
| "r_303_X.12a" { |
| @ X.12a: 0.15 min. spacing of moduleCutAREA & q0met4notBuildSpace |
| EXTERNAL moduleCutAREA q0met4notBuildSpace < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_304_X.12b" { |
| @ X.12b: 0.15 min. enclosure of q0met4notBuildSpace by moduleCutAREA |
| q0met4notBuildSpaceand = q0met4notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0met4notBuildSpaceand moduleCutAREA < 0.15 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0via4notBuildSpace = via4 NOT buildSpace |
| "r_305_X.12a" { |
| @ X.12a: 0.4 min. spacing of moduleCutAREA & q0via4notBuildSpace |
| EXTERNAL moduleCutAREA q0via4notBuildSpace < 0.4 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_306_X.12b" { |
| @ X.12b: 0.4 min. enclosure of q0via4notBuildSpace by moduleCutAREA |
| q0via4notBuildSpaceand = q0via4notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0via4notBuildSpaceand moduleCutAREA < 0.4 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0met5notBuildSpace = met5 NOT buildSpace |
| "r_307_X.12a" { |
| @ X.12a: 0.8 min. spacing of moduleCutAREA & q0met5notBuildSpace |
| EXTERNAL moduleCutAREA q0met5notBuildSpace < 0.8 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_308_X.12b" { |
| @ X.12b: 0.8 min. enclosure of q0met5notBuildSpace by moduleCutAREA |
| q0met5notBuildSpaceand = q0met5notBuildSpace AND moduleCutAREA |
| ENCLOSURE q0met5notBuildSpaceand moduleCutAREA < 0.8 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0nsmnotBuildSpace = nsm NOT buildSpace |
| "r_309_X.12a" { |
| @ X.12a: 2 min. spacing of moduleCutAREA & q0nsmnotBuildSpace |
| EXTERNAL moduleCutAREA q0nsmnotBuildSpace < 2.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_310_X.12b" { |
| @ X.12b: 2 min. enclosure of q0nsmnotBuildSpace by moduleCutAREA |
| q0nsmnotBuildSpaceand = q0nsmnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0nsmnotBuildSpaceand moduleCutAREA < 2.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0padnotBuildSpace = pad NOT buildSpace |
| "r_311_X.12a" { |
| @ X.12a: 0.635 min. spacing of moduleCutAREA & q0padnotBuildSpace |
| EXTERNAL moduleCutAREA q0padnotBuildSpace < 0.635 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_312_X.12b" { |
| @ X.12b: 0.635 min. enclosure of q0padnotBuildSpace by moduleCutAREA |
| q0padnotBuildSpaceand = q0padnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0padnotBuildSpaceand moduleCutAREA < 0.635 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0ldntmnotBuildSpace = ldntm NOT buildSpace |
| "r_313_X.12a" { |
| @ X.12a: 0.35 min. spacing of moduleCutAREA & q0ldntmnotBuildSpace |
| EXTERNAL moduleCutAREA q0ldntmnotBuildSpace < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_314_X.12b" { |
| @ X.12b: 0.35 min. enclosure of q0ldntmnotBuildSpace by moduleCutAREA |
| q0ldntmnotBuildSpaceand = q0ldntmnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0ldntmnotBuildSpaceand moduleCutAREA < 0.35 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0hvntmnotBuildSpace = hvntm NOT buildSpace |
| "r_315_X.12a" { |
| @ X.12a: 0.19 min. spacing of moduleCutAREA & q0hvntmnotBuildSpace |
| EXTERNAL moduleCutAREA q0hvntmnotBuildSpace < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_316_X.12b" { |
| @ X.12b: 0.19 min. enclosure of q0hvntmnotBuildSpace by moduleCutAREA |
| q0hvntmnotBuildSpaceand = q0hvntmnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0hvntmnotBuildSpaceand moduleCutAREA < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0ncmnotBuildSpace = ncm NOT buildSpace |
| "r_317_X.12a" { |
| @ X.12a: 0.19 min. spacing of moduleCutAREA & q0ncmnotBuildSpace |
| EXTERNAL moduleCutAREA q0ncmnotBuildSpace < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_318_X.12b" { |
| @ X.12b: 0.19 min. enclosure of q0ncmnotBuildSpace by moduleCutAREA |
| q0ncmnotBuildSpaceand = q0ncmnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0ncmnotBuildSpaceand moduleCutAREA < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0rdlnotBuildSpace = rdl NOT buildSpace |
| "r_319_X.12a" { |
| @ X.12a: 5 min. spacing of moduleCutAREA & q0rdlnotBuildSpace |
| EXTERNAL moduleCutAREA q0rdlnotBuildSpace < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_320_X.12b" { |
| @ X.12b: 5 min. enclosure of q0rdlnotBuildSpace by moduleCutAREA |
| q0rdlnotBuildSpaceand = q0rdlnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0rdlnotBuildSpaceand moduleCutAREA < 5.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q0hvtrnotBuildSpace = hvtr NOT buildSpace |
| "r_321_X.12a" { |
| @ X.12a: 0.19 min. spacing of moduleCutAREA & q0hvtrnotBuildSpace |
| EXTERNAL moduleCutAREA q0hvtrnotBuildSpace < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_322_X.12b" { |
| @ X.12b: 0.19 min. enclosure of q0hvtrnotBuildSpace by moduleCutAREA |
| q0hvtrnotBuildSpaceand = q0hvtrnotBuildSpace AND moduleCutAREA |
| ENCLOSURE q0hvtrnotBuildSpaceand moduleCutAREA < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q1met1notBuildSpace = (WITH WIDTH met1 >= 3.0) NOT (SEALnoHoles_ORIGIN OR buildSpace) |
| "r_323_X.12d" { |
| @ X.12d: 0.14 min. spacing of moduleCutAREA & q1met1notBuildSpace |
| EXTERNAL moduleCutAREA q1met1notBuildSpace < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_324_X.12e" { |
| @ X.12e: 0.14 min. enclosure of q1met1notBuildSpace by moduleCutAREA |
| q1met1notBuildSpaceand = q1met1notBuildSpace AND moduleCutAREA |
| ENCLOSURE q1met1notBuildSpaceand moduleCutAREA < 0.14 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q1met2notBuildSpace = (WITH WIDTH met2 >= 3.0) NOT (SEALnoHoles_ORIGIN OR buildSpace) |
| "r_325_X.12d" { |
| @ X.12d: 0.14 min. spacing of moduleCutAREA & q1met2notBuildSpace |
| EXTERNAL moduleCutAREA q1met2notBuildSpace < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_326_X.12e" { |
| @ X.12e: 0.14 min. enclosure of q1met2notBuildSpace by moduleCutAREA |
| q1met2notBuildSpaceand = q1met2notBuildSpace AND moduleCutAREA |
| ENCLOSURE q1met2notBuildSpaceand moduleCutAREA < 0.14 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q1met3notBuildSpace = (WITH WIDTH met3 >= 3.0) NOT (SEALnoHoles_ORIGIN OR buildSpace) |
| "r_327_X.12d" { |
| @ X.12d: 0.2 min. spacing of moduleCutAREA & q1met3notBuildSpace |
| EXTERNAL moduleCutAREA q1met3notBuildSpace < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_328_X.12e" { |
| @ X.12e: 0.2 min. enclosure of q1met3notBuildSpace by moduleCutAREA |
| q1met3notBuildSpaceand = q1met3notBuildSpace AND moduleCutAREA |
| ENCLOSURE q1met3notBuildSpaceand moduleCutAREA < 0.2 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| q1met4notBuildSpace = (WITH WIDTH met4 >= 3.0) NOT (SEALnoHoles_ORIGIN OR buildSpace) |
| "r_329_X.12d" { |
| @ X.12d: 0.2 min. spacing of moduleCutAREA & q1met4notBuildSpace |
| EXTERNAL moduleCutAREA q1met4notBuildSpace < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_330_X.12e" { |
| @ X.12e: 0.2 min. enclosure of q1met4notBuildSpace by moduleCutAREA |
| q1met4notBuildSpaceand = q1met4notBuildSpace AND moduleCutAREA |
| ENCLOSURE q1met4notBuildSpaceand moduleCutAREA < 0.2 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| //add cap, cap2m |
| "r_331_X.12e" { |
| @ X.12e: 0.42 min. spacing of moduleCutAREA & capm |
| EXTERNAL moduleCutAREA capm < 0.42 ABUT < 90 SINGULAR REGION |
| } |
| "r_326_X.18b" { |
| @ X.18b: 0.42 min. enclosure of capm by moduleCutAREA |
| q0capmand = capm AND moduleCutAREA |
| ENCLOSURE q0capmand moduleCutAREA < 0.42 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_327_X.18a" { |
| @ X.18a: 0.42 min. spacing of moduleCutAREA & cap2m |
| EXTERNAL moduleCutAREA cap2m < 0.42 ABUT < 90 SINGULAR REGION |
| } |
| "r_328_X.18b" { |
| @ X.18b: 0.42 min. enclosure of cap2m by moduleCutAREA |
| q0cap2mand = cap2m AND moduleCutAREA |
| ENCLOSURE q0cap2mand moduleCutAREA < 0.42 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| /// |
| q0cfom = cfom NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_331_X.15a" { |
| @ X.15a: X.15a: layer cfom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cfom |
| } |
| q0clvtnm = clvtnm NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_332_X.15a" { |
| @ X.15a: X.15a: layer clvtnm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0clvtnm |
| } |
| q0chvtpm = chvtpm NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_333_X.15a" { |
| @ X.15a: X.15a: layer chvtpm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0chvtpm |
| } |
| q0conom = conom NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_334_X.15a" { |
| @ X.15a: X.15a: layer conom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0conom |
| } |
| q0clvom = clvom NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_335_X.15a" { |
| @ X.15a: X.15a: layer clvom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0clvom |
| } |
| q0cntm = cntm NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_336_X.15a" { |
| @ X.15a: X.15a: layer cntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cntm |
| } |
| q0chvntm = chvntm NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_337_X.15a" { |
| @ X.15a: X.15a: layer chvntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0chvntm |
| } |
| q0cnpc = cnpc NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_338_X.15a" { |
| @ X.15a: X.15a: layer cnpc allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cnpc |
| } |
| q0cnsdm = cnsdm NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_339_X.15a" { |
| @ X.15a: X.15a: layer cnsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cnsdm |
| } |
| q0cpsdm = cpsdm NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_340_X.15a" { |
| @ X.15a: X.15a: layer cpsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cpsdm |
| } |
| q0cli1m = cli1m NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_341_X.15a" { |
| @ X.15a: X.15a: layer cli1m allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cli1m |
| } |
| q0cviam3 = cviam3 NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_342_X.15a" { |
| @ X.15a: X.15a: layer cviam3 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cviam3 |
| } |
| q0cviam4 = cviam4 NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_343_X.15a" { |
| @ X.15a: X.15a: layer cviam4 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0cviam4 |
| } |
| q0PMM2mk = PMM2mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_344_X.15a" { |
| @ X.15a: X.15a: layer PMM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0PMM2mk |
| } |
| q0CU1Mmk = CU1Mmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_345_X.15a" { |
| @ X.15a: X.15a: layer CU1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0CU1Mmk |
| } |
| q0RPMmk = RPMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_346_X.15a" { |
| @ X.15a: X.15a: layer RPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0RPMmk |
| } |
| q0PBOmk = PBOmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_347_X.15a" { |
| @ X.15a: X.15a: layer PBOmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0PBOmk |
| } |
| q0PDMmk = PDMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_348_X.15a" { |
| @ X.15a: X.15a: layer PDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0PDMmk |
| } |
| q0NSMmk = NSMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_349_X.15a" { |
| @ X.15a: X.15a: layer NSMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0NSMmk |
| } |
| q0MM5mk = MM5mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_350_X.15a" { |
| @ X.15a: X.15a: layer MM5mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0MM5mk |
| } |
| q0VIM4mk = VIM4mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_351_X.15a" { |
| @ X.15a: X.15a: layer VIM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0VIM4mk |
| } |
| q0MM4mk = MM4mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_352_X.15a" { |
| @ X.15a: X.15a: layer MM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0MM4mk |
| } |
| q0VIM3mk = VIM3mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_353_X.15a" { |
| @ X.15a: X.15a: layer VIM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0VIM3mk |
| } |
| q0MM3mk = MM3mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_354_X.15a" { |
| @ X.15a: X.15a: layer MM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0MM3mk |
| } |
| q0VIM2mk = VIM2mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_355_X.15a" { |
| @ X.15a: X.15a: layer VIM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0VIM2mk |
| } |
| q0MM2mk = MM2mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_356_X.15a" { |
| @ X.15a: X.15a: layer MM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0MM2mk |
| } |
| q0VIMmk = VIMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_357_X.15a" { |
| @ X.15a: X.15a: layer VIMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0VIMmk |
| } |
| q0MM1mk = MM1mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_358_X.15a" { |
| @ X.15a: X.15a: layer MM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0MM1mk |
| } |
| q0CTM1mk = CTM1mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_359_X.15a" { |
| @ X.15a: X.15a: layer CTM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0CTM1mk |
| } |
| q0LI1Mmk = LI1Mmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_360_X.15a" { |
| @ X.15a: X.15a: layer LI1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0LI1Mmk |
| } |
| q0LICM1mk = LICM1mk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_361_X.15a" { |
| @ X.15a: X.15a: layer LICM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0LICM1mk |
| } |
| q0PSDMmk = PSDMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_362_X.15a" { |
| @ X.15a: X.15a: layer PSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0PSDMmk |
| } |
| q0NSDMmk = NSDMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_363_X.15a" { |
| @ X.15a: X.15a: layer NSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0NSDMmk |
| } |
| q0LDNTMmk = LDNTMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_364_X.15a" { |
| @ X.15a: X.15a: layer LDNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0LDNTMmk |
| } |
| q0NPCMmk = NPCMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_365_X.15a" { |
| @ X.15a: X.15a: layer NPCMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0NPCMmk |
| } |
| q0HVNTMmk = HVNTMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_366_X.15a" { |
| @ X.15a: X.15a: layer HVNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0HVNTMmk |
| } |
| q0NTMmk = NTMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_367_X.15a" { |
| @ X.15a: X.15a: layer NTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0NTMmk |
| } |
| q0P1Mmk = P1Mmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_368_X.15a" { |
| @ X.15a: X.15a: layer P1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0P1Mmk |
| } |
| q0LVOMmk = LVOMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_369_X.15a" { |
| @ X.15a: X.15a: layer LVOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0LVOMmk |
| } |
| q0ONOMmk = ONOMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_370_X.15a" { |
| @ X.15a: X.15a: layer ONOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0ONOMmk |
| } |
| q0TUNMmk = TUNMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_371_X.15a" { |
| @ X.15a: X.15a: layer TUNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0TUNMmk |
| } |
| q0HVTRMmk = HVTRMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_372_X.15a" { |
| @ X.15a: X.15a: layer HVTRMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0HVTRMmk |
| } |
| q0HVTPMmk = HVTPMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_373_X.15a" { |
| @ X.15a: X.15a: layer HVTPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0HVTPMmk |
| } |
| q0LVTNMmk = LVTNMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_374_X.15a" { |
| @ X.15a: X.15a: layer LVTNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0LVTNMmk |
| } |
| q0NWMmk = NWMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_375_X.15a" { |
| @ X.15a: X.15a: layer NWMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0NWMmk |
| } |
| q0DNMmk = DNMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_376_X.15a" { |
| @ X.15a: X.15a: layer DNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0DNMmk |
| } |
| q0FOMmk = FOMmk NOT (COREID OR |
| (SEALID OR |
| (moduleCutAREA OR frameBndr))) |
| "r_377_X.15a" { |
| @ X.15a: X.15a: layer FOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft |
| COPY q0FOMmk |
| } |
| areaidMTorSC = moduleCutArea OR STDCID |
| SEALIDextent = EXTENT SEALID |
| SEALID_6um = SEALID AND ((EXTENT CELL "advSeal_6um*" ORIGINAL) OR (EXTENT CELL "cuPillarAdvSeal_6um*" ORIGINAL)) |
| diffOfA1K = INTERACT diff (EXPAND EDGE (LENGTH (DONUT DIFF) > 1000) INSIDE BY 0.005) |
| diffRingSeal = INTERACT (INTERACT diff (INTERNAL diffOfA1K == 0.3 ABUT < 90 SINGULAR REGION)) SEALID |
| "r_378_X.16" { |
| @ X.16: extentDie must not overlap moduleCutAREA |
| extentDie AND moduleCutAREA |
| } |
| SEALnotOrigin = TVF CALtvfOriginCheck SEALIDextent |
| "r_379_X.19" { |
| @ X.19: SEAL ring is not at origin (0,0) |
| COPY SEALnotOrigin |
| } |
| "r_380_X.21" { |
| @ X.21: prune must overlap areaidMTorSC |
| prune OUTSIDE areaidMTorSC |
| } |
| "r_381_X.23b" { |
| @ X.23b: diff must not straddle SEALID |
| CUT diff SEALID |
| } |
| "r_382_X.23c" { |
| @ X.23c: tap must not overlap SEALID |
| tap AND SEALID |
| } |
| "r_383_X.23c" { |
| @ X.23c: poly must not overlap SEALID |
| poly AND SEALID |
| } |
| "r_384_X.23c" { |
| @ X.23c: li1 must not overlap SEALID |
| li1 AND SEALID |
| } |
| "r_385_X.23c" { |
| @ X.23c: met1 must not overlap SEALID |
| met1 AND SEALID |
| } |
| "r_386_X.23c" { |
| @ X.23c: met2 must not overlap SEALID |
| met2 AND SEALID |
| } |
| "r_387_X.23c" { |
| @ X.23c: met3 must not overlap SEALID |
| met3 AND SEALID |
| } |
| "r_388_X.23c" { |
| @ X.23c: met4 must not overlap SEALID |
| met4 AND SEALID |
| } |
| "r_389_X.23c" { |
| @ X.23c: met5 must not overlap SEALID |
| met5 AND SEALID |
| } |
| "r_390_X.26" { |
| @ X.26: SEALID_6um must overlap diff |
| SEALID_6um OUTSIDE diff |
| } |
| ptapStradLocSub = CUT PTAP localSub |
| validPNPcell = (EXTENT CELL "s8rf_pnp" ORIGINAL) OR |
| ((EXTENT CELL "s8rf_pnp5x" ORIGINAL) OR |
| ((EXTENT CELL "s8tesd_iref_pnp") OR (EXTENT CELL "stk14ecx*" ORIGINAL))) |
| invalidPNP = pnp NOT validPNPcell |
| "s_5_X.23f" { |
| @ X.23f: ptap must not straddle localSub |
| COPY ptapStradLocSub |
| } |
| "r_391_X.25" { |
| @ X.25: pnp layer must be within specified fixed layout cells s8rf_pnp/s8rf_pnp5x |
| COPY invalidPNP |
| } |
| partNum_pcells = EXTENT CELL "partnum*" ORIGINAL |
| partNum_blockpcells = EXTENT CELL "partnum*block*" ORIGINAL |
| sealidWithExclusion = WITH TEXT SEALnoHoles_ORIGIN "partnum_not_necessary" textlabel |
| sealidWithPartnum = INTERACT SEALnoHoles_ORIGIN partNum_pcells |
| badSealidTmp = SEALnoHoles_ORIGIN NOT sealidWithPartnum |
| badSealid = badSealidTmp NOT sealidWithExclusion |
| InvalidPcell_X27 = partNum_pcells NOT partNum_blockpcells |
| "s_6_X.27" { |
| @ X.27: partnum or partnum exclusion 'partnum_not_necessary' not present on chip |
| COPY badSealid |
| } |
| "s_7_X.27" { |
| @ X.27: partnum*block pcell should be used instead of partnum* pcells |
| COPY InvalidPcell_X27 |
| } |
| "r_392_X.28" { |
| @ X.28: 6 min. width of SEALID |
| INTERNAL SEALID < 6.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| nwellring = DONUT nwell |
| photoDiode = INTERACT dnwell (dnwell AND photoID) |
| dnwellNotPhoto = dnwell NOT photoDiode |
| dnwellNotPhotoNotUHVI = dnwellNotPhoto NOT uhvi |
| PDIFFNotExempt = PDIFF NOT exempt_Pdiff_Cells |
| badLocalSub = (CUT dnwell localSub) AND localSub |
| "r_393_dnwell.2" { |
| @ dnwell.2: 3 min. width of dnwell |
| INTERNAL dnwell < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_394_dnwell.3" { |
| @ dnwell.3: 6.3 min. spacing/notch of dnwellNotPhotoNotUHVI |
| EXTERNAL dnwellNotPhotoNotUHVI < 6.3 ABUT < 90 SINGULAR REGION |
| } |
| "r_395_dnwell.4" { |
| @ dnwell.4: dnwell must not overlap pnp |
| dnwell AND pnp |
| } |
| "r_396_dnwell.5" { |
| @ dnwell.5: PDIFF not Exempt cells must not straddle dnwell |
| CUT PDIFFNotExempt dnwell |
| } |
| "r_397_dnwell.7" { |
| @ dnwell.7: dnwell cannot straddle localSub |
| COPY badLocalSub |
| } |
| nwell_tap = INTERACT NTAP (NTAP AND licon1) |
| nwellHoles = HOLES nwell |
| nwell_nonUHVI = nwell NOT uhvi |
| filledNwell = nwell OR nwellHoles |
| dnwellNotTechCD = dnwellNotPhoto NOT exempt_tech_CD |
| dnwellNotTechCDLOWVTID = dnwellNotTechCD NOT (uhvi OR LOWVTID) |
| nwellNotTechCD = nwell NOT exempt_tech_CD |
| nwellHoleOverDnwell = INTERACT nwellHoles (nwellHoles AND dnwellNotTechCD) |
| dnwellOverNwell = INTERACT (INTERACT dnwellNotTechCD (dnwellNotTechCD AND nwellNotTechCD)) nwellHoles |
| dnwellOverNwellEnc = INTERACT (EXPAND EDGE dnwellOverNwell INSIDE BY 1.03) nwellNotTechCD |
| dnwellOverNwellErr = dnwellOverNwellEnc NOT (nwellNotTechCD OR (exempt_nwell6_Cells OR uhvi)) |
| "r_398_nwell.1" { |
| @ nwell.1: 0.84 min. width of nwell |
| INTERNAL nwell < 0.84 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_399_nwell.2a" { |
| @ nwell.2a: 1.27 min. spacing/notch of nwell |
| EXTERNAL nwell < 1.27 ABUT < 90 SINGULAR REGION |
| } |
| /// nwell.3 is handled by design |
| "r_400_nwell.4" { |
| @ nwell.4: nwell_nonUHVI must overlap metal contacted tap to nwell |
| nwell_nonUHVI OUTSIDE nwell_tap |
| } |
| "r_401_nwell.5" { |
| @ nwell.5: 0.4 min. enclosure of dnwellNotTechCDLOWVTID by filledNwell |
| q0dnwellNotTechCDLOWVTIDand = dnwellNotTechCDLOWVTID AND filledNwell |
| ENCLOSURE q0dnwellNotTechCDLOWVTIDand filledNwell < 0.4 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_402_nwell.5" { |
| @ nwell.5: dnwellNotTechCDLOWVTID must be enclosed by filledNwell |
| dnwellNotTechCDLOWVTID NOT filledNwell |
| } |
| "r_403_nwell.6" { |
| @ nwell.6: 1.03 min enclosure of nwellHole by dnwell |
| COPY dnwellOverNwellErr |
| } |
| nwell_dnwell_no_minspace = EXTERNAL dnwellNotTechCD nwellNotTechCD < 4.5 MEASURE ALL NOT CONNECTED REGION |
| "r_404_nwell.7" { |
| @ nwell.7: 4.5 min spacing between nwell and dnwell on separate nets |
| COPY nwell_dnwell_no_minspace |
| } |
| PFET = GATE AND PDIFF |
| PFET_PERI = PFET NOT COREID |
| hvtpOnNwell = INTERACT hvtp_CORE (hvtp_CORE AND nwell) |
| InvalidNwellEnc = hvtpOnNwell NOT nwell |
| lvNwell_drc = nwell NOT hvi |
| PolyLvNwell = poly AND lvNwell_drc |
| lvNtap = tap AND lvNwell_drc |
| varChannel_drc = (PolylvNwell AND lvNtap) NOT COREID |
| LVnwellnovarChannel = lvNwell_drc NOT (INTERACT lvNwell_drc (lvNwell_drc AND varChannel_drc)) |
| hvtpHoles = HOLES hvtp |
| "r_405_hvtp.1" { |
| @ hvtp.1: 0.38 min. width of hvtp |
| INTERNAL hvtp < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_406_hvtp.2" { |
| @ hvtp.2: 0.38 min. spacing/notch of hvtp |
| EXTERNAL hvtp < 0.38 ABUT < 90 SINGULAR REGION |
| } |
| "r_407_hvtp.3" { |
| @ hvtp.3: 0.18 min. enclosure of PFET_PERI by hvtp |
| q0PFET_PERIand = PFET_PERI AND hvtp |
| ENCLOSURE q0PFET_PERIand hvtp < 0.18 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_408_hvtp.4" { |
| @ hvtp.4: 0.18 min. spacing of PFET_PERI & hvtp |
| EXTERNAL PFET_PERI hvtp < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_409_hvtp.5" { |
| @ hvtp.5: 0.265 min. area of hvtp |
| AREA hvtp < 0.265 |
| } |
| "r_410_hvtp.6" { |
| @ hvtp.6: 0.265 min. area of hvtpHoles |
| AREA hvtpHoles < 0.265 |
| } |
| "r_411_hvtp.c1" { |
| @ hvtp.c1: Min/Max enclosure of nwell by hvtp |
| COPY InvalidNwellEnc |
| } |
| lvtEncPDiff = lvtn ENCLOSE PDIFF |
| periDiffNoLvt = diff_PERI NOT lvtn_PERI |
| lvtGate = lvtn AND GATE |
| nwellNoVarac = (nwell NOT (INTERACT nwell (nwell AND varChannel_drc))) NOT INSIDE lvtn |
| lvtnInNwell = NOT TOUCH (ENCLOSURE lvtn nwellNoVarac < 0.38 REGION) nwellNoVarac |
| coreNwell = nwell INSIDE COREID |
| pfetSDedge = (NOT INTERACT pfet_PERI lvtn) COINCIDENT EDGE PSRCDRN |
| pfetSDedgeSz = EXPAND EDGE pfetSDedge OUTSIDE BY 0.195 |
| err_lvtn3b = INTERACT lvtn_PERI pfetSDedgeSz |
| lvtnHoles = HOLES lvtn |
| GATE_PERI_nonUHVI = GATE_PERI NOT uhvi |
| "r_412_lvtn.1a" { |
| @ lvtn.1a: 0.38 min. width of lvtn |
| INTERNAL lvtn < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_413_lvtn.2" { |
| @ lvtn.2: 0.38 min. spacing/notch of lvtn |
| EXTERNAL lvtn < 0.38 ABUT < 90 SINGULAR REGION |
| } |
| "r_414_lvtn.3a" { |
| @ lvtn.3a: 0.18 min. spacing of Gate in Periphery outside UHVI layer & "lvtn" in periphery |
| EXTERNAL GATE_PERI_nonUHVI lvtn_PERI < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_415_lvtn.3b" { |
| @ lvtn.3b: 0.19 min spacing of lvtn(peri) to pfet along S/D direction |
| COPY err_lvtn3b |
| } |
| "r_416_lvtn.4b" { |
| @ lvtn.4b: 0.18 min. enclosure of Gate in Periphery outside UHVI layer by "lvtn" in periphery |
| q0GATE_PERI_nonUHVIand = GATE_PERI_nonUHVI AND lvtn_PERI |
| ENCLOSURE q0GATE_PERI_nonUHVIand lvtn_PERI < 0.18 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_417_lvtn.9" { |
| @ lvtn.9: 0.38 min. spacing of lvtn & hvtp |
| EXTERNAL lvtn hvtp < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_418_lvtn.9" { |
| @ lvtn.9: lvtn must not overlap hvtp |
| lvtn AND hvtp |
| } |
| "r_419_lvtn.10" { |
| @ lvtn.10: 0.38 min enclosure of lvtn by (nwell not overlapping Varactor Channel) |
| COPY lvtnInNwell |
| } |
| "r_420_lvtn.12" { |
| @ lvtn.12: 0.38 min. spacing of lvtn & coreNwell |
| EXTERNAL lvtn coreNwell < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_421_lvtn.13" { |
| @ lvtn.13: 0.265 min. area of lvtn |
| AREA lvtn < 0.265 |
| } |
| "r_422_lvtn.14" { |
| @ lvtn.14: 0.265 min. area of lvtnHoles |
| AREA lvtnHoles < 0.265 |
| } |
| "r_423_hvtr.1" { |
| @ hvtr.1: 0.38 min. width of hvtr |
| INTERNAL hvtr < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_424_hvtr.2" { |
| @ hvtr.2: 0.38 min. spacing of hvtr & hvtp |
| EXTERNAL hvtr hvtp < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_425_hvtr.2" { |
| @ hvtr.2: hvtr must not overlap hvtp |
| hvtr AND hvtp |
| } |
| "r_426_hvtr.3" { |
| @ hvtr.3: 0.18 min. enclosure of PFET by hvtr |
| q0PFETand = PFET AND hvtr |
| ENCLOSURE q0PFETand hvtr < 0.18 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| GATE_PERI_SC = GATE_PERI AND STDCID |
| GATE_PERI_noSC = GATE_PERI NOT STDCID |
| nwell_noesd = nwell NOT ESD_nwell_tap |
| diff_noesd = diff NOT ESD_nwell_tap |
| tap_noesd = tap NOT ESD_nwell_tap |
| tabut_edge = TOUCH EDGE tap_noesd diff_noesd |
| dabut_edge = TOUCH EDGE diff_noesd tap_noesd |
| invalid_diff_tap = (EXPAND EDGE ((TOUCH EDGE tap diff) OUTSIDE EDGE diff) OUTSIDE BY 0.005) OR (EXPAND EDGE ((TOUCH EDGE diff tap) OUTSIDE EDGE tap) OUTSIDE BY 0.005) |
| diff_tap_no_minspace = (EXTERNAL diffNoTapEdge tabut_edge < 0.13 ABUT < 90 REGION) OR (EXTERNAL tapNoDiffEdge dabut_edge < 0.13 ABUT < 90 REGION) |
| nwellInDnwell = nwell INSIDE dnwell |
| chip = EXTENT |
| chipNotNwell = chip NOT nwell |
| PDIFF_PERI_nonESD = PDIFF_PERI NOT ((ESD_nwell_tap OR ENID) OR uhvi) |
| NDIFF_PERI_nonESD = NDIFF_PERI NOT (ESD_nwell_tap OR ENID) |
| PDIFF_PERI_nonESDuhvi = PDIFF_PERI_nonESD NOT uhvi |
| NDIFF_PERI_nonESDuhvi = NDIFF_PERI_nonESD NOT uhvi |
| PTAP_nonUHVI = PTAP NOT uhvi |
| q1diff = INTERNAL diff < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q4diff = q1diff OUTSIDE COREID |
| q8diff = diff NOT COREID |
| q7diff = INTERNAL q8diff < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q2diff = q7diff INSIDE (CUT q1diff COREID) |
| q3diff = SIZE q2diff BY 0.005 INSIDE OF q1diff STEP 0.15 |
| "r_427_difftap.1" { |
| @ difftap.1: 0.15 min. width of diff across areaid:ce |
| COPY q3diff |
| } |
| "r_428_difftap.1" { |
| @ difftap.1: 0.15 min. width of diff in PERI |
| COPY q4diff |
| } |
| q5diff = INTERNAL diff < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q6diff = q5diff INSIDE COREID |
| "r_429_difftap.c1" { |
| @ difftap.c1: 0.14 min. width of diff in COREID |
| COPY q6diff |
| } |
| q0tap = INTERNAL tap < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q3tap = q0tap OUTSIDE COREID |
| q7tap = tap NOT COREID |
| q6tap = INTERNAL q7tap < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q1tap = q6tap INSIDE (CUT q0tap COREID) |
| q2tap = SIZE q1tap BY 0.005 INSIDE OF q0tap STEP 0.15 |
| "r_430_difftap.1" { |
| @ difftap.1: 0.15 min. width of tap across areaid:ce |
| COPY q2tap |
| } |
| "r_431_difftap.1" { |
| @ difftap.1: 0.15 min. width of tap in PERI |
| COPY q3tap |
| } |
| q4tap = INTERNAL tap < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q5tap = q4tap INSIDE COREID |
| "r_432_difftap.c1" { |
| @ difftap.c1: 0.14 min. width of tap in COREID |
| COPY q5tap |
| } |
| "r_433_difftap.2" { |
| @ difftap.2: 0.42 min. width of GATE_PERI_noSC |
| q0GATE_PERI_noSCcoin = GATE_PERI_noSC COINCIDENT INSIDE EDGE diff |
| INTERNAL q0GATE_PERI_noSCcoin < 0.42 ABUT < 90 REGION OPPOSITE |
| } |
| "r_434_difftap.2b" { |
| @ difftap.2b: 0.36 min. width of GATE_PERI_SC |
| q0GATE_PERI_SCcoin = GATE_PERI_SC COINCIDENT INSIDE EDGE diff |
| INTERNAL q0GATE_PERI_SCcoin < 0.36 ABUT < 90 REGION OPPOSITE |
| } |
| "r_435_difftap.3" { |
| @ difftap.3: 0.27 min. spacing/notch of diff or tap |
| EXTERNAL diffTap < 0.27 ABUT < 90 SINGULAR REGION |
| } |
| "r_436_difftap.4" { |
| @ difftap.4: 0.29 min. width of tap butting diff |
| q9diff = diff COINCIDENT OUTSIDE EDGE tap |
| ENCLOSURE q9diff tap < 0.29 ABUT < 90 MEASURE COINCIDENT REGION |
| } |
| "r_437_difftap.5" { |
| @ difftap.5: 0.4 min. width of "tap" in periphery butting & between diff |
| q0tap_PERI = tap_PERI COINCIDENT OUTSIDE EDGE diff |
| INTERNAL q0tap_PERI < 0.4 ABUT < 90 REGION |
| } |
| "r_438_difftap.6" { |
| @ difftap.6: diff and tap are not allowed to extend beyond their abutting edge |
| COPY invalid_diff_tap |
| } |
| "r_439_difftap.7" { |
| @ difftap.7: 0.13 spacing of diff/tap butting edge to non-coincident diff/tap edge |
| COPY diff_tap_no_minspace |
| } |
| "r_440_difftap.8" { |
| @ difftap.8: 0.18 min. enclosure of PDIFF_PERI_nonESDuhvi by nwell |
| q0PDIFF_PERI_nonESDuhviand = PDIFF_PERI_nonESDuhvi AND nwell |
| ENCLOSURE q0PDIFF_PERI_nonESDuhviand nwell < 0.18 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_441_difftap.9" { |
| @ difftap.9: 0.34 min. spacing of NDIFF_PERI_nonESDuhvi & nwell_noesd |
| EXTERNAL NDIFF_PERI_nonESDuhvi nwell_noesd < 0.34 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_442_difftap.10" { |
| @ difftap.10: 0.18 min. enclosure of NTAP_nonESD_nonuhvi by nwell |
| q0NTAP_nonESD_nonuhviand = NTAP_nonESD_nonuhvi AND nwell |
| ENCLOSURE q0NTAP_nonESD_nonuhviand nwell < 0.18 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_443_difftap.11" { |
| @ difftap.11: 0.13 min. spacing of PTAP_nonUHVI & nwell |
| EXTERNAL PTAP_nonUHVI nwell < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| /// difftap.12 is handled by an instruction for lvs use |
| "r_444_difftap.c1" { |
| @ difftap.c1: 0.14 min. width of "gate" in core |
| q0EMOSGATE_COREcoin = EMOSGATE_CORE COINCIDENT INSIDE EDGE diff |
| INTERNAL q0EMOSGATE_COREcoin < 0.14 ABUT < 90 REGION |
| } |
| "r_445_difftap.c5" { |
| @ difftap.c5: 0.38 min. width of "tap" in core butting & between diff |
| q0tap_CORE = tap_CORE COINCIDENT OUTSIDE EDGE diff |
| INTERNAL q0tap_CORE < 0.38 ABUT < 90 REGION |
| } |
| "r_446_difftap.c8" { |
| @ difftap.c8: 0.15 min. enclosure of "pdiff" in core by nwell |
| q0PDIFF_COREand = PDIFF_CORE AND nwell |
| ENCLOSURE q0PDIFF_COREand nwell < 0.15 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_447_difftap.c10" { |
| @ difftap.c10: 0.15 min. enclosure of "ntap" in core by nwell |
| q0NTAP_COREand = NTAP_CORE AND nwell |
| ENCLOSURE q0NTAP_COREand nwell < 0.15 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_448_difftap.c12" { |
| @ difftap.c12: 0.18 min. enclosure of adj. sides of "pdiff" in core by nwell |
| q0nwellenc = ENCLOSURE [PDIFF_CORE] nwell < 0.18 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q0nwellenc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_449_difftap.c13" { |
| @ difftap.c13: 0.32 min. spacing of "ndiff" in core & nwell |
| EXTERNAL NDIFF_CORE nwell < 0.32 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_450_difftap.c14" { |
| @ difftap.c14: 0.34 min. enclosure of adj. sides of "ndiff" in core by chipNotNwell |
| q0chipNotNwellenc = ENCLOSURE [NDIFF_CORE] chipNotNwell < 0.34 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q0chipNotNwellenc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| GATE_outsidetunm = GATE NOT tunm |
| tunm_outsidednwell = (tunm NOT dnwell) NOT exempt_tech_CD |
| tunm_not_techCD = tunm NOT exempt_tech_CD |
| "r_451_tunm.1" { |
| @ tunm.1: 0.41 min. width of tunm |
| INTERNAL tunm < 0.41 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_452_tunm.2" { |
| @ tunm.2: 0.5 min. spacing/notch of tunm |
| EXTERNAL tunm < 0.5 ABUT < 90 SINGULAR REGION |
| } |
| "r_453_tunm.3" { |
| @ tunm.3: 0.095 min. extension of tunm beyond gate |
| ENCLOSURE GATE tunm < 0.095 MEASURE COINCIDENT ABUT < 90 SINGULAR |
| } |
| "r_454_tunm.4" { |
| @ tunm.4: 0.095 min. spacing of GATE_outsidetunm & tunm |
| EXTERNAL GATE_outsidetunm tunm < 0.095 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_455_tunm.5" { |
| @ tunm.5: gate must not straddle tunm |
| CUT GATE tunm |
| } |
| "r_456_tunm.6a" { |
| @ tunm.6a: tunm outside deep nwell is not allowed |
| COPY tunm_outsidednwell |
| } |
| "r_457_tunm.7" { |
| @ tunm.7: 0.672 min. area of tunm |
| AREA tunm < 0.672 |
| } |
| "r_458_tunm.8" { |
| @ tunm.8: tunm must be enclosed by COREID |
| tunm NOT COREID |
| } |
| nsdmHole = (HOLES nsdm) NOT nsdm |
| psdmHole = (HOLES psdm) NOT psdm |
| bad_ndiff_nobut = (ENCLOSURE [NDIFF] nsdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE tap |
| bad_pdiff_nobut = (ENCLOSURE [PDIFF] psdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE tap |
| bad_enclose_ntap = (ENCLOSURE [NTAP_PERI] nsdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE diff |
| bad_enclose_ptap = (ENCLOSURE [PTAP_PERI] psdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE diff |
| psd_c1a = (INTERNAL psdm < 0.38 OPPOSITE PARALLEL ONLY REGION) INSIDE COREID |
| nsd_c1a = (INTERNAL nsdm < 0.38 OPPOSITE PARALLEL ONLY REGION) INSIDE COREID |
| nsd_c5a = (ENCLOSURE [NTAP_CORE] nsdm < 0.13 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE diff |
| psd_c5b = (ENCLOSURE [PTAP_CORE] psdm < 0.12 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE diff |
| ENIDgate = poly AND (ENID OR EXTDRAIN20) |
| ENIDsource = INTERACT diff ENIDgate |
| ENIDNsource = NOT INTERACT NDIFF ENIDgate |
| pDiffTapNotENIDsource = pDiffTap NOT (ENIDsource OR ZENERID) |
| nsdmZENERID = nsdm NOT ZENERID |
| psdmZENERID = psdm NOT ZENERID |
| nDiffTapNotENIDsource = (ndiffTap NOT ENIDsource) NOT SEALID_6um |
| nDiffTapNotENIDsource_not_gated_npn = nDiffTapNotENIDsource NOT (gated_npn OR ZENERID) |
| q0nsdm = INTERNAL nsdm < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q3nsdm = q0nsdm OUTSIDE COREID |
| q7nsdm = nsdm NOT COREID |
| q6nsdm = INTERNAL q7nsdm < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q1nsdm = q6nsdm INSIDE (CUT q0nsdm COREID) |
| q2nsdm = SIZE q1nsdm BY 0.005 INSIDE OF q0nsdm STEP 0.38 |
| "r_459_nsd.1" { |
| @ nsd.1: 0.38 min. width of nsdm across areaid:ce |
| COPY q2nsdm |
| } |
| "r_460_nsd.1" { |
| @ nsd.1: 0.38 min. width of nsdm in PERI |
| COPY q3nsdm |
| } |
| q4nsdm = INTERNAL nsdm < 0.29 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q5nsdm = q4nsdm INSIDE COREID |
| "r_461_nsd.c1b" { |
| @ nsd.c1b: 0.29 min. width of nsdm in COREID |
| COPY q5nsdm |
| } |
| "r_462_nsd.2" { |
| @ nsd.2: 0.38 min. spacing/notch of "nsdm" in periphery |
| EXTERNAL nsdm_PERI < 0.38 ABUT < 90 SINGULAR REGION |
| } |
| "r_463_nsd.2" { |
| @ nsd.2: 0.38 min. spacing of nsdm across COREID boundary |
| EXTERNAL nsdm_CORE nsdm_PERI > 0 < 0.38 ABUT > 0 < 90 SINGULAR REGION |
| } |
| /// nsd.3 is handled by design |
| "r_464_nsd.5a" { |
| @ nsd.5a: 0.125 min. enclosure of n+ diff by nsdm |
| COPY bad_ndiff_nobut |
| } |
| "r_465_nsd.5b" { |
| @ nsd.5b: 0.125 min. enclosure of n+ tap in peri by nsdm |
| COPY bad_enclose_ntap |
| } |
| /// nsd.6 is handled by nsd.9 |
| "r_466_nsd.7" { |
| @ nsd.7: 0.13 min. spacing of nsdm & opposite implant diffTap |
| EXTERNAL nsdm diffTap < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_467_nsd.8" { |
| @ nsd.8: nsdm must not overlap pdiff/ptap (source of extendedDrain fet exempted) |
| nsdm AND pDiffTapNotENIDsource |
| } |
| "r_468_nsd.9" { |
| @ nsd.9: ndiff/ntap (source of extendedDrain fet and gated_npn exempted) must be enclosed by nsdmZENERID |
| nDiffTapNotENIDsource_not_gated_npn NOT nsdmZENERID |
| } |
| "r_469_nsd.10a" { |
| @ nsd.10a: 0.265 min. area of nsdm |
| AREA nsdm < 0.265 |
| } |
| "r_470_nsd.11" { |
| @ nsd.11: 0.265 min. area of nsdmHole |
| AREA nsdmHole < 0.265 |
| } |
| "r_471_nsd.c1a" { |
| @ nsd.c1a: 0.38 min. width of nsdm (opposite parallel) |
| COPY nsd_c1a |
| } |
| "r_472_nsd.c2a" { |
| @ nsd.c2a: 0.38 min. spacing/notch of "nsdm" in core |
| EXTERNAL nsdm_CORE < 0.38 REGION PARALLEL ONLY OPPOSITE |
| } |
| "r_473_nsd.c2b" { |
| @ nsd.c2b: 0.29 min. spacing/notch of "nsdm" in core |
| EXTERNAL nsdm_CORE < 0.29 ABUT < 90 SINGULAR REGION |
| } |
| "r_474_nsd.c5a" { |
| @ nsd.c5a: 0.13 min. enclosure of n+ tap in core by nsdm |
| COPY nsd_c5a |
| } |
| q0psdm = INTERNAL psdm < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q3psdm = q0psdm OUTSIDE COREID |
| q7psdm = psdm NOT COREID |
| q6psdm = INTERNAL q7psdm < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q1psdm = q6psdm INSIDE (CUT q0psdm COREID) |
| q2psdm = SIZE q1psdm BY 0.005 INSIDE OF q0psdm STEP 0.38 |
| "r_475_psd.1" { |
| @ psd.1: 0.38 min. width of psdm across areaid:ce |
| COPY q2psdm |
| } |
| "r_476_psd.1" { |
| @ psd.1: 0.38 min. width of psdm in PERI |
| COPY q3psdm |
| } |
| q4psdm = INTERNAL psdm < 0.29 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q5psdm = q4psdm INSIDE COREID |
| "r_477_psd.c1b" { |
| @ psd.c1b: 0.29 min. width of psdm in COREID |
| COPY q5psdm |
| } |
| "r_478_psd.2" { |
| @ psd.2: 0.38 min. spacing/notch of "psdm" in periphery |
| EXTERNAL psdm_PERI < 0.38 ABUT < 90 SINGULAR REGION |
| } |
| "r_479_psd.2" { |
| @ psd.2: 0.38 min. spacing of psdm across COREID boundary |
| EXTERNAL psdm_CORE psdm_PERI > 0 < 0.38 ABUT > 0 < 90 SINGULAR REGION |
| } |
| /// psd.3 is handled by design |
| "r_480_psd.5a" { |
| @ psd.5a: 0.125 min. enclosure of p+ diff by psdm |
| COPY bad_pdiff_nobut |
| } |
| "r_481_psd.5b" { |
| @ psd.5b: 0.125 min. enclosure of p+ tap in peri by psdm |
| COPY bad_enclose_ptap |
| } |
| /// psd.6 is handled by psd.9 |
| "r_482_psd.7" { |
| @ psd.7: 0.13 min. spacing of psdm & opposite implant diffTap |
| EXTERNAL psdm diffTap < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_483_psd.8" { |
| @ psd.8: psdm must not overlap ndiff/ntap (source of extendedDrain fet exempted) |
| psdm AND nDiffTapNotENIDsource |
| } |
| "r_484_psd.9" { |
| @ psd.9: pdiff/ptap (source of extendedDrain fet exempted) must be enclosed by psdmZENERID |
| pDiffTapNotENIDsource NOT psdmZENERID |
| } |
| "r_485_psd.10b" { |
| @ psd.10b: 0.255 min. area of psdm |
| AREA psdm < 0.255 |
| } |
| "r_486_psd.11" { |
| @ psd.11: 0.265 min. area of psdmHole |
| AREA psdmHole < 0.265 |
| } |
| "r_487_psd.c1a" { |
| @ psd.c1a: 0.38 min. width of psdm (opposite parallel) |
| COPY psd_c1a |
| } |
| "r_488_psd.c2a" { |
| @ psd.c2a: 0.38 min. spacing/notch of "psdm" in core |
| EXTERNAL psdm_CORE < 0.38 REGION PARALLEL ONLY OPPOSITE |
| } |
| "r_489_psd.c2b" { |
| @ psd.c2b: 0.29 min. spacing/notch of "psdm" in core |
| EXTERNAL psdm_CORE < 0.29 ABUT < 90 SINGULAR REGION |
| } |
| "r_490_psd.c5b" { |
| @ psd.c5b: 0.12 min. enclosure of p+ tap in core by psdm |
| COPY psd_c5b |
| } |
| nwellNoHv = nwell NOT hvi |
| hvi_peri = hvi NOT COREID |
| HVnwell = INTERACT nwell (nwell AND hvi) |
| nonCoinHviNwellEdges = hvi NOT COINCIDENT EDGE nwell |
| nwellHviSpacErr = EXTERNAL nonCoinHviNwellEdges nwell < 0.7 ABUT < 90 REGION EXCLUDE FALSE |
| "r_491_hvi.1" { |
| @ hvi.1: 0.6 min. width of hvi_peri |
| INTERNAL hvi_peri < 0.6 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_492_hvi.2a" { |
| @ hvi.2a: 0.7 min. spacing/notch of hvi_peri |
| EXTERNAL hvi_peri < 0.7 ABUT < 90 SINGULAR REGION |
| } |
| "r_493_hvi.4" { |
| @ hvi.4: hvi must not overlap tunm |
| hvi AND tunm |
| } |
| "r_494_hvi.5" { |
| @ hvi.5: 0.7 min. spacing between non-butting hvi and nwell |
| COPY nwellHviSpacErr |
| } |
| nwellHV = (nwell AND hvi) NOT exempt_tech_CD |
| nwellHVID = (INTERACT nwell HVNID) NOT exempt_tech_CD |
| HV_nwelltmp = nwellHV OR nwellHVID |
| HV_nwell = STAMP HV_nwelltmp BY nwell |
| nwellLV = (nwell NOT hvi) NOT exempt_tech_CD |
| hvNwellConn = NET AREA RATIO nwellHV nwellLV > 0 |
| lvNwellConn = NET AREA RATIO nwellLV nwellHV > 0 |
| li1text = WITH TEXT li1 "lv_net" textlabel |
| HVIDext = NET AREA RATIO nwellHV nwellHVID > 0 |
| lvexmpt1 = NET AREA RATIO nwellHV li1text > 0 |
| nwellHVLVerror = hvNwellConn NOT (lvexmpt1 OR HVIDext) |
| nwellLVHVerror = (NET AREA RATIO lvNwellConn nwellHVLVerror > 0) NOT nwellHVID |
| nwell_10_error = nwellLVHVerror OR nwellHVLVerror |
| nwell7P2V = WITH TEXT nwell "shv_nwell" |
| nwellLess2P5 = EXTERNAL nwell < 2.5 ABUT < 90 REGION |
| checkNwell_1 = INTERACT nwell nwellLess2P5 |
| nwell7P2VCheck = nwell7P2V AND checkNwell_1 |
| nwellCheck = nwell AND checkNwell_1 |
| "r_495_nwell.8" { |
| @ nwell.8: 2 min. spacing of HV_nwell & nwell |
| EXTERNAL HV_nwell nwell < 2.0 ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE |
| } |
| "r_496_hv.nwell.1" { |
| @ hv.nwell.1: 2.5 min. spacing of nwell with text (shv_nwell) & nwell |
| EXTERNAL nwell7P2VCheck nwellCheck < 2.5 ABUT < 90 SINGULAR REGION NOT CONNECTED EXCLUDE FALSE |
| } |
| "r_497_nwell.9" { |
| @ nwell.9: HVnwell must be enclosed by hvi |
| HVnwell NOT hvi |
| } |
| "r_498_nwell.10" { |
| @ nwell.10: LVnwell should not be on the same net as HVnwell |
| COPY nwell_10_error |
| } |
| diffHV = diff AND hvi |
| diffHV_CORE = diffHV AND COREID |
| diffHV_PERI = diffHV NOT COREID |
| diffHVpRes_PERI = diffHV_PERI AND (diffRes AND nwell) |
| diffHVpResNormSize = INTERACT diffHVpRes_PERI (EXPAND EDGE (LENGTH (diffHVpRes_PERI INSIDE EDGE diffHV) >= 0.29) INSIDE BY 0.005) |
| diffHVnopRes_PERI = (diffHV_PERI NOT diffHVpRes_PERI) OR diffHVpResNormSize |
| ndiffHV = NDIFF AND hvi |
| ndiffHV_PERI = ndiffHV NOT COREID |
| tapHV = tap AND hvi |
| tapHV_PERI = tapHV NOT COREID |
| ptapHV = PTAP AND hvi |
| ptapHV_PERI = ptapHV NOT COREID |
| diffTapHV = diffTap AND hvi |
| diffTapHV_PERI_nonUHVI = diffTapHV NOT (COREID OR uhvi) |
| diffTapNoHv = diffTap NOT hvi |
| diffTapNoHv_PERI = diffTapNoHv NOT COREID |
| nTapHV_nonESD_uhvi = NTAP_nonESD_nonuhvi AND (hvi OR HVNID) |
| ptapHV_PERI_noAbut = NOT TOUCH ptapHV_PERI ndiffHV_PERI |
| PTAP_noPwellRes = PTAP NOT (TOUCH PTAP pwres) |
| ndiffHV_nonESD = (ndiffHV NOT ESDID) NOT ENID |
| ndiff_nonESD = (NDIFF NOT ESD_nwell_tap) NOT ENID |
| pdiffHV_nonESD = ((PDIFF NOT ESD_nwell_tap) AND (hvi OR HVNID)) NOT (ENID OR uhvi) |
| diffHV_noUHVI = diffHV NOT uhvi |
| tapHV_noUHVI = tapHV NOT uhvi |
| ndiff_nonESDuhvi = ndiff_nonESD NOT uhvi |
| ndiffHV_nonESDuhvi = ndiffHV_nonESD NOT uhvi |
| PTAP_noPwellRes_noUHVI = PTAP_noPwellRes NOT uhvi |
| "r_499_difftap.14" { |
| @ difftap.14: 0.29 min. width of Hdiff in periphery not Hv Pdiff Res |
| INTERNAL diffHVnopRes_PERI < 0.29 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_500_difftap.14a" { |
| @ difftap.14a: 0.15 min. width of Hv Pdiff Res in periphery |
| INTERNAL diffHVpRes_PERI < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_501_difftap.15a" { |
| @ difftap.15a: 0.3 min. spacing/notch of Hdiff in periphery |
| EXTERNAL diffHV_PERI < 0.3 ABUT < 90 SINGULAR REGION |
| } |
| "r_502_difftap.15b" { |
| @ difftap.15b: 0.37 min. spacing of n+ diff inside hvi in periphery & ptapHV_PERI_noAbut |
| EXTERNAL ndiffHV_PERI ptapHV_PERI_noAbut < 0.37 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_503_difftap.16" { |
| @ difftap.16: 0.7 min. width of tapHV butting diffHV_noUHVI |
| q0diffHV_noUHVI = diffHV_noUHVI COINCIDENT OUTSIDE EDGE tapHV |
| ENCLOSURE q0diffHV_noUHVI tapHV < 0.7 ABUT < 90 MEASURE COINCIDENT REGION |
| } |
| "r_504_difftap.16" { |
| @ difftap.16: 0.7 min. width of tapHV_noUHVI butting & between Hdiff |
| q0tapHV_noUHVI = tapHV_noUHVI COINCIDENT OUTSIDE EDGE diffHV |
| INTERNAL q0tapHV_noUHVI < 0.7 ABUT < 90 REGION |
| } |
| "r_505_difftap.17" { |
| @ difftap.17: 0.33 min. enclosure of p+ Hdiff (no ESD)(no UHVI) by HV_nwell |
| q0pdiffHV_nonESDand = pdiffHV_nonESD AND HV_nwell |
| ENCLOSURE q0pdiffHV_nonESDand HV_nwell < 0.33 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_506_difftap.18" { |
| @ difftap.18: 0.43 min. spacing of ndiff_nonESDuhvi & HV_nwell |
| EXTERNAL ndiff_nonESDuhvi HV_nwell < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_507_difftap.19" { |
| @ difftap.19: 0.33 min. enclosure of n+ Htap (no ESD)(no UHVI) by HV_nwell |
| q0nTapHV_nonESD_uhviand = nTapHV_nonESD_uhvi AND HV_nwell |
| ENCLOSURE q0nTapHV_nonESD_uhviand HV_nwell < 0.33 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_508_difftap.20" { |
| @ difftap.20: 0.43 min. spacing of PTAP_noPwellRes_noUHVI & HV_nwell |
| EXTERNAL PTAP_noPwellRes_noUHVI HV_nwell < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_509_difftap.21" { |
| @ difftap.21: "diffTap" in periphery must not straddle hvi |
| CUT diffTap_PERI hvi |
| } |
| "r_510_difftap.22" { |
| @ difftap.22: 0.18 min. enclosure of Hdiff/Htap in periphery without UHVI by hvi |
| q0diffTapHV_PERI_nonUHVIand = diffTapHV_PERI_nonUHVI AND hvi |
| ENCLOSURE q0diffTapHV_PERI_nonUHVIand hvi < 0.18 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_511_difftap.23" { |
| @ difftap.23: 0.18 min. spacing of diffTapNoHv_PERI & hvi |
| EXTERNAL diffTapNoHv_PERI hvi < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_512_difftap.24" { |
| @ difftap.24: 0.43 min. spacing of ndiffHV_nonESDuhvi & nwell |
| EXTERNAL ndiffHV_nonESDuhvi nwell < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| /// difftap.25 is not checked |
| "r_513_difftap.c11" { |
| @ difftap.c11: 0.15 min. width of Hdiff in COREID |
| INTERNAL diffHV_CORE < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| gateHV_PERI = GATE_PERI AND hvi |
| gateEdgeHV_PERI = poly COINCIDENT EDGE gateHV_PERI |
| gateEdgeHV_PERI_err = INTERNAL gateEdgeHV_PERI < 0.5 OPPOSITE PARALLEL ONLY REGION |
| "r_514_poly.13" { |
| @ poly.13: 0.5 min. width of poly over diff inside hvi in periphery |
| INTERNAL gateEdgeHV_PERI_err < 0.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_515_poly.14" { |
| @ poly.14: gate must not straddle hvi |
| CUT GATE hvi |
| } |
| pfetOnLvtn = INTERACT PFET (PFET AND lvtn) |
| pLowVTEdge = pfetOnLvtn COINCIDENT OUTSIDE EDGE SRCDRN |
| BadpLowVTgate = (INTERNAL pLowVTEdge < 0.35 OPPOSITE PARALLEL ONLY REGION) NOT tableH3rfFets |
| PolyNoRes = poly NOT polyAndRes |
| PolyNotLvNwell = (poly NOT lvNwell_drc) NOT (exemptNhvnativeCell OR |
| (gated_npn OR uhvi)) |
| PolyInFGR = poly AND exemptNhvnativeCell |
| GATESIDE_PERI = GATESIDE OUTSIDE EDGE COREID |
| GATEEND_PERI = GATEEND OUTSIDE EDGE COREID |
| polyGapLEedg = LENGTH poly_CORE <= 0.15 |
| polyGapLEedgSz = EXPAND EDGE polyGapLEedg OUTSIDE BY (0.16 / 2) |
| polyGapRegion = EXTERNAL polyGapLEedg <= 0.16 OPPOSITE REGION |
| polyGapGoodSp = polyGapLEedgSz INSIDE polyGapRegion |
| badPoly_c2 = INTERACT (EXTERNAL poly_CORE < 0.16 ABUT < 90 REGION SINGULAR) polyGapGoodSp |
| badPoly_c3 = NOT INTERACT (EXTERNAL poly_CORE < 0.175 ABUT < 90 REGION SINGULAR) polyGapGoodSp |
| PolyNotLvNwellnoUHVI = PolyNotLvNwell NOT UHVI |
| evansXmtCell = EXTENT CELL "sr_bltd_eq" ORIGINAL |
| poly2noXmt = poly NOT evansXmtCell |
| "r_516_poly.1a" { |
| @ poly.1a: 0.15 min. width of poly |
| INTERNAL poly < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_517_poly.1b" { |
| @ poly.1b: poly.1b: 0.350 min. channel length of pfet overlapping lvtn |
| COPY BadpLowVTgate |
| } |
| "r_518_poly.2" { |
| @ poly.2: 0.21 min. spacing/notch of "poly" in periphery |
| EXTERNAL poly_PERI < 0.21 ABUT < 90 SINGULAR REGION |
| } |
| poly2noXmt_CORE = poly2noXmt AND COREID |
| poly2noXmt_PERI = poly2noXmt NOT COREID |
| "r_519_poly.2" { |
| @ poly.2: 0.21 min. spacing of poly2noXmt across COREID boundary |
| EXTERNAL poly2noXmt_CORE poly2noXmt_PERI > 0 < 0.21 ABUT > 0 < 90 SINGULAR REGION |
| } |
| "r_520_poly.c3" { |
| @ poly.c3: poly.c3: 0.175 min. spacing of poly (except for poly.c2) |
| COPY badPoly_c3 |
| } |
| "r_521_poly.c2" { |
| @ poly.c2: poly.c2: 0.160 min. spacing of poly for poly core gap |
| COPY badPoly_c2 |
| } |
| q0polyAndRes = PolyNoRes COINCIDENT OUTSIDE EDGE polyAndRes |
| q1polyAndRes = LENGTH q0polyAndRes < 0.33 |
| "r_522_poly.3" { |
| @ poly.3: 0.33 min. width of poly resistor |
| q2polyAndRes = EXPAND EDGE q1polyAndRes OUTSIDE BY 0.005 CORNER FILL |
| q3polyAndRes = polyAndRes WITH EDGE (polyAndRes COINCIDENT EDGE q2polyAndRes) |
| q4polyAndRes = polyAndRes OUTSIDE EDGE PolyNoRes |
| q5polyAndRes = EXPAND EDGE q4polyAndRes INSIDE BY 0.16 CORNER FILL |
| q6polyAndRes = polyAndRes NOT q5polyAndRes |
| q7polyAndRes = INTERNAL q6polyAndRes < 0.005 ABUT < 90 REGION |
| q8polyAndRes = q6polyAndRes NOT q7polyAndRes |
| q9polyAndRes = INTERACT polyAndRes (polyAndRes AND q8polyAndRes) == 1 |
| q10polyAndRes = polyAndRes NOT q9polyAndRes |
| q3polyAndRes OR q10polyAndRes |
| } |
| "r_523_poly.4" { |
| @ poly.4: 0.075 min. spacing of "poly" in periphery & diff |
| EXTERNAL poly_PERI diff < 0.075 ABUT == 0 REGION PARALLEL ONLY EXCLUDE FALSE |
| } |
| "r_524_poly.5" { |
| @ poly.5: 0.055 min. spacing of "poly" in periphery & tap |
| EXTERNAL poly_PERI tap < 0.055 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_525_poly.6" { |
| @ poly.6: 0.3 min. extension of diff edge butting tap beyond gate edge in periphery |
| ENCLOSURE GATESIDE_PERI diffTapEdge < 0.3 MEASURE COINCIDENT ABUT < 90 |
| } |
| "r_526_poly.7" { |
| @ poly.7: 0.25 min. extension of diff beyond gate edge in periphery |
| ENCLOSURE GATESIDE_PERI diff < 0.25 MEASURE COINCIDENT ABUT < 90 |
| } |
| "r_527_poly.8" { |
| @ poly.8: 0.13 min. extension of poly beyond gate end in periphery |
| ENCLOSURE GATEEND_PERI poly < 0.13 MEASURE COINCIDENT ABUT < 90 |
| } |
| "r_528_poly.9" { |
| @ poly.9: 0.48 min. spacing of poly resistor & diffTap |
| EXTERNAL polyAndRes diffTap < 0.48 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_529_poly.9" { |
| @ poly.9: poly resistor must not overlap diffTap |
| polyAndRes AND diffTap |
| } |
| "r_530_poly.9" { |
| @ poly.9: 0.48 min. spacing of poly resistor & poly |
| EXTERNAL polyAndRes poly < 0.48 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| q10diff = poly AND diff |
| q11diff = NOT RECTANGLE q10diff ORTHOGONAL ONLY |
| q12diff = EXTERNAL q11diff <= 0.005 ABUT REGION |
| q13diff = q12diff AND poly |
| "r_531_poly.10" { |
| @ poly.10: poly must not overlap any inner corner of diff |
| COPY q13diff |
| } |
| q0poly = poly AND diff |
| q1poly = NOT RECTANGLE q0poly ORTHOGONAL ONLY |
| q2poly = INTERNAL q1poly <= 0.005 ABUT == 90 PERPENDICULAR ONLY REGION |
| q4poly = q2poly WITH EDGE (q2poly COINCIDENT INSIDE EDGE diff) |
| q6poly = q2poly NOT q4poly |
| q3poly = EXTERNAL q1poly <= 0.005 ABUT == 90 PERPENDICULAR ONLY REGION |
| q5poly = TOUCH q3poly diff |
| q7poly = q3poly NOT q5poly |
| q8poly = q6poly OR q7poly |
| "r_532_poly.11" { |
| @ poly.11: No 90 degree bends of poly on diff |
| COPY q8poly |
| } |
| "r_533_poly.12" { |
| @ poly.12: PolyNotLvNwellnoUHVI must not overlap "tap" in periphery |
| PolyNotLvNwellnoUHVI AND tap_PERI |
| } |
| "r_534_poly.15" { |
| @ poly.15: poly must not overlap diffres |
| poly AND diffres |
| } |
| "r_535_poly.c1" { |
| @ poly.c1: 0.03 min. spacing of "poly" in core & diff |
| EXTERNAL poly_CORE diff < 0.03 ABUT == 0 REGION PARALLEL ONLY EXCLUDE FALSE |
| } |
| "r_536_poly.c1" { |
| @ poly.c1: 0.03 min. spacing of "poly" in core & tap |
| EXTERNAL poly_CORE tap < 0.03 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| MOSDIFFandPOLY = diff AND poly |
| derivedGate = MOSDIFFandPOLY OUTSIDE polyGate |
| userGate = MOSDIFFandPOLY AND polyGate |
| allGatetmp = (derivedGate OR userGate) NOT (ENID OR EXTDRAIN20) |
| drainGate = EXPAND EDGE (MOSDIFFandPOLY COINCIDENT INSIDE EDGE poly) OUTSIDE BY 0.005 |
| remGate = TOUCH allGatetmp drainGate == 1 |
| allGate = allGatetmp NOT remGate |
| esdGate = allGate AND ESDID |
| nesd = esdGate NOT nwell |
| nesdHV = INTERACT nesd hvi |
| nhvnativeesd = nesdHV AND lvtn |
| nhvesd = nesdHV NOT nhvnativeesd |
| nshortesd = nesd NOT nesdHV |
| pesd = esdGate AND nwell |
| phvesd = INTERACT pesd hvi |
| nwellENID = INTERACT nwell ENID |
| nwellEXTDRAIN20 = INTERACT nwell EXTDRAIN20 |
| allENIDgate = ENID AND (POLY AND hvi) |
| allEXTDRAIN20gate = EXTDRAIN20 AND (POLY AND hvi) |
| pfetExtDrTmp = allENIDgate AND dnwell |
| nfetExtDrTmp = allENIDgate NOT dnwell |
| nfetExtDr20Tmp = allEXTDRAIN20gate NOT dnwell |
| nfetExtDr = nfetExtDrTmp NOT nwellENID |
| nfetExtDr20 = nfetExtDr20Tmp NOT nwellEXTDRAIN20 |
| pfetExtDr = pfetExtDrTmp AND nwellENID |
| nvhv = COPY nfetExtDr |
| n20vhv1 = COPY nfetExtDr20 |
| pvhv = COPY pfetExtDr |
| fetGate = allGate NOT esdGate |
| nfet_dev = fetGate NOT nwell |
| pfet_dev = fetGate AND nwell |
| hvinmos = INTERACT nfet_dev hvi |
| hvilvtnfet = lvtnfet AND hvinmos |
| s8rf_npn1x1_2p0_HV_cell = EXTENT CELL "s8rf_npn1x1_2p0_HV_cell" ORIGINAL |
| lvtnfet = (INTERACT nfet_dev lvtn) NOT nlvtpass |
| fnpass = (WITH TEXT (ldntm AND |
| (nfet_dev AND hvinmos)) "fnpass" polyModel) AND COREID |
| npass = (WITH TEXT nfet_dev "npass" polyModel) AND COREID |
| nlvtpass = (WITH TEXT nfet_dev "nlvtpass" polyModel) AND COREID |
| npd = (WITH TEXT nfet_dev "npd" polyModel) AND COREID |
| ppu = (WITH TEXT pfet_dev "ppu" polyModel) AND COREID |
| ntvnative = (hvilvtnfet NOT fnpass) AND LVID |
| nhvnative = (hvilvtnfet NOT fnpass) NOT LVID |
| nhvnative_L_0_75_tmp = LENGTH (nhvnative COINCIDENT INSIDE EDGE diff) == 0.75 |
| nhvnative_L_0_75_W_4_3_exempt = (INTERNAL nhvnative_L_0_75_tmp == 4.3 OPPOSITE PARALLEL ONLY REGION) AND exemptNhvnativeCell |
| nhvnative_L_0_75_W_4_3_bad = (INTERNAL nhvnative_L_0_75_tmp == 4.3 OPPOSITE PARALLEL ONLY REGION) NOT exemptNhvnativeCell |
| sonos_p = lvtnfet AND (dnwell AND |
| (ldntm AND tunm)) |
| sonos_e = COPY sonos_p |
| phighvt = (INTERACT pfet_dev hvtp) NOT ppu |
| phv = (INTERACT pfet_dev hvi) NOT (pvhv OR phvesd) |
| rfGate = GATE AND (INSIDE CELL poly "s8rf_xcmvpp1_nwell" "s8rf_xcmvpp1" "xcmvpp2" "xcmvpp1" "s8rf_pmedlvt_W1p68_L0p15_4F" "s8rf_pmedlvt_W1p68_L0p15_2F" "s8rf_pmedlvt_W0p84_L0p15_2F" "s8rf_pshort_W5p0_L0p15_2F" "s8rf_pshort_W3p0_L0p15_2F" "s8rf_pshort_W1p68_L0p15_4F" "s8rf_pshort_W1p68_L0p15_2F" "s8rf_pshort_W0p84_L0p15_2F" "s8rf_pshort_W5p0_L0p25_M4_b" "s8rf_pshort_W5p0_L0p25_M2_b" "s8rf_pshort_W5p0_L0p18_M4_b" "s8rf_pshort_W5p0_L0p18_M2_b" "s8rf_pshort_W5p0_L0p15_M4_b" "s8rf_pshort_W5p0_L0p15_M2_b" "s8rf_pshort_W3p0_L0p25_M4_b" "s8rf_pshort_W3p0_L0p25_M2_b" "s8rf_pshort_W3p0_L0p18_M4_b" "s8rf_pshort_W3p0_L0p18_M2_b" "s8rf_pshort_W3p0_L0p15_M4_b" "s8rf_pshort_W3p0_L0p15_M2_b" "s8rf_pshort_W1p65_L0p25_M4_b" "s8rf_pshort_W1p65_L0p25_M2_b" "s8rf_pshort_W1p65_L0p18_M4_b" "s8rf_pshort_W1p65_L0p18_M2_b" "s8rf_pshort_W1p65_L0p15_M4_b" "s8rf_pshort_W1p65_L0p15_M2_b" "s8rf_nshort_W5p0_L0p25_M4_b" "s8rf_nshort_W5p0_L0p25_M2_b" "s8rf_nshort_W5p0_L0p18_M4_b" "s8rf_nshort_W5p0_L0p18_M2_b" "s8rf_nshort_W5p0_L0p15_M4_b" "s8rf_nshort_W5p0_L0p15_M2_b" "s8rf_nshort_W3p0_L0p25_M4_b" "s8rf_nshort_W3p0_L0p25_M2_b" "s8rf_nshort_W3p0_L0p18_M4_b" "s8rf_nshort_W3p0_L0p18_M2_b" "s8rf_nshort_W3p0_L0p15_M4_b" "s8rf_nshort_W3p0_L0p15_M2_b" "s8rf_nshort_W1p65_L0p25_M4_b" "s8rf_nshort_W1p65_L0p25_M2_b" "s8rf_nshort_W1p65_L0p18_M4_b" "s8rf_nshort_W1p65_L0p18_M2_b" "s8rf_nshort_W1p65_L0p15_M4_b" "s8rf_nshort_W1p65_L0p15_M2_b" "s8rf_nlowvt_W3p0_L0p15_8F" "s8rf_nlowvt_W3p0_L0p15_4F" "s8rf_nlowvt_W3p0_L0p15_2F" "s8rf_nlowvt_W0p84_L0p15_8F" "s8rf_nlowvt_W0p84_L0p15_4F" "s8rf_nlowvt_W0p84_L0p15_2F" "s8rf_nlowvt_W0p42_L0p15_2F" "s8rf_nlowvt_W5p0_L0p25_M4_b" "s8rf_nlowvt_W5p0_L0p25_M2_b" "s8rf_nlowvt_W5p0_L0p18_M4_b" "s8rf_nlowvt_W5p0_L0p18_M2_b" "s8rf_nlowvt_W5p0_L0p15_M4_b" "s8rf_nlowvt_W5p0_L0p15_M2_b" "s8rf_nlowvt_W3p0_L0p25_M4_b" "s8rf_nlowvt_W3p0_L0p25_M2_b" "s8rf_nlowvt_W3p0_L0p18_M4_b" "s8rf_nlowvt_W3p0_L0p18_M2_b" "s8rf_nlowvt_W3p0_L0p15_M4_b" "s8rf_nlowvt_W3p0_L0p15_M2_b" "s8rf_nlowvt_W1p65_L0p25_M4_b" "s8rf_nlowvt_W1p65_L0p25_M2_b" "s8rf_nlowvt_W1p65_L0p18_M4_b" "s8rf_nlowvt_W1p65_L0p18_M2_b" "s8rf_nlowvt_W1p65_L0p15_M4_b" "s8rf_nlowvt_W1p65_L0p15_M2_b" "s8rf_nhv_W5p0_L0p5_M2_b" "s8rf_nhv_W3p0_L0p5_M2_b" "s8rf_nhv_W7p0_L0p5_M4_b" "s8rf_nhv_W7p0_L0p5_M10_b" "s8rf_nhv_W5p0_L0p5_M4_b" "s8rf_nhv_W5p0_L0p5_M10_b" "s8rf_nhv_W3p0_L0p5_M4_b" "s8rf_nhv_W3p0_L0p5_M10_b") |
| nhv = (hvinmos NOT (nhvnative OR |
| (ntvnative OR |
| (fnpass OR |
| (nhvesd OR |
| (nhvnativeesd OR |
| (nvhv OR n20vhv1))))))) NOT rfGate |
| nlowvt = (lvtnfet NOT (hvilvtnfet OR |
| (sonos_p OR |
| (ldntm OR tunm)))) NOT rfGate |
| nshort = (nfet_dev NOT (lvtnfet OR |
| (hvinmos OR |
| (nshortesd OR |
| (npass OR |
| (npd OR nlvtpass)))))) NOT rfGate |
| badnfet = nfet_dev NOT (nshort OR |
| (lvtnfet OR |
| (hvinmos OR |
| (nshortesd OR |
| (npass OR |
| (npd OR |
| (nlvtpass OR rfGate))))))) |
| plowvt = (pfet_dev AND lvtn) NOT rfGate |
| pshort = (pfet_dev NOT (phv OR |
| (phighvt OR |
| (plowvt OR |
| (phvesd OR ppu))))) NOT rfGate |
| badpfet = pfet_dev NOT (pshort OR |
| (phv OR |
| (phighvt OR |
| (plowvt OR |
| (phvesd OR |
| (ppu OR rfGate)))))) |
| rfNMOS = rfGate NOT nwell |
| dummy_rfGate = (WITH TEXT rfGate "dummy_poly" textlabel) NOT tableH3rfFets |
| dummy_nhv = (hvinmos NOT (nhvnative OR |
| (ntvnative OR |
| (fnpass OR |
| (nhvesd OR |
| (nhvnativeesd OR |
| (nvhv OR n20vhv1))))))) AND dummy_rfGate |
| dummy_nlowvt = (lvtnfet NOT (hvilvtnfet OR |
| (sonos_p OR |
| (ldntm OR tunm)))) AND dummy_rfGate |
| dummy_nshort = (nfet_dev NOT (lvtnfet OR |
| (hvinmos OR nshortesd))) AND dummy_rfGate |
| dummy_plowvt = (pfet_dev AND lvtn) AND dummy_rfGate |
| dummy_pshort = (pfet_dev NOT (phv OR |
| (phighvt OR |
| (plowvt OR phvesd)))) AND dummy_rfGate |
| "k_1_rfGate" { |
| @ keep: rfGate - rfGate |
| COPY rfGate |
| } |
| "r_537_dnwell.6" { |
| @ dnwell.6: rfNMOS must be enclosed by dnwell |
| rfNMOS NOT dnwell |
| } |
| "r_538_poly.X.1a" { |
| @ poly.X.1a: 0.5 min. width of dummy_nhv |
| q0dummy_nhvcoin = dummy_nhv INSIDE EDGE diff |
| dummy_nhv NOT (INTERNAL q0dummy_nhvcoin == 0.5 ABUT < 90 REGION) |
| } |
| "r_539_poly.X.1a" { |
| @ poly.X.1a: 0.15 min. width of dummy_nlowvt |
| q0dummy_nlowvtcoin = dummy_nlowvt INSIDE EDGE diff |
| dummy_nlowvt NOT (INTERNAL q0dummy_nlowvtcoin == 0.15 ABUT < 90 REGION) |
| } |
| "r_540_poly.X.1a" { |
| @ poly.X.1a: 0.15 min. width of dummy_nshort |
| q0dummy_nshortcoin = dummy_nshort INSIDE EDGE diff |
| dummy_nshort NOT (INTERNAL q0dummy_nshortcoin == 0.15 ABUT < 90 REGION) |
| } |
| "r_541_poly.X.1a" { |
| @ poly.X.1a: 0.15 min. width of dummy_pshort |
| q0dummy_pshortcoin = dummy_pshort INSIDE EDGE diff |
| dummy_pshort NOT (INTERNAL q0dummy_pshortcoin == 0.15 ABUT < 90 REGION) |
| } |
| "r_542_poly.X.1a" { |
| @ poly.X.1a: 0.35 min. width of dummy_plowvt |
| q0dummy_plowvtcoin = dummy_plowvt INSIDE EDGE diff |
| dummy_plowvt NOT (INTERNAL q0dummy_plowvtcoin == 0.35 ABUT < 90 REGION) |
| } |
| "r_543_POLY.X.1" { |
| @ POLY.X.1: This is an invalid nfet |
| COPY badnfet |
| } |
| "r_544_POLY.X.1" { |
| @ POLY.X.1: This is an invalid pfet |
| COPY badpfet |
| } |
| "r_545_POLY.X.1" { |
| @ POLY.X.1: This nhvnative is only allow in the FGR |
| COPY nhvnative_L_0_75_W_4_3_bad |
| } |
| deCapLength = (fetGate AND exemptDeCapCell) COINCIDENT INSIDE EDGE diff |
| deCapfet_L_0_170 = LENGTH deCapLength == 0.17 |
| deCapfet_L_0_590 = LENGTH deCapLength == 0.59 |
| deCapfet_L_0_650 = LENGTH deCapLength == 0.65 |
| deCapfet_L_1_050 = LENGTH deCapLength == 1.05 |
| deCapfet_L_1_130 = LENGTH deCapLength == 1.13 |
| deCapfet_L_1_970 = LENGTH deCapLength == 1.97 |
| deCapfet_L_2_090 = LENGTH deCapLength == 2.09 |
| deCapfet_L_2_890 = LENGTH deCapLength == 2.89 |
| deCapfet_L_3_050 = LENGTH deCapLength == 3.05 |
| deCapfet_L_4_730 = LENGTH deCapLength == 4.73 |
| deCapNfet_L_0_170_W_0_535 = (INTERNAL deCapfet_L_0_170 == 0.535 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_0_590_W_0_550 = (INTERNAL deCapfet_L_0_590 == 0.55 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_1_050_W_0_550 = (INTERNAL deCapfet_L_1_050 == 0.55 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_1_970_W_0_550 = (INTERNAL deCapfet_L_1_970 == 0.55 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_2_890_W_0_550 = (INTERNAL deCapfet_L_2_890 == 0.55 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_4_730_W_0_550 = (INTERNAL deCapfet_L_4_730 == 0.55 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_0_650_W_0_775 = (INTERNAL deCapfet_L_0_650 == 0.775 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_1_130_W_0_775 = (INTERNAL deCapfet_L_1_130 == 0.775 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_2_090_W_0_775 = (INTERNAL deCapfet_L_2_090 == 0.775 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapNfet_L_3_050_W_0_775 = (INTERNAL deCapfet_L_3_050 == 0.775 OPPOSITE PARALLEL ONLY REGION) AND nshort |
| deCapPfet_L_0_170_W_1_255 = (INTERNAL deCapfet_L_0_170 == 1.255 OPPOSITE PARALLEL ONLY REGION) AND pshort |
| deCapPfet_L_0_650_W_1_255 = (INTERNAL deCapfet_L_0_650 == 1.255 OPPOSITE PARALLEL ONLY REGION) AND pshort |
| deCapPfet_L_1_130_W_1_255 = (INTERNAL deCapfet_L_1_130 == 1.255 OPPOSITE PARALLEL ONLY REGION) AND pshort |
| deCapPfet_L_2_090_W_1_255 = (INTERNAL deCapfet_L_2_090 == 1.255 OPPOSITE PARALLEL ONLY REGION) AND pshort |
| deCapPfet_L_3_050_W_1_255 = (INTERNAL deCapfet_L_3_050 == 1.255 OPPOSITE PARALLEL ONLY REGION) AND pshort |
| deCapPfet_L_0_590_W_0_870 = (INTERNAL deCapfet_L_0_590 == 0.87 OPPOSITE PARALLEL ONLY REGION) AND phighvt |
| deCapPfet_L_1_050_W_0_870 = (INTERNAL deCapfet_L_1_050 == 0.87 OPPOSITE PARALLEL ONLY REGION) AND phighvt |
| deCapPfet_L_1_970_W_0_870 = (INTERNAL deCapfet_L_1_970 == 0.87 OPPOSITE PARALLEL ONLY REGION) AND phighvt |
| deCapPfet_L_2_890_W_0_870 = (INTERNAL deCapfet_L_2_890 == 0.87 OPPOSITE PARALLEL ONLY REGION) AND phighvt |
| deCapPfet_L_4_730_W_0_870 = (INTERNAL deCapfet_L_4_730 == 0.87 OPPOSITE PARALLEL ONLY REGION) AND phighvt |
| phighvt_L_0_18_W_0_54 = INTERNAL phighvt_L_0_18 == 0.54 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_70 = INTERNAL phighvt_L_0_18 == 0.7 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_75 = INTERNAL phighvt_L_0_18 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_79 = INTERNAL phighvt_L_0_18 == 0.79 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_94 = INTERNAL phighvt_L_0_18 == 0.94 OPPOSITE PARALLEL ONLY REGION |
| scs8hdllStndCell = EXTENT CELL "scs8hdll*" ORIGINAL |
| phighvt_L_0_18_W_valid = (phighvt_L_0_18_W_0_54 OR (phighvt_L_0_18_W_0_70 OR (phighvt_L_0_18_W_0_75 OR (phighvt_L_0_18_W_0_79 OR phighvt_L_0_18_W_0_94)))) AND scs8hdllStndCell |
| goodDecapNfets = deCapNfet_L_4_730_W_0_550 OR (deCapNfet_L_2_890_W_0_550 OR (deCapNfet_L_1_970_W_0_550 OR (deCapNfet_L_1_050_W_0_550 OR (deCapNfet_L_0_590_W_0_550 OR (deCapNfet_L_0_170_W_0_535 OR |
| ((deCapNfet_L_0_650_W_0_775 OR deCapNfet_L_1_130_W_0_775) OR (deCapNfet_L_2_090_W_0_775 OR deCapNfet_L_3_050_W_0_775))))))) |
| goodDecapPfets = deCapPfet_L_0_170_W_1_255 OR |
| ((deCapPfet_L_0_650_W_1_255 OR deCapPfet_L_1_130_W_1_255) OR (deCapPfet_L_2_090_W_1_255 OR deCapPfet_L_3_050_W_1_255)) |
| goodDecapPhighvts = phighvt_L_0_18_W_valid OR (deCapPfet_L_4_730_W_0_870 OR (deCapPfet_L_2_890_W_0_870 OR (deCapPfet_L_1_970_W_0_870 OR (deCapPfet_L_0_590_W_0_870 OR deCapPfet_L_1_050_W_0_870)))) |
| exemptDecaps = goodDecapNfets OR |
| (goodDecapPfets OR goodDecapPhighvts) |
| GATEnoPrune = GATE NOT prune |
| s8rf_pmedlvt_W0p84_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_pmedlvt_W0p84_L0p15_2F") |
| "k_2_s8rf_pmedlvt_W0p84_L0p15_2F" { |
| @ keep: s8rf_pmedlvt_W0p84_L0p15_2F - s8rf_pmedlvt_W0p84_L0p15_2F |
| COPY s8rf_pmedlvt_W0p84_L0p15_2F |
| } |
| s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15 = LENGTH (s8rf_pmedlvt_W0p84_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_3_s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15" { |
| @ keep: s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15 - s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15 |
| COPY s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15 |
| } |
| s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15_W_0_84_tmp = INTERNAL s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15_W_0_84 = (WITH TEXT s8rf_pmedlvt_W0p84_L0p15_2F "dummy_poly" textlabel) OR s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15_W_0_84_tmp |
| s8rf_pmedlvt_W0p84_L0p15_2F_valid = COPY s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15_W_0_84 |
| "k_4_s8rf_pmedlvt_W0p84_L0p15_2F_valid" { |
| @ keep: s8rf_pmedlvt_W0p84_L0p15_2F_valid - s8rf_pmedlvt_W0p84_L0p15_2F_valid |
| COPY s8rf_pmedlvt_W0p84_L0p15_2F_valid |
| } |
| s8rf_pmedlvt_W0p84_L0p15_2F_invalid = s8rf_pmedlvt_W0p84_L0p15_2F NOT (exemptDecaps OR s8rf_pmedlvt_W0p84_L0p15_2F_valid) |
| "r_546_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pmedlvt_W0p84_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pmedlvt_W0p84_L0p15_2F_invalid |
| } |
| s8rf_pshort_W3p0_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W3p0_L0p25_M4_b") |
| "k_5_s8rf_pshort_W3p0_L0p25_M4_b" { |
| @ keep: s8rf_pshort_W3p0_L0p25_M4_b - s8rf_pshort_W3p0_L0p25_M4_b |
| COPY s8rf_pshort_W3p0_L0p25_M4_b |
| } |
| s8rf_pshort_W3p0_L0p25_M4_b_L_0_25 = LENGTH (s8rf_pshort_W3p0_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_6_s8rf_pshort_W3p0_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_pshort_W3p0_L0p25_M4_b_L_0_25 - s8rf_pshort_W3p0_L0p25_M4_b_L_0_25 |
| COPY s8rf_pshort_W3p0_L0p25_M4_b_L_0_25 |
| } |
| s8rf_pshort_W3p0_L0p25_M4_b_L_0_25_W_3_01_tmp = INTERNAL s8rf_pshort_W3p0_L0p25_M4_b_L_0_25 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W3p0_L0p25_M4_b_L_0_25_W_3_01 = (WITH TEXT s8rf_pshort_W3p0_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W3p0_L0p25_M4_b_L_0_25_W_3_01_tmp |
| s8rf_pshort_W3p0_L0p25_M4_b_valid = COPY s8rf_pshort_W3p0_L0p25_M4_b_L_0_25_W_3_01 |
| "k_7_s8rf_pshort_W3p0_L0p25_M4_b_valid" { |
| @ keep: s8rf_pshort_W3p0_L0p25_M4_b_valid - s8rf_pshort_W3p0_L0p25_M4_b_valid |
| COPY s8rf_pshort_W3p0_L0p25_M4_b_valid |
| } |
| s8rf_pshort_W3p0_L0p25_M4_b_invalid = s8rf_pshort_W3p0_L0p25_M4_b NOT (exemptDecaps OR s8rf_pshort_W3p0_L0p25_M4_b_valid) |
| "r_547_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W3p0_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W3p0_L0p25_M4_b_invalid |
| } |
| s8rf_pshort_W5p0_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_pshort_W5p0_L0p15_2F") |
| "k_8_s8rf_pshort_W5p0_L0p15_2F" { |
| @ keep: s8rf_pshort_W5p0_L0p15_2F - s8rf_pshort_W5p0_L0p15_2F |
| COPY s8rf_pshort_W5p0_L0p15_2F |
| } |
| s8rf_pshort_W5p0_L0p15_2F_L_0_15 = LENGTH (s8rf_pshort_W5p0_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_9_s8rf_pshort_W5p0_L0p15_2F_L_0_15" { |
| @ keep: s8rf_pshort_W5p0_L0p15_2F_L_0_15 - s8rf_pshort_W5p0_L0p15_2F_L_0_15 |
| COPY s8rf_pshort_W5p0_L0p15_2F_L_0_15 |
| } |
| s8rf_pshort_W5p0_L0p15_2F_L_0_15_W_5_00_tmp = INTERNAL s8rf_pshort_W5p0_L0p15_2F_L_0_15 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W5p0_L0p15_2F_L_0_15_W_5_00 = (WITH TEXT s8rf_pshort_W5p0_L0p15_2F "dummy_poly" textlabel) OR s8rf_pshort_W5p0_L0p15_2F_L_0_15_W_5_00_tmp |
| s8rf_pshort_W5p0_L0p15_2F_valid = COPY s8rf_pshort_W5p0_L0p15_2F_L_0_15_W_5_00 |
| "k_10_s8rf_pshort_W5p0_L0p15_2F_valid" { |
| @ keep: s8rf_pshort_W5p0_L0p15_2F_valid - s8rf_pshort_W5p0_L0p15_2F_valid |
| COPY s8rf_pshort_W5p0_L0p15_2F_valid |
| } |
| s8rf_pshort_W5p0_L0p15_2F_invalid = s8rf_pshort_W5p0_L0p15_2F NOT (exemptDecaps OR s8rf_pshort_W5p0_L0p15_2F_valid) |
| "r_548_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W5p0_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W5p0_L0p15_2F_invalid |
| } |
| s8rf_pshort_W1p65_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W1p65_L0p25_M4_b") |
| "k_11_s8rf_pshort_W1p65_L0p25_M4_b" { |
| @ keep: s8rf_pshort_W1p65_L0p25_M4_b - s8rf_pshort_W1p65_L0p25_M4_b |
| COPY s8rf_pshort_W1p65_L0p25_M4_b |
| } |
| s8rf_pshort_W1p65_L0p25_M4_b_L_0_25 = LENGTH (s8rf_pshort_W1p65_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_12_s8rf_pshort_W1p65_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_pshort_W1p65_L0p25_M4_b_L_0_25 - s8rf_pshort_W1p65_L0p25_M4_b_L_0_25 |
| COPY s8rf_pshort_W1p65_L0p25_M4_b_L_0_25 |
| } |
| s8rf_pshort_W1p65_L0p25_M4_b_L_0_25_W_1_65_tmp = INTERNAL s8rf_pshort_W1p65_L0p25_M4_b_L_0_25 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p65_L0p25_M4_b_L_0_25_W_1_65 = (WITH TEXT s8rf_pshort_W1p65_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W1p65_L0p25_M4_b_L_0_25_W_1_65_tmp |
| s8rf_pshort_W1p65_L0p25_M4_b_valid = COPY s8rf_pshort_W1p65_L0p25_M4_b_L_0_25_W_1_65 |
| "k_13_s8rf_pshort_W1p65_L0p25_M4_b_valid" { |
| @ keep: s8rf_pshort_W1p65_L0p25_M4_b_valid - s8rf_pshort_W1p65_L0p25_M4_b_valid |
| COPY s8rf_pshort_W1p65_L0p25_M4_b_valid |
| } |
| s8rf_pshort_W1p65_L0p25_M4_b_invalid = s8rf_pshort_W1p65_L0p25_M4_b NOT (exemptDecaps OR s8rf_pshort_W1p65_L0p25_M4_b_valid) |
| "r_549_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p65_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p65_L0p25_M4_b_invalid |
| } |
| phvesd_L_0_55 = LENGTH ("phvesd" COINCIDENT INSIDE EDGE diff) == 0.55 |
| "k_14_phvesd_L_0_55" { |
| @ keep: phvesd_L_0_55 - phvesd_L_0_55 |
| COPY phvesd_L_0_55 |
| } |
| phvesd_L_0_55_W_14_50_tmp = INTERNAL phvesd_L_0_55 == 14.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_14_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_14_50_tmp |
| phvesd_L_0_55_W_15_50_tmp = INTERNAL phvesd_L_0_55 == 15.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_15_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_15_50_tmp |
| phvesd_L_0_55_W_16_50_tmp = INTERNAL phvesd_L_0_55 == 16.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_16_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_16_50_tmp |
| phvesd_L_0_55_W_17_50_tmp = INTERNAL phvesd_L_0_55 == 17.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_17_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_17_50_tmp |
| phvesd_L_0_55_W_19_50_tmp = INTERNAL phvesd_L_0_55 == 19.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_19_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_19_50_tmp |
| phvesd_L_0_55_W_21_50_tmp = INTERNAL phvesd_L_0_55 == 21.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_21_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_21_50_tmp |
| phvesd_L_0_55_W_23_50_tmp = INTERNAL phvesd_L_0_55 == 23.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_23_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_23_50_tmp |
| phvesd_L_0_55_W_26_50_tmp = INTERNAL phvesd_L_0_55 == 26.5 OPPOSITE PARALLEL ONLY REGION |
| phvesd_L_0_55_W_26_50 = (WITH TEXT "phvesd" "dummy_poly" textlabel) OR phvesd_L_0_55_W_26_50_tmp |
| phvesd_valid = phvesd_L_0_55_W_26_50 OR |
| (phvesd_L_0_55_W_23_50 OR |
| (phvesd_L_0_55_W_21_50 OR |
| (phvesd_L_0_55_W_19_50 OR |
| (phvesd_L_0_55_W_17_50 OR |
| (phvesd_L_0_55_W_16_50 OR |
| (phvesd_L_0_55_W_15_50 OR phvesd_L_0_55_W_14_50)))))) |
| "k_15_phvesd_valid" { |
| @ keep: phvesd_valid - phvesd_valid |
| COPY phvesd_valid |
| } |
| phvesd_invalid = phvesd NOT (exemptDecaps OR phvesd_valid) |
| "r_550_Poly.X.1" { |
| @ Poly.X.1: This phvesd device has an invalid W/L. Please see MRGA |
| COPY phvesd_invalid |
| } |
| s8rf_pshort_W3p0_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W3p0_L0p15_M4_b") |
| "k_16_s8rf_pshort_W3p0_L0p15_M4_b" { |
| @ keep: s8rf_pshort_W3p0_L0p15_M4_b - s8rf_pshort_W3p0_L0p15_M4_b |
| COPY s8rf_pshort_W3p0_L0p15_M4_b |
| } |
| s8rf_pshort_W3p0_L0p15_M4_b_L_0_15 = LENGTH (s8rf_pshort_W3p0_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_17_s8rf_pshort_W3p0_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_pshort_W3p0_L0p15_M4_b_L_0_15 - s8rf_pshort_W3p0_L0p15_M4_b_L_0_15 |
| COPY s8rf_pshort_W3p0_L0p15_M4_b_L_0_15 |
| } |
| s8rf_pshort_W3p0_L0p15_M4_b_L_0_15_W_3_01_tmp = INTERNAL s8rf_pshort_W3p0_L0p15_M4_b_L_0_15 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W3p0_L0p15_M4_b_L_0_15_W_3_01 = (WITH TEXT s8rf_pshort_W3p0_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W3p0_L0p15_M4_b_L_0_15_W_3_01_tmp |
| s8rf_pshort_W3p0_L0p15_M4_b_valid = COPY s8rf_pshort_W3p0_L0p15_M4_b_L_0_15_W_3_01 |
| "k_18_s8rf_pshort_W3p0_L0p15_M4_b_valid" { |
| @ keep: s8rf_pshort_W3p0_L0p15_M4_b_valid - s8rf_pshort_W3p0_L0p15_M4_b_valid |
| COPY s8rf_pshort_W3p0_L0p15_M4_b_valid |
| } |
| s8rf_pshort_W3p0_L0p15_M4_b_invalid = s8rf_pshort_W3p0_L0p15_M4_b NOT (exemptDecaps OR s8rf_pshort_W3p0_L0p15_M4_b_valid) |
| "r_551_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W3p0_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W3p0_L0p15_M4_b_invalid |
| } |
| s8rf_pshort_W5p0_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W5p0_L0p25_M4_b") |
| "k_19_s8rf_pshort_W5p0_L0p25_M4_b" { |
| @ keep: s8rf_pshort_W5p0_L0p25_M4_b - s8rf_pshort_W5p0_L0p25_M4_b |
| COPY s8rf_pshort_W5p0_L0p25_M4_b |
| } |
| s8rf_pshort_W5p0_L0p25_M4_b_L_0_25 = LENGTH (s8rf_pshort_W5p0_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_20_s8rf_pshort_W5p0_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_pshort_W5p0_L0p25_M4_b_L_0_25 - s8rf_pshort_W5p0_L0p25_M4_b_L_0_25 |
| COPY s8rf_pshort_W5p0_L0p25_M4_b_L_0_25 |
| } |
| s8rf_pshort_W5p0_L0p25_M4_b_L_0_25_W_5_05_tmp = INTERNAL s8rf_pshort_W5p0_L0p25_M4_b_L_0_25 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W5p0_L0p25_M4_b_L_0_25_W_5_05 = (WITH TEXT s8rf_pshort_W5p0_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W5p0_L0p25_M4_b_L_0_25_W_5_05_tmp |
| s8rf_pshort_W5p0_L0p25_M4_b_valid = COPY s8rf_pshort_W5p0_L0p25_M4_b_L_0_25_W_5_05 |
| "k_21_s8rf_pshort_W5p0_L0p25_M4_b_valid" { |
| @ keep: s8rf_pshort_W5p0_L0p25_M4_b_valid - s8rf_pshort_W5p0_L0p25_M4_b_valid |
| COPY s8rf_pshort_W5p0_L0p25_M4_b_valid |
| } |
| s8rf_pshort_W5p0_L0p25_M4_b_invalid = s8rf_pshort_W5p0_L0p25_M4_b NOT (exemptDecaps OR s8rf_pshort_W5p0_L0p25_M4_b_valid) |
| "r_552_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W5p0_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W5p0_L0p25_M4_b_invalid |
| } |
| s8rf_pshort_W5p0_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W5p0_L0p25_M2_b") |
| "k_22_s8rf_pshort_W5p0_L0p25_M2_b" { |
| @ keep: s8rf_pshort_W5p0_L0p25_M2_b - s8rf_pshort_W5p0_L0p25_M2_b |
| COPY s8rf_pshort_W5p0_L0p25_M2_b |
| } |
| s8rf_pshort_W5p0_L0p25_M2_b_L_0_25 = LENGTH (s8rf_pshort_W5p0_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_23_s8rf_pshort_W5p0_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_pshort_W5p0_L0p25_M2_b_L_0_25 - s8rf_pshort_W5p0_L0p25_M2_b_L_0_25 |
| COPY s8rf_pshort_W5p0_L0p25_M2_b_L_0_25 |
| } |
| s8rf_pshort_W5p0_L0p25_M2_b_L_0_25_W_5_05_tmp = INTERNAL s8rf_pshort_W5p0_L0p25_M2_b_L_0_25 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W5p0_L0p25_M2_b_L_0_25_W_5_05 = (WITH TEXT s8rf_pshort_W5p0_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W5p0_L0p25_M2_b_L_0_25_W_5_05_tmp |
| s8rf_pshort_W5p0_L0p25_M2_b_valid = COPY s8rf_pshort_W5p0_L0p25_M2_b_L_0_25_W_5_05 |
| "k_24_s8rf_pshort_W5p0_L0p25_M2_b_valid" { |
| @ keep: s8rf_pshort_W5p0_L0p25_M2_b_valid - s8rf_pshort_W5p0_L0p25_M2_b_valid |
| COPY s8rf_pshort_W5p0_L0p25_M2_b_valid |
| } |
| s8rf_pshort_W5p0_L0p25_M2_b_invalid = s8rf_pshort_W5p0_L0p25_M2_b NOT (exemptDecaps OR s8rf_pshort_W5p0_L0p25_M2_b_valid) |
| "r_553_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W5p0_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W5p0_L0p25_M2_b_invalid |
| } |
| plowvt_L_0_35 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 0.35 |
| "k_25_plowvt_L_0_35" { |
| @ keep: plowvt_L_0_35 - plowvt_L_0_35 |
| COPY plowvt_L_0_35 |
| } |
| plowvt_L_0_35_W_0_42_tmp = INTERNAL plowvt_L_0_35 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_35_W_0_42 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_35_W_0_42_tmp |
| plowvt_L_0_35_W_0_55_tmp = INTERNAL plowvt_L_0_35 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_35_W_0_55 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_35_W_0_55_tmp |
| plowvt_L_0_35_W_1_00_tmp = INTERNAL plowvt_L_0_35 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_35_W_1_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_35_W_1_00_tmp |
| plowvt_L_0_35_W_3_00_tmp = INTERNAL plowvt_L_0_35 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_35_W_3_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_35_W_3_00_tmp |
| plowvt_L_0_35_W_5_00_tmp = INTERNAL plowvt_L_0_35 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_35_W_5_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_35_W_5_00_tmp |
| plowvt_L_0_35_W_7_00_tmp = INTERNAL plowvt_L_0_35 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_35_W_7_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_35_W_7_00_tmp |
| plowvt_L_0_50 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_26_plowvt_L_0_50" { |
| @ keep: plowvt_L_0_50 - plowvt_L_0_50 |
| COPY plowvt_L_0_50 |
| } |
| plowvt_L_0_50_W_0_42_tmp = INTERNAL plowvt_L_0_50 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_50_W_0_42 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_50_W_0_42_tmp |
| plowvt_L_0_50_W_0_55_tmp = INTERNAL plowvt_L_0_50 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_50_W_0_55 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_50_W_0_55_tmp |
| plowvt_L_0_50_W_1_00_tmp = INTERNAL plowvt_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_50_W_1_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_50_W_1_00_tmp |
| plowvt_L_0_50_W_3_00_tmp = INTERNAL plowvt_L_0_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_50_W_3_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_50_W_3_00_tmp |
| plowvt_L_0_50_W_5_00_tmp = INTERNAL plowvt_L_0_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_50_W_5_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_50_W_5_00_tmp |
| plowvt_L_0_50_W_7_00_tmp = INTERNAL plowvt_L_0_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_0_50_W_7_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_0_50_W_7_00_tmp |
| plowvt_L_1_00 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_27_plowvt_L_1_00" { |
| @ keep: plowvt_L_1_00 - plowvt_L_1_00 |
| COPY plowvt_L_1_00 |
| } |
| plowvt_L_1_00_W_0_42_tmp = INTERNAL plowvt_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_00_W_0_42 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_00_W_0_42_tmp |
| plowvt_L_1_00_W_0_55_tmp = INTERNAL plowvt_L_1_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_00_W_0_55 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_00_W_0_55_tmp |
| plowvt_L_1_00_W_1_00_tmp = INTERNAL plowvt_L_1_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_00_W_1_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_00_W_1_00_tmp |
| plowvt_L_1_00_W_3_00_tmp = INTERNAL plowvt_L_1_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_00_W_3_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_00_W_3_00_tmp |
| plowvt_L_1_00_W_5_00_tmp = INTERNAL plowvt_L_1_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_00_W_5_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_00_W_5_00_tmp |
| plowvt_L_1_00_W_7_00_tmp = INTERNAL plowvt_L_1_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_00_W_7_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_00_W_7_00_tmp |
| plowvt_L_1_50 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 1.5 |
| "k_28_plowvt_L_1_50" { |
| @ keep: plowvt_L_1_50 - plowvt_L_1_50 |
| COPY plowvt_L_1_50 |
| } |
| plowvt_L_1_50_W_3_00_tmp = INTERNAL plowvt_L_1_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_50_W_3_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_50_W_3_00_tmp |
| plowvt_L_1_50_W_5_00_tmp = INTERNAL plowvt_L_1_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_50_W_5_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_50_W_5_00_tmp |
| plowvt_L_1_50_W_7_00_tmp = INTERNAL plowvt_L_1_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_1_50_W_7_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_1_50_W_7_00_tmp |
| plowvt_L_2_00 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_29_plowvt_L_2_00" { |
| @ keep: plowvt_L_2_00 - plowvt_L_2_00 |
| COPY plowvt_L_2_00 |
| } |
| plowvt_L_2_00_W_0_42_tmp = INTERNAL plowvt_L_2_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_0_42 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_0_42_tmp |
| plowvt_L_2_00_W_0_55_tmp = INTERNAL plowvt_L_2_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_0_55 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_0_55_tmp |
| plowvt_L_2_00_W_1_00_tmp = INTERNAL plowvt_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_1_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_1_00_tmp |
| plowvt_L_2_00_W_2_40_tmp = INTERNAL plowvt_L_2_00 == 2.4 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_2_40 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_2_40_tmp |
| plowvt_L_2_00_W_3_00_tmp = INTERNAL plowvt_L_2_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_3_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_3_00_tmp |
| plowvt_L_2_00_W_3_375_tmp = INTERNAL plowvt_L_2_00 == 3.375 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_3_375 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_3_375_tmp |
| plowvt_L_2_00_W_3_990_tmp = INTERNAL plowvt_L_2_00 == 3.99 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_3_990 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_3_990_tmp |
| plowvt_L_2_00_W_4_255_tmp = INTERNAL plowvt_L_2_00 == 4.255 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_4_255 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_4_255_tmp |
| plowvt_L_2_00_W_5_00_tmp = INTERNAL plowvt_L_2_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_5_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_5_00_tmp |
| plowvt_L_2_00_W_7_00_tmp = INTERNAL plowvt_L_2_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_2_00_W_7_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_2_00_W_7_00_tmp |
| plowvt_L_4_00 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_30_plowvt_L_4_00" { |
| @ keep: plowvt_L_4_00 - plowvt_L_4_00 |
| COPY plowvt_L_4_00 |
| } |
| plowvt_L_4_00_W_0_42_tmp = INTERNAL plowvt_L_4_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_0_42 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_0_42_tmp |
| plowvt_L_4_00_W_0_55_tmp = INTERNAL plowvt_L_4_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_0_55 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_0_55_tmp |
| plowvt_L_4_00_W_1_00_tmp = INTERNAL plowvt_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_1_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_1_00_tmp |
| plowvt_L_4_00_W_1_770_tmp = INTERNAL plowvt_L_4_00 == 1.77 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_1_770 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_1_770_tmp |
| plowvt_L_4_00_W_1_805_tmp = INTERNAL plowvt_L_4_00 == 1.805 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_1_805 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_1_805_tmp |
| plowvt_L_4_00_W_1_995_tmp = INTERNAL plowvt_L_4_00 == 1.995 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_1_995 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_1_995_tmp |
| plowvt_L_4_00_W_2_005_tmp = INTERNAL plowvt_L_4_00 == 2.005 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_005 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_005_tmp |
| plowvt_L_4_00_W_2_140_tmp = INTERNAL plowvt_L_4_00 == 2.14 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_140 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_140_tmp |
| plowvt_L_4_00_W_2_190_tmp = INTERNAL plowvt_L_4_00 == 2.19 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_190 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_190_tmp |
| plowvt_L_4_00_W_2_295_tmp = INTERNAL plowvt_L_4_00 == 2.295 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_295 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_295_tmp |
| plowvt_L_4_00_W_2_340_tmp = INTERNAL plowvt_L_4_00 == 2.34 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_340 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_340_tmp |
| plowvt_L_4_00_W_2_500_tmp = INTERNAL plowvt_L_4_00 == 2.5 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_500 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_500_tmp |
| plowvt_L_4_00_W_2_755_tmp = INTERNAL plowvt_L_4_00 == 2.755 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_755 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_755_tmp |
| plowvt_L_4_00_W_2_770_tmp = INTERNAL plowvt_L_4_00 == 2.77 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_770 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_770_tmp |
| plowvt_L_4_00_W_2_875_tmp = INTERNAL plowvt_L_4_00 == 2.875 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_875 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_875_tmp |
| plowvt_L_4_00_W_2_910_tmp = INTERNAL plowvt_L_4_00 == 2.91 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_2_910 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_2_910_tmp |
| plowvt_L_4_00_W_3_00_tmp = INTERNAL plowvt_L_4_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_3_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_3_00_tmp |
| plowvt_L_4_00_W_5_00_tmp = INTERNAL plowvt_L_4_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_5_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_5_00_tmp |
| plowvt_L_4_00_W_7_00_tmp = INTERNAL plowvt_L_4_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_4_00_W_7_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_4_00_W_7_00_tmp |
| plowvt_L_8_00 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_31_plowvt_L_8_00" { |
| @ keep: plowvt_L_8_00 - plowvt_L_8_00 |
| COPY plowvt_L_8_00 |
| } |
| plowvt_L_8_00_W_0_42_tmp = INTERNAL plowvt_L_8_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_8_00_W_0_42 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_8_00_W_0_42_tmp |
| plowvt_L_8_00_W_0_55_tmp = INTERNAL plowvt_L_8_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_8_00_W_0_55 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_8_00_W_0_55_tmp |
| plowvt_L_8_00_W_1_00_tmp = INTERNAL plowvt_L_8_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_8_00_W_1_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_8_00_W_1_00_tmp |
| plowvt_L_8_00_W_3_00_tmp = INTERNAL plowvt_L_8_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_8_00_W_3_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_8_00_W_3_00_tmp |
| plowvt_L_8_00_W_5_00_tmp = INTERNAL plowvt_L_8_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_8_00_W_5_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_8_00_W_5_00_tmp |
| plowvt_L_8_00_W_7_00_tmp = INTERNAL plowvt_L_8_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_8_00_W_7_00 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_8_00_W_7_00_tmp |
| plowvt_L_20_0 = LENGTH ("plowvt" COINCIDENT INSIDE EDGE diff) == 20.0 |
| "k_32_plowvt_L_20_0" { |
| @ keep: plowvt_L_20_0 - plowvt_L_20_0 |
| COPY plowvt_L_20_0 |
| } |
| plowvt_L_20_0_W_0_42_tmp = INTERNAL plowvt_L_20_0 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| plowvt_L_20_0_W_0_42 = (WITH TEXT "plowvt" "dummy_poly" textlabel) OR plowvt_L_20_0_W_0_42_tmp |
| plowvt_valid = plowvt_L_20_0_W_0_42 OR |
| (plowvt_L_8_00_W_7_00 OR |
| (plowvt_L_8_00_W_5_00 OR |
| (plowvt_L_8_00_W_3_00 OR |
| (plowvt_L_8_00_W_1_00 OR |
| (plowvt_L_8_00_W_0_55 OR |
| (plowvt_L_8_00_W_0_42 OR |
| (plowvt_L_4_00_W_7_00 OR |
| (plowvt_L_4_00_W_5_00 OR |
| (plowvt_L_4_00_W_3_00 OR |
| (plowvt_L_4_00_W_2_910 OR |
| (plowvt_L_4_00_W_2_875 OR |
| (plowvt_L_4_00_W_2_770 OR |
| (plowvt_L_4_00_W_2_755 OR |
| (plowvt_L_4_00_W_2_500 OR |
| (plowvt_L_4_00_W_2_340 OR |
| (plowvt_L_4_00_W_2_295 OR |
| (plowvt_L_4_00_W_2_190 OR |
| (plowvt_L_4_00_W_2_140 OR |
| (plowvt_L_4_00_W_2_005 OR |
| (plowvt_L_4_00_W_1_995 OR |
| (plowvt_L_4_00_W_1_805 OR |
| (plowvt_L_4_00_W_1_770 OR |
| (plowvt_L_4_00_W_1_00 OR |
| (plowvt_L_4_00_W_0_55 OR |
| (plowvt_L_4_00_W_0_42 OR |
| (plowvt_L_2_00_W_7_00 OR |
| (plowvt_L_2_00_W_5_00 OR |
| (plowvt_L_2_00_W_4_255 OR |
| (plowvt_L_2_00_W_3_990 OR |
| (plowvt_L_2_00_W_3_375 OR |
| (plowvt_L_2_00_W_3_00 OR |
| (plowvt_L_2_00_W_2_40 OR |
| (plowvt_L_2_00_W_1_00 OR |
| (plowvt_L_2_00_W_0_55 OR |
| (plowvt_L_2_00_W_0_42 OR |
| (plowvt_L_1_50_W_7_00 OR |
| (plowvt_L_1_50_W_5_00 OR |
| (plowvt_L_1_50_W_3_00 OR |
| (plowvt_L_1_00_W_7_00 OR |
| (plowvt_L_1_00_W_5_00 OR |
| (plowvt_L_1_00_W_3_00 OR |
| (plowvt_L_1_00_W_1_00 OR |
| (plowvt_L_1_00_W_0_55 OR |
| (plowvt_L_1_00_W_0_42 OR |
| (plowvt_L_0_50_W_7_00 OR |
| (plowvt_L_0_50_W_5_00 OR |
| (plowvt_L_0_50_W_3_00 OR |
| (plowvt_L_0_50_W_1_00 OR |
| (plowvt_L_0_50_W_0_55 OR |
| (plowvt_L_0_50_W_0_42 OR |
| (plowvt_L_0_35_W_7_00 OR |
| (plowvt_L_0_35_W_5_00 OR |
| (plowvt_L_0_35_W_3_00 OR |
| (plowvt_L_0_35_W_1_00 OR |
| (plowvt_L_0_35_W_0_55 OR plowvt_L_0_35_W_0_42))))))))))))))))))))))))))))))))))))))))))))))))))))))) |
| "k_33_plowvt_valid" { |
| @ keep: plowvt_valid - plowvt_valid |
| COPY plowvt_valid |
| } |
| plowvt_invalid = plowvt NOT (exemptDecaps OR plowvt_valid) |
| "r_554_Poly.X.1" { |
| @ Poly.X.1: This plowvt device has an invalid W/L. Please see MRGA |
| COPY plowvt_invalid |
| } |
| s8rf_pshort_W0p84_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_pshort_W0p84_L0p15_2F") |
| "k_34_s8rf_pshort_W0p84_L0p15_2F" { |
| @ keep: s8rf_pshort_W0p84_L0p15_2F - s8rf_pshort_W0p84_L0p15_2F |
| COPY s8rf_pshort_W0p84_L0p15_2F |
| } |
| s8rf_pshort_W0p84_L0p15_2F_L_0_15 = LENGTH (s8rf_pshort_W0p84_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_35_s8rf_pshort_W0p84_L0p15_2F_L_0_15" { |
| @ keep: s8rf_pshort_W0p84_L0p15_2F_L_0_15 - s8rf_pshort_W0p84_L0p15_2F_L_0_15 |
| COPY s8rf_pshort_W0p84_L0p15_2F_L_0_15 |
| } |
| s8rf_pshort_W0p84_L0p15_2F_L_0_15_W_0_84_tmp = INTERNAL s8rf_pshort_W0p84_L0p15_2F_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W0p84_L0p15_2F_L_0_15_W_0_84 = (WITH TEXT s8rf_pshort_W0p84_L0p15_2F "dummy_poly" textlabel) OR s8rf_pshort_W0p84_L0p15_2F_L_0_15_W_0_84_tmp |
| s8rf_pshort_W0p84_L0p15_2F_valid = COPY s8rf_pshort_W0p84_L0p15_2F_L_0_15_W_0_84 |
| "k_36_s8rf_pshort_W0p84_L0p15_2F_valid" { |
| @ keep: s8rf_pshort_W0p84_L0p15_2F_valid - s8rf_pshort_W0p84_L0p15_2F_valid |
| COPY s8rf_pshort_W0p84_L0p15_2F_valid |
| } |
| s8rf_pshort_W0p84_L0p15_2F_invalid = s8rf_pshort_W0p84_L0p15_2F NOT (exemptDecaps OR s8rf_pshort_W0p84_L0p15_2F_valid) |
| "r_555_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W0p84_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W0p84_L0p15_2F_invalid |
| } |
| s8rf_pshort_W1p65_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W1p65_L0p25_M2_b") |
| "k_37_s8rf_pshort_W1p65_L0p25_M2_b" { |
| @ keep: s8rf_pshort_W1p65_L0p25_M2_b - s8rf_pshort_W1p65_L0p25_M2_b |
| COPY s8rf_pshort_W1p65_L0p25_M2_b |
| } |
| s8rf_pshort_W1p65_L0p25_M2_b_L_0_25 = LENGTH (s8rf_pshort_W1p65_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_38_s8rf_pshort_W1p65_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_pshort_W1p65_L0p25_M2_b_L_0_25 - s8rf_pshort_W1p65_L0p25_M2_b_L_0_25 |
| COPY s8rf_pshort_W1p65_L0p25_M2_b_L_0_25 |
| } |
| s8rf_pshort_W1p65_L0p25_M2_b_L_0_25_W_1_65_tmp = INTERNAL s8rf_pshort_W1p65_L0p25_M2_b_L_0_25 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p65_L0p25_M2_b_L_0_25_W_1_65 = (WITH TEXT s8rf_pshort_W1p65_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W1p65_L0p25_M2_b_L_0_25_W_1_65_tmp |
| s8rf_pshort_W1p65_L0p25_M2_b_valid = COPY s8rf_pshort_W1p65_L0p25_M2_b_L_0_25_W_1_65 |
| "k_39_s8rf_pshort_W1p65_L0p25_M2_b_valid" { |
| @ keep: s8rf_pshort_W1p65_L0p25_M2_b_valid - s8rf_pshort_W1p65_L0p25_M2_b_valid |
| COPY s8rf_pshort_W1p65_L0p25_M2_b_valid |
| } |
| s8rf_pshort_W1p65_L0p25_M2_b_invalid = s8rf_pshort_W1p65_L0p25_M2_b NOT (exemptDecaps OR s8rf_pshort_W1p65_L0p25_M2_b_valid) |
| "r_556_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p65_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p65_L0p25_M2_b_invalid |
| } |
| phv_L_0_50 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_40_phv_L_0_50" { |
| @ keep: phv_L_0_50 - phv_L_0_50 |
| COPY phv_L_0_50 |
| } |
| phv_L_0_50_W_0_42_tmp = INTERNAL phv_L_0_50 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_0_42_tmp |
| phv_L_0_50_W_0_75_tmp = INTERNAL phv_L_0_50 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_0_75 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_0_75_tmp |
| phv_L_0_50_W_1_00_tmp = INTERNAL phv_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_1_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_1_00_tmp |
| phv_L_0_50_W_1_50_tmp = INTERNAL phv_L_0_50 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_1_50 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_1_50_tmp |
| phv_L_0_50_W_3_00_tmp = INTERNAL phv_L_0_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_3_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_3_00_tmp |
| phv_L_0_50_W_5_00_tmp = INTERNAL phv_L_0_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_5_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_5_00_tmp |
| phv_L_0_50_W_7_00_tmp = INTERNAL phv_L_0_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_7_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_7_00_tmp |
| phv_L_0_50_W_10_0_tmp = INTERNAL phv_L_0_50 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_10_0 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_10_0_tmp |
| phv_L_0_50_W_15_0_tmp = INTERNAL phv_L_0_50 == 15.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_15_0 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_15_0_tmp |
| phv_L_0_50_W_20_0_tmp = INTERNAL phv_L_0_50 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_50_W_20_0 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_50_W_20_0_tmp |
| phv_L_0_60 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 0.6 |
| "k_41_phv_L_0_60" { |
| @ keep: phv_L_0_60 - phv_L_0_60 |
| COPY phv_L_0_60 |
| } |
| phv_L_0_60_W_0_42_tmp = INTERNAL phv_L_0_60 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_60_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_60_W_0_42_tmp |
| phv_L_0_60_W_0_70_tmp = INTERNAL phv_L_0_60 == 0.7 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_60_W_0_70 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_60_W_0_70_tmp |
| phv_L_0_60_W_1_00_tmp = INTERNAL phv_L_0_60 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_60_W_1_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_60_W_1_00_tmp |
| phv_L_0_60_W_3_00_tmp = INTERNAL phv_L_0_60 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_60_W_3_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_60_W_3_00_tmp |
| phv_L_0_60_W_5_00_tmp = INTERNAL phv_L_0_60 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_60_W_5_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_60_W_5_00_tmp |
| phv_L_0_80 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 0.8 |
| "k_42_phv_L_0_80" { |
| @ keep: phv_L_0_80 - phv_L_0_80 |
| COPY phv_L_0_80 |
| } |
| phv_L_0_80_W_0_42_tmp = INTERNAL phv_L_0_80 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_80_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_80_W_0_42_tmp |
| phv_L_0_80_W_0_75_tmp = INTERNAL phv_L_0_80 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_80_W_0_75 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_80_W_0_75_tmp |
| phv_L_0_80_W_1_00_tmp = INTERNAL phv_L_0_80 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_80_W_1_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_80_W_1_00_tmp |
| phv_L_0_80_W_5_00_tmp = INTERNAL phv_L_0_80 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_80_W_5_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_80_W_5_00_tmp |
| phv_L_0_80_W_7_00_tmp = INTERNAL phv_L_0_80 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_0_80_W_7_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_0_80_W_7_00_tmp |
| phv_L_1_00 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_43_phv_L_1_00" { |
| @ keep: phv_L_1_00 - phv_L_1_00 |
| COPY phv_L_1_00 |
| } |
| phv_L_1_00_W_0_42_tmp = INTERNAL phv_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_0_42_tmp |
| phv_L_1_00_W_0_75_tmp = INTERNAL phv_L_1_00 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_0_75 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_0_75_tmp |
| phv_L_1_00_W_1_00_tmp = INTERNAL phv_L_1_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_1_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_1_00_tmp |
| phv_L_1_00_W_1_50_tmp = INTERNAL phv_L_1_00 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_1_50 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_1_50_tmp |
| phv_L_1_00_W_3_00_tmp = INTERNAL phv_L_1_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_3_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_3_00_tmp |
| phv_L_1_00_W_5_00_tmp = INTERNAL phv_L_1_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_5_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_5_00_tmp |
| phv_L_1_00_W_7_00_tmp = INTERNAL phv_L_1_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_7_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_7_00_tmp |
| phv_L_1_00_W_15_0_tmp = INTERNAL phv_L_1_00 == 15.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_15_0 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_15_0_tmp |
| phv_L_1_00_W_20_0_tmp = INTERNAL phv_L_1_00 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_1_00_W_20_0 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_1_00_W_20_0_tmp |
| phv_L_2_00 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_44_phv_L_2_00" { |
| @ keep: phv_L_2_00 - phv_L_2_00 |
| COPY phv_L_2_00 |
| } |
| phv_L_2_00_W_0_42_tmp = INTERNAL phv_L_2_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_2_00_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_2_00_W_0_42_tmp |
| phv_L_2_00_W_0_75_tmp = INTERNAL phv_L_2_00 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| phv_L_2_00_W_0_75 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_2_00_W_0_75_tmp |
| phv_L_2_00_W_1_00_tmp = INTERNAL phv_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_2_00_W_1_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_2_00_W_1_00_tmp |
| phv_L_2_00_W_1_50_tmp = INTERNAL phv_L_2_00 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| phv_L_2_00_W_1_50 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_2_00_W_1_50_tmp |
| phv_L_2_00_W_3_00_tmp = INTERNAL phv_L_2_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_2_00_W_3_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_2_00_W_3_00_tmp |
| phv_L_2_00_W_5_00_tmp = INTERNAL phv_L_2_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_2_00_W_5_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_2_00_W_5_00_tmp |
| phv_L_2_00_W_7_00_tmp = INTERNAL phv_L_2_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_2_00_W_7_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_2_00_W_7_00_tmp |
| phv_L_4_00 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_45_phv_L_4_00" { |
| @ keep: phv_L_4_00 - phv_L_4_00 |
| COPY phv_L_4_00 |
| } |
| phv_L_4_00_W_0_42_tmp = INTERNAL phv_L_4_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_4_00_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_4_00_W_0_42_tmp |
| phv_L_4_00_W_0_75_tmp = INTERNAL phv_L_4_00 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| phv_L_4_00_W_0_75 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_4_00_W_0_75_tmp |
| phv_L_4_00_W_1_00_tmp = INTERNAL phv_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_4_00_W_1_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_4_00_W_1_00_tmp |
| phv_L_4_00_W_1_50_tmp = INTERNAL phv_L_4_00 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| phv_L_4_00_W_1_50 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_4_00_W_1_50_tmp |
| phv_L_4_00_W_3_00_tmp = INTERNAL phv_L_4_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_4_00_W_3_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_4_00_W_3_00_tmp |
| phv_L_4_00_W_5_00_tmp = INTERNAL phv_L_4_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_4_00_W_5_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_4_00_W_5_00_tmp |
| phv_L_4_00_W_7_00_tmp = INTERNAL phv_L_4_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_4_00_W_7_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_4_00_W_7_00_tmp |
| phv_L_8_00 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_46_phv_L_8_00" { |
| @ keep: phv_L_8_00 - phv_L_8_00 |
| COPY phv_L_8_00 |
| } |
| phv_L_8_00_W_0_42_tmp = INTERNAL phv_L_8_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_8_00_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_8_00_W_0_42_tmp |
| phv_L_8_00_W_1_00_tmp = INTERNAL phv_L_8_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_8_00_W_1_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_8_00_W_1_00_tmp |
| phv_L_8_00_W_3_00_tmp = INTERNAL phv_L_8_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_8_00_W_3_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_8_00_W_3_00_tmp |
| phv_L_8_00_W_5_00_tmp = INTERNAL phv_L_8_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_8_00_W_5_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_8_00_W_5_00_tmp |
| phv_L_8_00_W_7_00_tmp = INTERNAL phv_L_8_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phv_L_8_00_W_7_00 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_8_00_W_7_00_tmp |
| phv_L_20_0 = LENGTH ("phv" COINCIDENT INSIDE EDGE diff) == 20.0 |
| "k_47_phv_L_20_0" { |
| @ keep: phv_L_20_0 - phv_L_20_0 |
| COPY phv_L_20_0 |
| } |
| phv_L_20_0_W_0_42_tmp = INTERNAL phv_L_20_0 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phv_L_20_0_W_0_42 = (WITH TEXT "phv" "dummy_poly" textlabel) OR phv_L_20_0_W_0_42_tmp |
| phv_valid = phv_L_20_0_W_0_42 OR |
| (phv_L_8_00_W_7_00 OR |
| (phv_L_8_00_W_5_00 OR |
| (phv_L_8_00_W_3_00 OR |
| (phv_L_8_00_W_1_00 OR |
| (phv_L_8_00_W_0_42 OR |
| (phv_L_4_00_W_7_00 OR |
| (phv_L_4_00_W_5_00 OR |
| (phv_L_4_00_W_3_00 OR |
| (phv_L_4_00_W_1_50 OR |
| (phv_L_4_00_W_1_00 OR |
| (phv_L_4_00_W_0_75 OR |
| (phv_L_4_00_W_0_42 OR |
| (phv_L_2_00_W_7_00 OR |
| (phv_L_2_00_W_5_00 OR |
| (phv_L_2_00_W_3_00 OR |
| (phv_L_2_00_W_1_50 OR |
| (phv_L_2_00_W_1_00 OR |
| (phv_L_2_00_W_0_75 OR |
| (phv_L_2_00_W_0_42 OR |
| (phv_L_1_00_W_20_0 OR |
| (phv_L_1_00_W_15_0 OR |
| (phv_L_1_00_W_7_00 OR |
| (phv_L_1_00_W_5_00 OR |
| (phv_L_1_00_W_3_00 OR |
| (phv_L_1_00_W_1_50 OR |
| (phv_L_1_00_W_1_00 OR |
| (phv_L_1_00_W_0_75 OR |
| (phv_L_1_00_W_0_42 OR |
| (phv_L_0_80_W_7_00 OR |
| (phv_L_0_80_W_5_00 OR |
| (phv_L_0_80_W_1_00 OR |
| (phv_L_0_80_W_0_75 OR |
| (phv_L_0_80_W_0_42 OR |
| (phv_L_0_60_W_5_00 OR |
| (phv_L_0_60_W_3_00 OR |
| (phv_L_0_60_W_1_00 OR |
| (phv_L_0_60_W_0_70 OR |
| (phv_L_0_60_W_0_42 OR |
| (phv_L_0_50_W_20_0 OR |
| (phv_L_0_50_W_15_0 OR |
| (phv_L_0_50_W_10_0 OR |
| (phv_L_0_50_W_7_00 OR |
| (phv_L_0_50_W_5_00 OR |
| (phv_L_0_50_W_3_00 OR |
| (phv_L_0_50_W_1_50 OR |
| (phv_L_0_50_W_1_00 OR |
| (phv_L_0_50_W_0_75 OR phv_L_0_50_W_0_42))))))))))))))))))))))))))))))))))))))))))))))) |
| "k_48_phv_valid" { |
| @ keep: phv_valid - phv_valid |
| COPY phv_valid |
| } |
| phv_invalid = phv NOT (exemptDecaps OR phv_valid) |
| "r_557_Poly.X.1" { |
| @ Poly.X.1: This phv device has an invalid W/L. Please see MRGA |
| COPY phv_invalid |
| } |
| s8rf_pshort_W3p0_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W3p0_L0p15_M2_b") |
| "k_49_s8rf_pshort_W3p0_L0p15_M2_b" { |
| @ keep: s8rf_pshort_W3p0_L0p15_M2_b - s8rf_pshort_W3p0_L0p15_M2_b |
| COPY s8rf_pshort_W3p0_L0p15_M2_b |
| } |
| s8rf_pshort_W3p0_L0p15_M2_b_L_0_15 = LENGTH (s8rf_pshort_W3p0_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_50_s8rf_pshort_W3p0_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_pshort_W3p0_L0p15_M2_b_L_0_15 - s8rf_pshort_W3p0_L0p15_M2_b_L_0_15 |
| COPY s8rf_pshort_W3p0_L0p15_M2_b_L_0_15 |
| } |
| s8rf_pshort_W3p0_L0p15_M2_b_L_0_15_W_3_01_tmp = INTERNAL s8rf_pshort_W3p0_L0p15_M2_b_L_0_15 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W3p0_L0p15_M2_b_L_0_15_W_3_01 = (WITH TEXT s8rf_pshort_W3p0_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W3p0_L0p15_M2_b_L_0_15_W_3_01_tmp |
| s8rf_pshort_W3p0_L0p15_M2_b_valid = COPY s8rf_pshort_W3p0_L0p15_M2_b_L_0_15_W_3_01 |
| "k_51_s8rf_pshort_W3p0_L0p15_M2_b_valid" { |
| @ keep: s8rf_pshort_W3p0_L0p15_M2_b_valid - s8rf_pshort_W3p0_L0p15_M2_b_valid |
| COPY s8rf_pshort_W3p0_L0p15_M2_b_valid |
| } |
| s8rf_pshort_W3p0_L0p15_M2_b_invalid = s8rf_pshort_W3p0_L0p15_M2_b NOT (exemptDecaps OR s8rf_pshort_W3p0_L0p15_M2_b_valid) |
| "r_558_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W3p0_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W3p0_L0p15_M2_b_invalid |
| } |
| s8rf_pshort_W5p0_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W5p0_L0p15_M4_b") |
| "k_52_s8rf_pshort_W5p0_L0p15_M4_b" { |
| @ keep: s8rf_pshort_W5p0_L0p15_M4_b - s8rf_pshort_W5p0_L0p15_M4_b |
| COPY s8rf_pshort_W5p0_L0p15_M4_b |
| } |
| s8rf_pshort_W5p0_L0p15_M4_b_L_0_15 = LENGTH (s8rf_pshort_W5p0_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_53_s8rf_pshort_W5p0_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_pshort_W5p0_L0p15_M4_b_L_0_15 - s8rf_pshort_W5p0_L0p15_M4_b_L_0_15 |
| COPY s8rf_pshort_W5p0_L0p15_M4_b_L_0_15 |
| } |
| s8rf_pshort_W5p0_L0p15_M4_b_L_0_15_W_5_05_tmp = INTERNAL s8rf_pshort_W5p0_L0p15_M4_b_L_0_15 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W5p0_L0p15_M4_b_L_0_15_W_5_05 = (WITH TEXT s8rf_pshort_W5p0_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W5p0_L0p15_M4_b_L_0_15_W_5_05_tmp |
| s8rf_pshort_W5p0_L0p15_M4_b_valid = COPY s8rf_pshort_W5p0_L0p15_M4_b_L_0_15_W_5_05 |
| "k_54_s8rf_pshort_W5p0_L0p15_M4_b_valid" { |
| @ keep: s8rf_pshort_W5p0_L0p15_M4_b_valid - s8rf_pshort_W5p0_L0p15_M4_b_valid |
| COPY s8rf_pshort_W5p0_L0p15_M4_b_valid |
| } |
| s8rf_pshort_W5p0_L0p15_M4_b_invalid = s8rf_pshort_W5p0_L0p15_M4_b NOT (exemptDecaps OR s8rf_pshort_W5p0_L0p15_M4_b_valid) |
| "r_559_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W5p0_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W5p0_L0p15_M4_b_invalid |
| } |
| s8rf_pshort_W5p0_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W5p0_L0p15_M2_b") |
| "k_55_s8rf_pshort_W5p0_L0p15_M2_b" { |
| @ keep: s8rf_pshort_W5p0_L0p15_M2_b - s8rf_pshort_W5p0_L0p15_M2_b |
| COPY s8rf_pshort_W5p0_L0p15_M2_b |
| } |
| s8rf_pshort_W5p0_L0p15_M2_b_L_0_15 = LENGTH (s8rf_pshort_W5p0_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_56_s8rf_pshort_W5p0_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_pshort_W5p0_L0p15_M2_b_L_0_15 - s8rf_pshort_W5p0_L0p15_M2_b_L_0_15 |
| COPY s8rf_pshort_W5p0_L0p15_M2_b_L_0_15 |
| } |
| s8rf_pshort_W5p0_L0p15_M2_b_L_0_15_W_5_05_tmp = INTERNAL s8rf_pshort_W5p0_L0p15_M2_b_L_0_15 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W5p0_L0p15_M2_b_L_0_15_W_5_05 = (WITH TEXT s8rf_pshort_W5p0_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W5p0_L0p15_M2_b_L_0_15_W_5_05_tmp |
| s8rf_pshort_W5p0_L0p15_M2_b_valid = COPY s8rf_pshort_W5p0_L0p15_M2_b_L_0_15_W_5_05 |
| "k_57_s8rf_pshort_W5p0_L0p15_M2_b_valid" { |
| @ keep: s8rf_pshort_W5p0_L0p15_M2_b_valid - s8rf_pshort_W5p0_L0p15_M2_b_valid |
| COPY s8rf_pshort_W5p0_L0p15_M2_b_valid |
| } |
| s8rf_pshort_W5p0_L0p15_M2_b_invalid = s8rf_pshort_W5p0_L0p15_M2_b NOT (exemptDecaps OR s8rf_pshort_W5p0_L0p15_M2_b_valid) |
| "r_560_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W5p0_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W5p0_L0p15_M2_b_invalid |
| } |
| s8rf_pshort_W3p0_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_pshort_W3p0_L0p15_2F") |
| "k_58_s8rf_pshort_W3p0_L0p15_2F" { |
| @ keep: s8rf_pshort_W3p0_L0p15_2F - s8rf_pshort_W3p0_L0p15_2F |
| COPY s8rf_pshort_W3p0_L0p15_2F |
| } |
| s8rf_pshort_W3p0_L0p15_2F_L_0_15 = LENGTH (s8rf_pshort_W3p0_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_59_s8rf_pshort_W3p0_L0p15_2F_L_0_15" { |
| @ keep: s8rf_pshort_W3p0_L0p15_2F_L_0_15 - s8rf_pshort_W3p0_L0p15_2F_L_0_15 |
| COPY s8rf_pshort_W3p0_L0p15_2F_L_0_15 |
| } |
| s8rf_pshort_W3p0_L0p15_2F_L_0_15_W_3_00_tmp = INTERNAL s8rf_pshort_W3p0_L0p15_2F_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W3p0_L0p15_2F_L_0_15_W_3_00 = (WITH TEXT s8rf_pshort_W3p0_L0p15_2F "dummy_poly" textlabel) OR s8rf_pshort_W3p0_L0p15_2F_L_0_15_W_3_00_tmp |
| s8rf_pshort_W3p0_L0p15_2F_valid = COPY s8rf_pshort_W3p0_L0p15_2F_L_0_15_W_3_00 |
| "k_60_s8rf_pshort_W3p0_L0p15_2F_valid" { |
| @ keep: s8rf_pshort_W3p0_L0p15_2F_valid - s8rf_pshort_W3p0_L0p15_2F_valid |
| COPY s8rf_pshort_W3p0_L0p15_2F_valid |
| } |
| s8rf_pshort_W3p0_L0p15_2F_invalid = s8rf_pshort_W3p0_L0p15_2F NOT (exemptDecaps OR s8rf_pshort_W3p0_L0p15_2F_valid) |
| "r_561_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W3p0_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W3p0_L0p15_2F_invalid |
| } |
| s8rf_pshort_W5p0_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W5p0_L0p18_M4_b") |
| "k_61_s8rf_pshort_W5p0_L0p18_M4_b" { |
| @ keep: s8rf_pshort_W5p0_L0p18_M4_b - s8rf_pshort_W5p0_L0p18_M4_b |
| COPY s8rf_pshort_W5p0_L0p18_M4_b |
| } |
| s8rf_pshort_W5p0_L0p18_M4_b_L_0_18 = LENGTH (s8rf_pshort_W5p0_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_62_s8rf_pshort_W5p0_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_pshort_W5p0_L0p18_M4_b_L_0_18 - s8rf_pshort_W5p0_L0p18_M4_b_L_0_18 |
| COPY s8rf_pshort_W5p0_L0p18_M4_b_L_0_18 |
| } |
| s8rf_pshort_W5p0_L0p18_M4_b_L_0_18_W_5_05_tmp = INTERNAL s8rf_pshort_W5p0_L0p18_M4_b_L_0_18 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W5p0_L0p18_M4_b_L_0_18_W_5_05 = (WITH TEXT s8rf_pshort_W5p0_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W5p0_L0p18_M4_b_L_0_18_W_5_05_tmp |
| s8rf_pshort_W5p0_L0p18_M4_b_valid = COPY s8rf_pshort_W5p0_L0p18_M4_b_L_0_18_W_5_05 |
| "k_63_s8rf_pshort_W5p0_L0p18_M4_b_valid" { |
| @ keep: s8rf_pshort_W5p0_L0p18_M4_b_valid - s8rf_pshort_W5p0_L0p18_M4_b_valid |
| COPY s8rf_pshort_W5p0_L0p18_M4_b_valid |
| } |
| s8rf_pshort_W5p0_L0p18_M4_b_invalid = s8rf_pshort_W5p0_L0p18_M4_b NOT (exemptDecaps OR s8rf_pshort_W5p0_L0p18_M4_b_valid) |
| "r_562_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W5p0_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W5p0_L0p18_M4_b_invalid |
| } |
| s8rf_pshort_W1p68_L0p15_4F = rfGate AND (EXTENT CELL "s8rf_pshort_W1p68_L0p15_4F") |
| "k_64_s8rf_pshort_W1p68_L0p15_4F" { |
| @ keep: s8rf_pshort_W1p68_L0p15_4F - s8rf_pshort_W1p68_L0p15_4F |
| COPY s8rf_pshort_W1p68_L0p15_4F |
| } |
| s8rf_pshort_W1p68_L0p15_4F_L_0_15 = LENGTH (s8rf_pshort_W1p68_L0p15_4F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_65_s8rf_pshort_W1p68_L0p15_4F_L_0_15" { |
| @ keep: s8rf_pshort_W1p68_L0p15_4F_L_0_15 - s8rf_pshort_W1p68_L0p15_4F_L_0_15 |
| COPY s8rf_pshort_W1p68_L0p15_4F_L_0_15 |
| } |
| s8rf_pshort_W1p68_L0p15_4F_L_0_15_W_1_68_tmp = INTERNAL s8rf_pshort_W1p68_L0p15_4F_L_0_15 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p68_L0p15_4F_L_0_15_W_1_68 = (WITH TEXT s8rf_pshort_W1p68_L0p15_4F "dummy_poly" textlabel) OR s8rf_pshort_W1p68_L0p15_4F_L_0_15_W_1_68_tmp |
| s8rf_pshort_W1p68_L0p15_4F_valid = COPY s8rf_pshort_W1p68_L0p15_4F_L_0_15_W_1_68 |
| "k_66_s8rf_pshort_W1p68_L0p15_4F_valid" { |
| @ keep: s8rf_pshort_W1p68_L0p15_4F_valid - s8rf_pshort_W1p68_L0p15_4F_valid |
| COPY s8rf_pshort_W1p68_L0p15_4F_valid |
| } |
| s8rf_pshort_W1p68_L0p15_4F_invalid = s8rf_pshort_W1p68_L0p15_4F NOT (exemptDecaps OR s8rf_pshort_W1p68_L0p15_4F_valid) |
| "r_563_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p68_L0p15_4F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p68_L0p15_4F_invalid |
| } |
| s8rf_pshort_W3p0_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W3p0_L0p18_M4_b") |
| "k_67_s8rf_pshort_W3p0_L0p18_M4_b" { |
| @ keep: s8rf_pshort_W3p0_L0p18_M4_b - s8rf_pshort_W3p0_L0p18_M4_b |
| COPY s8rf_pshort_W3p0_L0p18_M4_b |
| } |
| s8rf_pshort_W3p0_L0p18_M4_b_L_0_18 = LENGTH (s8rf_pshort_W3p0_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_68_s8rf_pshort_W3p0_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_pshort_W3p0_L0p18_M4_b_L_0_18 - s8rf_pshort_W3p0_L0p18_M4_b_L_0_18 |
| COPY s8rf_pshort_W3p0_L0p18_M4_b_L_0_18 |
| } |
| s8rf_pshort_W3p0_L0p18_M4_b_L_0_18_W_3_01_tmp = INTERNAL s8rf_pshort_W3p0_L0p18_M4_b_L_0_18 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W3p0_L0p18_M4_b_L_0_18_W_3_01 = (WITH TEXT s8rf_pshort_W3p0_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W3p0_L0p18_M4_b_L_0_18_W_3_01_tmp |
| s8rf_pshort_W3p0_L0p18_M4_b_valid = COPY s8rf_pshort_W3p0_L0p18_M4_b_L_0_18_W_3_01 |
| "k_69_s8rf_pshort_W3p0_L0p18_M4_b_valid" { |
| @ keep: s8rf_pshort_W3p0_L0p18_M4_b_valid - s8rf_pshort_W3p0_L0p18_M4_b_valid |
| COPY s8rf_pshort_W3p0_L0p18_M4_b_valid |
| } |
| s8rf_pshort_W3p0_L0p18_M4_b_invalid = s8rf_pshort_W3p0_L0p18_M4_b NOT (exemptDecaps OR s8rf_pshort_W3p0_L0p18_M4_b_valid) |
| "r_564_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W3p0_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W3p0_L0p18_M4_b_invalid |
| } |
| s8rf_pshort_W5p0_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W5p0_L0p18_M2_b") |
| "k_70_s8rf_pshort_W5p0_L0p18_M2_b" { |
| @ keep: s8rf_pshort_W5p0_L0p18_M2_b - s8rf_pshort_W5p0_L0p18_M2_b |
| COPY s8rf_pshort_W5p0_L0p18_M2_b |
| } |
| s8rf_pshort_W5p0_L0p18_M2_b_L_0_18 = LENGTH (s8rf_pshort_W5p0_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_71_s8rf_pshort_W5p0_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_pshort_W5p0_L0p18_M2_b_L_0_18 - s8rf_pshort_W5p0_L0p18_M2_b_L_0_18 |
| COPY s8rf_pshort_W5p0_L0p18_M2_b_L_0_18 |
| } |
| s8rf_pshort_W5p0_L0p18_M2_b_L_0_18_W_5_05_tmp = INTERNAL s8rf_pshort_W5p0_L0p18_M2_b_L_0_18 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W5p0_L0p18_M2_b_L_0_18_W_5_05 = (WITH TEXT s8rf_pshort_W5p0_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W5p0_L0p18_M2_b_L_0_18_W_5_05_tmp |
| s8rf_pshort_W5p0_L0p18_M2_b_valid = COPY s8rf_pshort_W5p0_L0p18_M2_b_L_0_18_W_5_05 |
| "k_72_s8rf_pshort_W5p0_L0p18_M2_b_valid" { |
| @ keep: s8rf_pshort_W5p0_L0p18_M2_b_valid - s8rf_pshort_W5p0_L0p18_M2_b_valid |
| COPY s8rf_pshort_W5p0_L0p18_M2_b_valid |
| } |
| s8rf_pshort_W5p0_L0p18_M2_b_invalid = s8rf_pshort_W5p0_L0p18_M2_b NOT (exemptDecaps OR s8rf_pshort_W5p0_L0p18_M2_b_valid) |
| "r_565_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W5p0_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W5p0_L0p18_M2_b_invalid |
| } |
| s8rf_pshort_W3p0_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W3p0_L0p25_M2_b") |
| "k_73_s8rf_pshort_W3p0_L0p25_M2_b" { |
| @ keep: s8rf_pshort_W3p0_L0p25_M2_b - s8rf_pshort_W3p0_L0p25_M2_b |
| COPY s8rf_pshort_W3p0_L0p25_M2_b |
| } |
| s8rf_pshort_W3p0_L0p25_M2_b_L_0_25 = LENGTH (s8rf_pshort_W3p0_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_74_s8rf_pshort_W3p0_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_pshort_W3p0_L0p25_M2_b_L_0_25 - s8rf_pshort_W3p0_L0p25_M2_b_L_0_25 |
| COPY s8rf_pshort_W3p0_L0p25_M2_b_L_0_25 |
| } |
| s8rf_pshort_W3p0_L0p25_M2_b_L_0_25_W_3_01_tmp = INTERNAL s8rf_pshort_W3p0_L0p25_M2_b_L_0_25 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W3p0_L0p25_M2_b_L_0_25_W_3_01 = (WITH TEXT s8rf_pshort_W3p0_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W3p0_L0p25_M2_b_L_0_25_W_3_01_tmp |
| s8rf_pshort_W3p0_L0p25_M2_b_valid = COPY s8rf_pshort_W3p0_L0p25_M2_b_L_0_25_W_3_01 |
| "k_75_s8rf_pshort_W3p0_L0p25_M2_b_valid" { |
| @ keep: s8rf_pshort_W3p0_L0p25_M2_b_valid - s8rf_pshort_W3p0_L0p25_M2_b_valid |
| COPY s8rf_pshort_W3p0_L0p25_M2_b_valid |
| } |
| s8rf_pshort_W3p0_L0p25_M2_b_invalid = s8rf_pshort_W3p0_L0p25_M2_b NOT (exemptDecaps OR s8rf_pshort_W3p0_L0p25_M2_b_valid) |
| "r_566_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W3p0_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W3p0_L0p25_M2_b_invalid |
| } |
| s8rf_pshort_W1p65_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W1p65_L0p15_M2_b") |
| "k_76_s8rf_pshort_W1p65_L0p15_M2_b" { |
| @ keep: s8rf_pshort_W1p65_L0p15_M2_b - s8rf_pshort_W1p65_L0p15_M2_b |
| COPY s8rf_pshort_W1p65_L0p15_M2_b |
| } |
| s8rf_pshort_W1p65_L0p15_M2_b_L_0_15 = LENGTH (s8rf_pshort_W1p65_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_77_s8rf_pshort_W1p65_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_pshort_W1p65_L0p15_M2_b_L_0_15 - s8rf_pshort_W1p65_L0p15_M2_b_L_0_15 |
| COPY s8rf_pshort_W1p65_L0p15_M2_b_L_0_15 |
| } |
| s8rf_pshort_W1p65_L0p15_M2_b_L_0_15_W_1_65_tmp = INTERNAL s8rf_pshort_W1p65_L0p15_M2_b_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p65_L0p15_M2_b_L_0_15_W_1_65 = (WITH TEXT s8rf_pshort_W1p65_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W1p65_L0p15_M2_b_L_0_15_W_1_65_tmp |
| s8rf_pshort_W1p65_L0p15_M2_b_valid = COPY s8rf_pshort_W1p65_L0p15_M2_b_L_0_15_W_1_65 |
| "k_78_s8rf_pshort_W1p65_L0p15_M2_b_valid" { |
| @ keep: s8rf_pshort_W1p65_L0p15_M2_b_valid - s8rf_pshort_W1p65_L0p15_M2_b_valid |
| COPY s8rf_pshort_W1p65_L0p15_M2_b_valid |
| } |
| s8rf_pshort_W1p65_L0p15_M2_b_invalid = s8rf_pshort_W1p65_L0p15_M2_b NOT (exemptDecaps OR s8rf_pshort_W1p65_L0p15_M2_b_valid) |
| "r_567_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p65_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p65_L0p15_M2_b_invalid |
| } |
| pshort_L_0_15 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_79_pshort_L_0_15" { |
| @ keep: pshort_L_0_15 - pshort_L_0_15 |
| COPY pshort_L_0_15 |
| } |
| pshort_L_0_15_W_0_42_tmp = INTERNAL pshort_L_0_15 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_0_42_tmp |
| pshort_L_0_15_W_0_55_tmp = INTERNAL pshort_L_0_15 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_0_55_tmp |
| pshort_L_0_15_W_0_64_tmp = INTERNAL pshort_L_0_15 == 0.64 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_0_64 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_0_64_tmp |
| pshort_L_0_15_W_0_84_tmp = INTERNAL pshort_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_0_84 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_0_84_tmp |
| pshort_L_0_15_W_1_00_tmp = INTERNAL pshort_L_0_15 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_1_00_tmp |
| pshort_L_0_15_W_1_12_tmp = INTERNAL pshort_L_0_15 == 1.12 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_1_12 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_1_12_tmp |
| pshort_L_0_15_W_1_26_tmp = INTERNAL pshort_L_0_15 == 1.26 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_1_26 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_1_26_tmp |
| pshort_L_0_15_W_1_65_tmp = INTERNAL pshort_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_1_65 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_1_65_tmp |
| pshort_L_0_15_W_1_68_tmp = INTERNAL pshort_L_0_15 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_1_68 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_1_68_tmp |
| pshort_L_0_15_W_2_00_tmp = INTERNAL pshort_L_0_15 == 2.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_2_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_2_00_tmp |
| pshort_L_0_15_W_3_00_tmp = INTERNAL pshort_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_3_00_tmp |
| pshort_L_0_15_W_5_00_tmp = INTERNAL pshort_L_0_15 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_5_00_tmp |
| pshort_L_0_15_W_7_00_tmp = INTERNAL pshort_L_0_15 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_15_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_15_W_7_00_tmp |
| pshort_L_0_17 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 0.17 |
| "k_80_pshort_L_0_17" { |
| @ keep: pshort_L_0_17 - pshort_L_0_17 |
| COPY pshort_L_0_17 |
| } |
| pshort_L_0_17_W_0_42_tmp = INTERNAL pshort_L_0_17 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_17_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_17_W_0_42_tmp |
| pshort_L_0_17_W_0_55_tmp = INTERNAL pshort_L_0_17 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_17_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_17_W_0_55_tmp |
| pshort_L_0_17_W_0_64_tmp = INTERNAL pshort_L_0_17 == 0.64 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_17_W_0_64 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_17_W_0_64_tmp |
| pshort_L_0_17_W_0_84_tmp = INTERNAL pshort_L_0_17 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_17_W_0_84 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_17_W_0_84_tmp |
| pshort_L_0_17_W_1_00_tmp = INTERNAL pshort_L_0_17 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_17_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_17_W_1_00_tmp |
| pshort_L_0_17_W_1_12_tmp = INTERNAL pshort_L_0_17 == 1.12 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_17_W_1_12 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_17_W_1_12_tmp |
| pshort_L_0_18 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_81_pshort_L_0_18" { |
| @ keep: pshort_L_0_18 - pshort_L_0_18 |
| COPY pshort_L_0_18 |
| } |
| pshort_L_0_18_W_0_42_tmp = INTERNAL pshort_L_0_18 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_0_42_tmp |
| pshort_L_0_18_W_0_55_tmp = INTERNAL pshort_L_0_18 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_0_55_tmp |
| pshort_L_0_18_W_0_64_tmp = INTERNAL pshort_L_0_18 == 0.64 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_0_64 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_0_64_tmp |
| pshort_L_0_18_W_0_84_tmp = INTERNAL pshort_L_0_18 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_0_84 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_0_84_tmp |
| pshort_L_0_18_W_1_00_tmp = INTERNAL pshort_L_0_18 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_1_00_tmp |
| pshort_L_0_18_W_1_12_tmp = INTERNAL pshort_L_0_18 == 1.12 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_1_12 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_1_12_tmp |
| pshort_L_0_18_W_1_26_tmp = INTERNAL pshort_L_0_18 == 1.26 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_1_26 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_1_26_tmp |
| pshort_L_0_18_W_1_68_tmp = INTERNAL pshort_L_0_18 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_1_68 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_1_68_tmp |
| pshort_L_0_18_W_2_00_tmp = INTERNAL pshort_L_0_18 == 2.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_2_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_2_00_tmp |
| pshort_L_0_18_W_3_00_tmp = INTERNAL pshort_L_0_18 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_3_00_tmp |
| pshort_L_0_18_W_5_00_tmp = INTERNAL pshort_L_0_18 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_5_00_tmp |
| pshort_L_0_18_W_7_00_tmp = INTERNAL pshort_L_0_18 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_18_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_18_W_7_00_tmp |
| pshort_L_0_25 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_82_pshort_L_0_25" { |
| @ keep: pshort_L_0_25 - pshort_L_0_25 |
| COPY pshort_L_0_25 |
| } |
| pshort_L_0_25_W_1_00_tmp = INTERNAL pshort_L_0_25 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_25_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_25_W_1_00_tmp |
| pshort_L_0_25_W_3_00_tmp = INTERNAL pshort_L_0_25 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_25_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_25_W_3_00_tmp |
| pshort_L_0_25_W_5_00_tmp = INTERNAL pshort_L_0_25 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_25_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_25_W_5_00_tmp |
| pshort_L_0_25_W_7_00_tmp = INTERNAL pshort_L_0_25 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_25_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_25_W_7_00_tmp |
| pshort_L_0_50 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_83_pshort_L_0_50" { |
| @ keep: pshort_L_0_50 - pshort_L_0_50 |
| COPY pshort_L_0_50 |
| } |
| pshort_L_0_50_W_0_42_tmp = INTERNAL pshort_L_0_50 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_50_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_50_W_0_42_tmp |
| pshort_L_0_50_W_0_55_tmp = INTERNAL pshort_L_0_50 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_50_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_50_W_0_55_tmp |
| pshort_L_0_50_W_1_00_tmp = INTERNAL pshort_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_50_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_50_W_1_00_tmp |
| pshort_L_0_50_W_3_00_tmp = INTERNAL pshort_L_0_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_50_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_50_W_3_00_tmp |
| pshort_L_0_50_W_5_00_tmp = INTERNAL pshort_L_0_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_50_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_50_W_5_00_tmp |
| pshort_L_0_50_W_7_00_tmp = INTERNAL pshort_L_0_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_0_50_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_0_50_W_7_00_tmp |
| pshort_L_1_00 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_84_pshort_L_1_00" { |
| @ keep: pshort_L_1_00 - pshort_L_1_00 |
| COPY pshort_L_1_00 |
| } |
| pshort_L_1_00_W_0_42_tmp = INTERNAL pshort_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_1_00_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_1_00_W_0_42_tmp |
| pshort_L_1_00_W_0_55_tmp = INTERNAL pshort_L_1_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_1_00_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_1_00_W_0_55_tmp |
| pshort_L_1_00_W_1_00_tmp = INTERNAL pshort_L_1_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_1_00_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_1_00_W_1_00_tmp |
| pshort_L_1_00_W_3_00_tmp = INTERNAL pshort_L_1_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_1_00_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_1_00_W_3_00_tmp |
| pshort_L_1_00_W_5_00_tmp = INTERNAL pshort_L_1_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_1_00_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_1_00_W_5_00_tmp |
| pshort_L_1_00_W_7_00_tmp = INTERNAL pshort_L_1_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_1_00_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_1_00_W_7_00_tmp |
| pshort_L_2_00 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_85_pshort_L_2_00" { |
| @ keep: pshort_L_2_00 - pshort_L_2_00 |
| COPY pshort_L_2_00 |
| } |
| pshort_L_2_00_W_0_42_tmp = INTERNAL pshort_L_2_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_2_00_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_2_00_W_0_42_tmp |
| pshort_L_2_00_W_0_55_tmp = INTERNAL pshort_L_2_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_2_00_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_2_00_W_0_55_tmp |
| pshort_L_2_00_W_1_00_tmp = INTERNAL pshort_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_2_00_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_2_00_W_1_00_tmp |
| pshort_L_2_00_W_3_00_tmp = INTERNAL pshort_L_2_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_2_00_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_2_00_W_3_00_tmp |
| pshort_L_2_00_W_5_00_tmp = INTERNAL pshort_L_2_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_2_00_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_2_00_W_5_00_tmp |
| pshort_L_2_00_W_7_00_tmp = INTERNAL pshort_L_2_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_2_00_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_2_00_W_7_00_tmp |
| pshort_L_4_00 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_86_pshort_L_4_00" { |
| @ keep: pshort_L_4_00 - pshort_L_4_00 |
| COPY pshort_L_4_00 |
| } |
| pshort_L_4_00_W_0_42_tmp = INTERNAL pshort_L_4_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_4_00_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_4_00_W_0_42_tmp |
| pshort_L_4_00_W_0_55_tmp = INTERNAL pshort_L_4_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_4_00_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_4_00_W_0_55_tmp |
| pshort_L_4_00_W_1_00_tmp = INTERNAL pshort_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_4_00_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_4_00_W_1_00_tmp |
| pshort_L_4_00_W_3_00_tmp = INTERNAL pshort_L_4_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_4_00_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_4_00_W_3_00_tmp |
| pshort_L_4_00_W_5_00_tmp = INTERNAL pshort_L_4_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_4_00_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_4_00_W_5_00_tmp |
| pshort_L_4_00_W_7_00_tmp = INTERNAL pshort_L_4_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_4_00_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_4_00_W_7_00_tmp |
| pshort_L_8_00 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_87_pshort_L_8_00" { |
| @ keep: pshort_L_8_00 - pshort_L_8_00 |
| COPY pshort_L_8_00 |
| } |
| pshort_L_8_00_W_0_42_tmp = INTERNAL pshort_L_8_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_8_00_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_8_00_W_0_42_tmp |
| pshort_L_8_00_W_0_55_tmp = INTERNAL pshort_L_8_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_8_00_W_0_55 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_8_00_W_0_55_tmp |
| pshort_L_8_00_W_1_00_tmp = INTERNAL pshort_L_8_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_8_00_W_1_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_8_00_W_1_00_tmp |
| pshort_L_8_00_W_3_00_tmp = INTERNAL pshort_L_8_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_8_00_W_3_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_8_00_W_3_00_tmp |
| pshort_L_8_00_W_5_00_tmp = INTERNAL pshort_L_8_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_8_00_W_5_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_8_00_W_5_00_tmp |
| pshort_L_8_00_W_7_00_tmp = INTERNAL pshort_L_8_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_8_00_W_7_00 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_8_00_W_7_00_tmp |
| pshort_L_20_0 = LENGTH ("pshort" COINCIDENT INSIDE EDGE diff) == 20.0 |
| "k_88_pshort_L_20_0" { |
| @ keep: pshort_L_20_0 - pshort_L_20_0 |
| COPY pshort_L_20_0 |
| } |
| pshort_L_20_0_W_0_42_tmp = INTERNAL pshort_L_20_0 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| pshort_L_20_0_W_0_42 = (WITH TEXT "pshort" "dummy_poly" textlabel) OR pshort_L_20_0_W_0_42_tmp |
| pshort_valid = pshort_L_20_0_W_0_42 OR |
| (pshort_L_8_00_W_7_00 OR |
| (pshort_L_8_00_W_5_00 OR |
| (pshort_L_8_00_W_3_00 OR |
| (pshort_L_8_00_W_1_00 OR |
| (pshort_L_8_00_W_0_55 OR |
| (pshort_L_8_00_W_0_42 OR |
| (pshort_L_4_00_W_7_00 OR |
| (pshort_L_4_00_W_5_00 OR |
| (pshort_L_4_00_W_3_00 OR |
| (pshort_L_4_00_W_1_00 OR |
| (pshort_L_4_00_W_0_55 OR |
| (pshort_L_4_00_W_0_42 OR |
| (pshort_L_2_00_W_7_00 OR |
| (pshort_L_2_00_W_5_00 OR |
| (pshort_L_2_00_W_3_00 OR |
| (pshort_L_2_00_W_1_00 OR |
| (pshort_L_2_00_W_0_55 OR |
| (pshort_L_2_00_W_0_42 OR |
| (pshort_L_1_00_W_7_00 OR |
| (pshort_L_1_00_W_5_00 OR |
| (pshort_L_1_00_W_3_00 OR |
| (pshort_L_1_00_W_1_00 OR |
| (pshort_L_1_00_W_0_55 OR |
| (pshort_L_1_00_W_0_42 OR |
| (pshort_L_0_50_W_7_00 OR |
| (pshort_L_0_50_W_5_00 OR |
| (pshort_L_0_50_W_3_00 OR |
| (pshort_L_0_50_W_1_00 OR |
| (pshort_L_0_50_W_0_55 OR |
| (pshort_L_0_50_W_0_42 OR |
| (pshort_L_0_25_W_7_00 OR |
| (pshort_L_0_25_W_5_00 OR |
| (pshort_L_0_25_W_3_00 OR |
| (pshort_L_0_25_W_1_00 OR |
| (pshort_L_0_18_W_7_00 OR |
| (pshort_L_0_18_W_5_00 OR |
| (pshort_L_0_18_W_3_00 OR |
| (pshort_L_0_18_W_2_00 OR |
| (pshort_L_0_18_W_1_68 OR |
| (pshort_L_0_18_W_1_26 OR |
| (pshort_L_0_18_W_1_12 OR |
| (pshort_L_0_18_W_1_00 OR |
| (pshort_L_0_18_W_0_84 OR |
| (pshort_L_0_18_W_0_64 OR |
| (pshort_L_0_18_W_0_55 OR |
| (pshort_L_0_18_W_0_42 OR |
| (pshort_L_0_17_W_1_12 OR |
| (pshort_L_0_17_W_1_00 OR |
| (pshort_L_0_17_W_0_84 OR |
| (pshort_L_0_17_W_0_64 OR |
| (pshort_L_0_17_W_0_55 OR |
| (pshort_L_0_17_W_0_42 OR |
| (pshort_L_0_15_W_7_00 OR |
| (pshort_L_0_15_W_5_00 OR |
| (pshort_L_0_15_W_3_00 OR |
| (pshort_L_0_15_W_2_00 OR |
| (pshort_L_0_15_W_1_68 OR |
| (pshort_L_0_15_W_1_65 OR |
| (pshort_L_0_15_W_1_26 OR |
| (pshort_L_0_15_W_1_12 OR |
| (pshort_L_0_15_W_1_00 OR |
| (pshort_L_0_15_W_0_84 OR |
| (pshort_L_0_15_W_0_64 OR |
| (pshort_L_0_15_W_0_55 OR pshort_L_0_15_W_0_42)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) |
| "k_89_pshort_valid" { |
| @ keep: pshort_valid - pshort_valid |
| COPY pshort_valid |
| } |
| pshort_invalid = pshort NOT (exemptDecaps OR pshort_valid) |
| "r_568_Poly.X.1" { |
| @ Poly.X.1: This pshort device has an invalid W/L. Please see MRGA |
| COPY pshort_invalid |
| } |
| ppu_L_0_15 = LENGTH ("ppu" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_90_ppu_L_0_15" { |
| @ keep: ppu_L_0_15 - ppu_L_0_15 |
| COPY ppu_L_0_15 |
| } |
| ppu_L_0_15_W_0_14_tmp = INTERNAL ppu_L_0_15 == 0.14 OPPOSITE PARALLEL ONLY REGION |
| ppu_L_0_15_W_0_14 = (WITH TEXT "ppu" "dummy_poly" textlabel) OR ppu_L_0_15_W_0_14_tmp |
| ppu_valid = COPY ppu_L_0_15_W_0_14 |
| "k_91_ppu_valid" { |
| @ keep: ppu_valid - ppu_valid |
| COPY ppu_valid |
| } |
| ppu_invalid = ppu NOT (exemptDecaps OR ppu_valid) |
| "r_569_Poly.X.1" { |
| @ Poly.X.1: This ppu device has an invalid W/L. Please see MRGA |
| COPY ppu_invalid |
| } |
| s8rf_pshort_W1p68_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_pshort_W1p68_L0p15_2F") |
| "k_92_s8rf_pshort_W1p68_L0p15_2F" { |
| @ keep: s8rf_pshort_W1p68_L0p15_2F - s8rf_pshort_W1p68_L0p15_2F |
| COPY s8rf_pshort_W1p68_L0p15_2F |
| } |
| s8rf_pshort_W1p68_L0p15_2F_L_0_15 = LENGTH (s8rf_pshort_W1p68_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_93_s8rf_pshort_W1p68_L0p15_2F_L_0_15" { |
| @ keep: s8rf_pshort_W1p68_L0p15_2F_L_0_15 - s8rf_pshort_W1p68_L0p15_2F_L_0_15 |
| COPY s8rf_pshort_W1p68_L0p15_2F_L_0_15 |
| } |
| s8rf_pshort_W1p68_L0p15_2F_L_0_15_W_1_68_tmp = INTERNAL s8rf_pshort_W1p68_L0p15_2F_L_0_15 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p68_L0p15_2F_L_0_15_W_1_68 = (WITH TEXT s8rf_pshort_W1p68_L0p15_2F "dummy_poly" textlabel) OR s8rf_pshort_W1p68_L0p15_2F_L_0_15_W_1_68_tmp |
| s8rf_pshort_W1p68_L0p15_2F_valid = COPY s8rf_pshort_W1p68_L0p15_2F_L_0_15_W_1_68 |
| "k_94_s8rf_pshort_W1p68_L0p15_2F_valid" { |
| @ keep: s8rf_pshort_W1p68_L0p15_2F_valid - s8rf_pshort_W1p68_L0p15_2F_valid |
| COPY s8rf_pshort_W1p68_L0p15_2F_valid |
| } |
| s8rf_pshort_W1p68_L0p15_2F_invalid = s8rf_pshort_W1p68_L0p15_2F NOT (exemptDecaps OR s8rf_pshort_W1p68_L0p15_2F_valid) |
| "r_570_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p68_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p68_L0p15_2F_invalid |
| } |
| s8rf_pshort_W1p65_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W1p65_L0p18_M4_b") |
| "k_95_s8rf_pshort_W1p65_L0p18_M4_b" { |
| @ keep: s8rf_pshort_W1p65_L0p18_M4_b - s8rf_pshort_W1p65_L0p18_M4_b |
| COPY s8rf_pshort_W1p65_L0p18_M4_b |
| } |
| s8rf_pshort_W1p65_L0p18_M4_b_L_0_18 = LENGTH (s8rf_pshort_W1p65_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_96_s8rf_pshort_W1p65_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_pshort_W1p65_L0p18_M4_b_L_0_18 - s8rf_pshort_W1p65_L0p18_M4_b_L_0_18 |
| COPY s8rf_pshort_W1p65_L0p18_M4_b_L_0_18 |
| } |
| s8rf_pshort_W1p65_L0p18_M4_b_L_0_18_W_1_65_tmp = INTERNAL s8rf_pshort_W1p65_L0p18_M4_b_L_0_18 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p65_L0p18_M4_b_L_0_18_W_1_65 = (WITH TEXT s8rf_pshort_W1p65_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W1p65_L0p18_M4_b_L_0_18_W_1_65_tmp |
| s8rf_pshort_W1p65_L0p18_M4_b_valid = COPY s8rf_pshort_W1p65_L0p18_M4_b_L_0_18_W_1_65 |
| "k_97_s8rf_pshort_W1p65_L0p18_M4_b_valid" { |
| @ keep: s8rf_pshort_W1p65_L0p18_M4_b_valid - s8rf_pshort_W1p65_L0p18_M4_b_valid |
| COPY s8rf_pshort_W1p65_L0p18_M4_b_valid |
| } |
| s8rf_pshort_W1p65_L0p18_M4_b_invalid = s8rf_pshort_W1p65_L0p18_M4_b NOT (exemptDecaps OR s8rf_pshort_W1p65_L0p18_M4_b_valid) |
| "r_571_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p65_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p65_L0p18_M4_b_invalid |
| } |
| s8rf_pmedlvt_W1p68_L0p15_4F = rfGate AND (EXTENT CELL "s8rf_pmedlvt_W1p68_L0p15_4F") |
| "k_98_s8rf_pmedlvt_W1p68_L0p15_4F" { |
| @ keep: s8rf_pmedlvt_W1p68_L0p15_4F - s8rf_pmedlvt_W1p68_L0p15_4F |
| COPY s8rf_pmedlvt_W1p68_L0p15_4F |
| } |
| s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15 = LENGTH (s8rf_pmedlvt_W1p68_L0p15_4F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_99_s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15" { |
| @ keep: s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15 - s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15 |
| COPY s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15 |
| } |
| s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15_W_1_68_tmp = INTERNAL s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15_W_1_68 = (WITH TEXT s8rf_pmedlvt_W1p68_L0p15_4F "dummy_poly" textlabel) OR s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15_W_1_68_tmp |
| s8rf_pmedlvt_W1p68_L0p15_4F_valid = COPY s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15_W_1_68 |
| "k_100_s8rf_pmedlvt_W1p68_L0p15_4F_valid" { |
| @ keep: s8rf_pmedlvt_W1p68_L0p15_4F_valid - s8rf_pmedlvt_W1p68_L0p15_4F_valid |
| COPY s8rf_pmedlvt_W1p68_L0p15_4F_valid |
| } |
| s8rf_pmedlvt_W1p68_L0p15_4F_invalid = s8rf_pmedlvt_W1p68_L0p15_4F NOT (exemptDecaps OR s8rf_pmedlvt_W1p68_L0p15_4F_valid) |
| "r_572_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pmedlvt_W1p68_L0p15_4F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pmedlvt_W1p68_L0p15_4F_invalid |
| } |
| s8rf_pshort_W1p65_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W1p65_L0p18_M2_b") |
| "k_101_s8rf_pshort_W1p65_L0p18_M2_b" { |
| @ keep: s8rf_pshort_W1p65_L0p18_M2_b - s8rf_pshort_W1p65_L0p18_M2_b |
| COPY s8rf_pshort_W1p65_L0p18_M2_b |
| } |
| s8rf_pshort_W1p65_L0p18_M2_b_L_0_18 = LENGTH (s8rf_pshort_W1p65_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_102_s8rf_pshort_W1p65_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_pshort_W1p65_L0p18_M2_b_L_0_18 - s8rf_pshort_W1p65_L0p18_M2_b_L_0_18 |
| COPY s8rf_pshort_W1p65_L0p18_M2_b_L_0_18 |
| } |
| s8rf_pshort_W1p65_L0p18_M2_b_L_0_18_W_1_65_tmp = INTERNAL s8rf_pshort_W1p65_L0p18_M2_b_L_0_18 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p65_L0p18_M2_b_L_0_18_W_1_65 = (WITH TEXT s8rf_pshort_W1p65_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W1p65_L0p18_M2_b_L_0_18_W_1_65_tmp |
| s8rf_pshort_W1p65_L0p18_M2_b_valid = COPY s8rf_pshort_W1p65_L0p18_M2_b_L_0_18_W_1_65 |
| "k_103_s8rf_pshort_W1p65_L0p18_M2_b_valid" { |
| @ keep: s8rf_pshort_W1p65_L0p18_M2_b_valid - s8rf_pshort_W1p65_L0p18_M2_b_valid |
| COPY s8rf_pshort_W1p65_L0p18_M2_b_valid |
| } |
| s8rf_pshort_W1p65_L0p18_M2_b_invalid = s8rf_pshort_W1p65_L0p18_M2_b NOT (exemptDecaps OR s8rf_pshort_W1p65_L0p18_M2_b_valid) |
| "r_573_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p65_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p65_L0p18_M2_b_invalid |
| } |
| s8rf_pshort_W1p65_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_pshort_W1p65_L0p15_M4_b") |
| "k_104_s8rf_pshort_W1p65_L0p15_M4_b" { |
| @ keep: s8rf_pshort_W1p65_L0p15_M4_b - s8rf_pshort_W1p65_L0p15_M4_b |
| COPY s8rf_pshort_W1p65_L0p15_M4_b |
| } |
| s8rf_pshort_W1p65_L0p15_M4_b_L_0_15 = LENGTH (s8rf_pshort_W1p65_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_105_s8rf_pshort_W1p65_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_pshort_W1p65_L0p15_M4_b_L_0_15 - s8rf_pshort_W1p65_L0p15_M4_b_L_0_15 |
| COPY s8rf_pshort_W1p65_L0p15_M4_b_L_0_15 |
| } |
| s8rf_pshort_W1p65_L0p15_M4_b_L_0_15_W_1_65_tmp = INTERNAL s8rf_pshort_W1p65_L0p15_M4_b_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W1p65_L0p15_M4_b_L_0_15_W_1_65 = (WITH TEXT s8rf_pshort_W1p65_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_pshort_W1p65_L0p15_M4_b_L_0_15_W_1_65_tmp |
| s8rf_pshort_W1p65_L0p15_M4_b_valid = COPY s8rf_pshort_W1p65_L0p15_M4_b_L_0_15_W_1_65 |
| "k_106_s8rf_pshort_W1p65_L0p15_M4_b_valid" { |
| @ keep: s8rf_pshort_W1p65_L0p15_M4_b_valid - s8rf_pshort_W1p65_L0p15_M4_b_valid |
| COPY s8rf_pshort_W1p65_L0p15_M4_b_valid |
| } |
| s8rf_pshort_W1p65_L0p15_M4_b_invalid = s8rf_pshort_W1p65_L0p15_M4_b NOT (exemptDecaps OR s8rf_pshort_W1p65_L0p15_M4_b_valid) |
| "r_574_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W1p65_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W1p65_L0p15_M4_b_invalid |
| } |
| phighvt_L_0_15 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_107_phighvt_L_0_15" { |
| @ keep: phighvt_L_0_15 - phighvt_L_0_15 |
| COPY phighvt_L_0_15 |
| } |
| phighvt_L_0_15_W_0_36_tmp = INTERNAL phighvt_L_0_15 == 0.36 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_36 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_36_tmp |
| phighvt_L_0_15_W_0_42_tmp = INTERNAL phighvt_L_0_15 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_42_tmp |
| phighvt_L_0_15_W_0_54_tmp = INTERNAL phighvt_L_0_15 == 0.54 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_54 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_54_tmp |
| phighvt_L_0_15_W_0_55_tmp = INTERNAL phighvt_L_0_15 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_55 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_55_tmp |
| phighvt_L_0_15_W_0_63_tmp = INTERNAL phighvt_L_0_15 == 0.63 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_63 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_63_tmp |
| phighvt_L_0_15_W_0_64_tmp = INTERNAL phighvt_L_0_15 == 0.64 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_64 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_64_tmp |
| phighvt_L_0_15_W_0_70_tmp = INTERNAL phighvt_L_0_15 == 0.7 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_70 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_70_tmp |
| phighvt_L_0_15_W_0_75_tmp = INTERNAL phighvt_L_0_15 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_75 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_75_tmp |
| phighvt_L_0_15_W_0_79_tmp = INTERNAL phighvt_L_0_15 == 0.79 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_79 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_79_tmp |
| phighvt_L_0_15_W_0_82_tmp = INTERNAL phighvt_L_0_15 == 0.82 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_82 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_82_tmp |
| phighvt_L_0_15_W_0_84_tmp = INTERNAL phighvt_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_84 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_84_tmp |
| phighvt_L_0_15_W_0_86_tmp = INTERNAL phighvt_L_0_15 == 0.86 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_86 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_86_tmp |
| phighvt_L_0_15_W_0_94_tmp = INTERNAL phighvt_L_0_15 == 0.94 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_0_94 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_0_94_tmp |
| phighvt_L_0_15_W_1_00_tmp = INTERNAL phighvt_L_0_15 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_1_00_tmp |
| phighvt_L_0_15_W_1_12_tmp = INTERNAL phighvt_L_0_15 == 1.12 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_1_12 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_1_12_tmp |
| phighvt_L_0_15_W_1_26_tmp = INTERNAL phighvt_L_0_15 == 1.26 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_1_26 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_1_26_tmp |
| phighvt_L_0_15_W_1_65_tmp = INTERNAL phighvt_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_1_65 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_1_65_tmp |
| phighvt_L_0_15_W_1_68_tmp = INTERNAL phighvt_L_0_15 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_1_68 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_1_68_tmp |
| phighvt_L_0_15_W_2_00_tmp = INTERNAL phighvt_L_0_15 == 2.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_2_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_2_00_tmp |
| phighvt_L_0_15_W_3_00_tmp = INTERNAL phighvt_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_3_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_3_00_tmp |
| phighvt_L_0_15_W_5_00_tmp = INTERNAL phighvt_L_0_15 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_5_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_5_00_tmp |
| phighvt_L_0_15_W_7_00_tmp = INTERNAL phighvt_L_0_15 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_15_W_7_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_15_W_7_00_tmp |
| phighvt_L_0_18 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_108_phighvt_L_0_18" { |
| @ keep: phighvt_L_0_18 - phighvt_L_0_18 |
| COPY phighvt_L_0_18 |
| } |
| phighvt_L_0_18_W_0_42_tmp = INTERNAL phighvt_L_0_18 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_0_42_tmp |
| phighvt_L_0_18_W_0_64_tmp = INTERNAL phighvt_L_0_18 == 0.64 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_64 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_0_64_tmp |
| phighvt_L_0_18_W_0_82_tmp = INTERNAL phighvt_L_0_18 == 0.82 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_82 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_0_82_tmp |
| phighvt_L_0_18_W_0_84_tmp = INTERNAL phighvt_L_0_18 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_0_84 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_0_84_tmp |
| phighvt_L_0_18_W_1_00_tmp = INTERNAL phighvt_L_0_18 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_1_00_tmp |
| phighvt_L_0_18_W_1_68_tmp = INTERNAL phighvt_L_0_18 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_1_68 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_1_68_tmp |
| phighvt_L_0_18_W_3_0_tmp = INTERNAL phighvt_L_0_18 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_3_0 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_3_0_tmp |
| phighvt_L_0_18_W_5_0_tmp = INTERNAL phighvt_L_0_18 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_5_0 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_5_0_tmp |
| phighvt_L_0_18_W_7_0_tmp = INTERNAL phighvt_L_0_18 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_18_W_7_0 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_18_W_7_0_tmp |
| phighvt_L_0_25 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_109_phighvt_L_0_25" { |
| @ keep: phighvt_L_0_25 - phighvt_L_0_25 |
| COPY phighvt_L_0_25 |
| } |
| phighvt_L_0_25_W_0_82_tmp = INTERNAL phighvt_L_0_25 == 0.82 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_25_W_0_82 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_25_W_0_82_tmp |
| phighvt_L_0_25_W_1_00_tmp = INTERNAL phighvt_L_0_25 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_25_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_25_W_1_00_tmp |
| phighvt_L_0_25_W_3_00_tmp = INTERNAL phighvt_L_0_25 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_25_W_3_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_25_W_3_00_tmp |
| phighvt_L_0_25_W_5_00_tmp = INTERNAL phighvt_L_0_25 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_25_W_5_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_25_W_5_00_tmp |
| phighvt_L_0_25_W_7_00_tmp = INTERNAL phighvt_L_0_25 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_25_W_7_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_25_W_7_00_tmp |
| phighvt_L_0_50 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_110_phighvt_L_0_50" { |
| @ keep: phighvt_L_0_50 - phighvt_L_0_50 |
| COPY phighvt_L_0_50 |
| } |
| phighvt_L_0_50_W_0_42_tmp = INTERNAL phighvt_L_0_50 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_50_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_50_W_0_42_tmp |
| phighvt_L_0_50_W_0_55_tmp = INTERNAL phighvt_L_0_50 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_50_W_0_55 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_50_W_0_55_tmp |
| phighvt_L_0_50_W_0_82_tmp = INTERNAL phighvt_L_0_50 == 0.82 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_50_W_0_82 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_50_W_0_82_tmp |
| phighvt_L_0_50_W_1_00_tmp = INTERNAL phighvt_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_50_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_50_W_1_00_tmp |
| phighvt_L_0_50_W_3_00_tmp = INTERNAL phighvt_L_0_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_50_W_3_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_50_W_3_00_tmp |
| phighvt_L_0_50_W_5_00_tmp = INTERNAL phighvt_L_0_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_50_W_5_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_50_W_5_00_tmp |
| phighvt_L_0_50_W_7_00_tmp = INTERNAL phighvt_L_0_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_0_50_W_7_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_0_50_W_7_00_tmp |
| phighvt_L_1_00 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_111_phighvt_L_1_00" { |
| @ keep: phighvt_L_1_00 - phighvt_L_1_00 |
| COPY phighvt_L_1_00 |
| } |
| phighvt_L_1_00_W_0_42_tmp = INTERNAL phighvt_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_1_00_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_1_00_W_0_42_tmp |
| phighvt_L_1_00_W_0_55_tmp = INTERNAL phighvt_L_1_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_1_00_W_0_55 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_1_00_W_0_55_tmp |
| phighvt_L_1_00_W_1_00_tmp = INTERNAL phighvt_L_1_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_1_00_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_1_00_W_1_00_tmp |
| phighvt_L_1_00_W_3_00_tmp = INTERNAL phighvt_L_1_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_1_00_W_3_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_1_00_W_3_00_tmp |
| phighvt_L_1_00_W_5_00_tmp = INTERNAL phighvt_L_1_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_1_00_W_5_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_1_00_W_5_00_tmp |
| phighvt_L_1_00_W_7_00_tmp = INTERNAL phighvt_L_1_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_1_00_W_7_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_1_00_W_7_00_tmp |
| phighvt_L_2_00 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_112_phighvt_L_2_00" { |
| @ keep: phighvt_L_2_00 - phighvt_L_2_00 |
| COPY phighvt_L_2_00 |
| } |
| phighvt_L_2_00_W_0_42_tmp = INTERNAL phighvt_L_2_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_2_00_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_2_00_W_0_42_tmp |
| phighvt_L_2_00_W_0_55_tmp = INTERNAL phighvt_L_2_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_2_00_W_0_55 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_2_00_W_0_55_tmp |
| phighvt_L_2_00_W_1_00_tmp = INTERNAL phighvt_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_2_00_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_2_00_W_1_00_tmp |
| phighvt_L_2_00_W_3_00_tmp = INTERNAL phighvt_L_2_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_2_00_W_3_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_2_00_W_3_00_tmp |
| phighvt_L_2_00_W_5_00_tmp = INTERNAL phighvt_L_2_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_2_00_W_5_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_2_00_W_5_00_tmp |
| phighvt_L_2_00_W_7_00_tmp = INTERNAL phighvt_L_2_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_2_00_W_7_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_2_00_W_7_00_tmp |
| phighvt_L_4_00 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_113_phighvt_L_4_00" { |
| @ keep: phighvt_L_4_00 - phighvt_L_4_00 |
| COPY phighvt_L_4_00 |
| } |
| phighvt_L_4_00_W_0_42_tmp = INTERNAL phighvt_L_4_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_4_00_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_4_00_W_0_42_tmp |
| phighvt_L_4_00_W_0_55_tmp = INTERNAL phighvt_L_4_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_4_00_W_0_55 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_4_00_W_0_55_tmp |
| phighvt_L_4_00_W_1_00_tmp = INTERNAL phighvt_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_4_00_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_4_00_W_1_00_tmp |
| phighvt_L_4_00_W_3_00_tmp = INTERNAL phighvt_L_4_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_4_00_W_3_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_4_00_W_3_00_tmp |
| phighvt_L_4_00_W_5_00_tmp = INTERNAL phighvt_L_4_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_4_00_W_5_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_4_00_W_5_00_tmp |
| phighvt_L_4_00_W_7_00_tmp = INTERNAL phighvt_L_4_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_4_00_W_7_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_4_00_W_7_00_tmp |
| phighvt_L_8_00 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_114_phighvt_L_8_00" { |
| @ keep: phighvt_L_8_00 - phighvt_L_8_00 |
| COPY phighvt_L_8_00 |
| } |
| phighvt_L_8_00_W_0_42_tmp = INTERNAL phighvt_L_8_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_8_00_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_8_00_W_0_42_tmp |
| phighvt_L_8_00_W_0_55_tmp = INTERNAL phighvt_L_8_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_8_00_W_0_55 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_8_00_W_0_55_tmp |
| phighvt_L_8_00_W_1_00_tmp = INTERNAL phighvt_L_8_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_8_00_W_1_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_8_00_W_1_00_tmp |
| phighvt_L_8_00_W_3_00_tmp = INTERNAL phighvt_L_8_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_8_00_W_3_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_8_00_W_3_00_tmp |
| phighvt_L_8_00_W_5_00_tmp = INTERNAL phighvt_L_8_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_8_00_W_5_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_8_00_W_5_00_tmp |
| phighvt_L_8_00_W_7_00_tmp = INTERNAL phighvt_L_8_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_8_00_W_7_00 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_8_00_W_7_00_tmp |
| phighvt_L_20_0 = LENGTH ("phighvt" COINCIDENT INSIDE EDGE diff) == 20.0 |
| "k_115_phighvt_L_20_0" { |
| @ keep: phighvt_L_20_0 - phighvt_L_20_0 |
| COPY phighvt_L_20_0 |
| } |
| phighvt_L_20_0_W_0_42_tmp = INTERNAL phighvt_L_20_0 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| phighvt_L_20_0_W_0_42 = (WITH TEXT "phighvt" "dummy_poly" textlabel) OR phighvt_L_20_0_W_0_42_tmp |
| phighvt_valid = phighvt_L_20_0_W_0_42 OR |
| (phighvt_L_8_00_W_7_00 OR |
| (phighvt_L_8_00_W_5_00 OR |
| (phighvt_L_8_00_W_3_00 OR |
| (phighvt_L_8_00_W_1_00 OR |
| (phighvt_L_8_00_W_0_55 OR |
| (phighvt_L_8_00_W_0_42 OR |
| (phighvt_L_4_00_W_7_00 OR |
| (phighvt_L_4_00_W_5_00 OR |
| (phighvt_L_4_00_W_3_00 OR |
| (phighvt_L_4_00_W_1_00 OR |
| (phighvt_L_4_00_W_0_55 OR |
| (phighvt_L_4_00_W_0_42 OR |
| (phighvt_L_2_00_W_7_00 OR |
| (phighvt_L_2_00_W_5_00 OR |
| (phighvt_L_2_00_W_3_00 OR |
| (phighvt_L_2_00_W_1_00 OR |
| (phighvt_L_2_00_W_0_55 OR |
| (phighvt_L_2_00_W_0_42 OR |
| (phighvt_L_1_00_W_7_00 OR |
| (phighvt_L_1_00_W_5_00 OR |
| (phighvt_L_1_00_W_3_00 OR |
| (phighvt_L_1_00_W_1_00 OR |
| (phighvt_L_1_00_W_0_55 OR |
| (phighvt_L_1_00_W_0_42 OR |
| (phighvt_L_0_50_W_7_00 OR |
| (phighvt_L_0_50_W_5_00 OR |
| (phighvt_L_0_50_W_3_00 OR |
| (phighvt_L_0_50_W_1_00 OR |
| (phighvt_L_0_50_W_0_82 OR |
| (phighvt_L_0_50_W_0_55 OR |
| (phighvt_L_0_50_W_0_42 OR |
| (phighvt_L_0_25_W_7_00 OR |
| (phighvt_L_0_25_W_5_00 OR |
| (phighvt_L_0_25_W_3_00 OR |
| (phighvt_L_0_25_W_1_00 OR |
| (phighvt_L_0_25_W_0_82 OR |
| (phighvt_L_0_18_W_7_0 OR |
| (phighvt_L_0_18_W_5_0 OR |
| (phighvt_L_0_18_W_3_0 OR |
| (phighvt_L_0_18_W_1_68 OR |
| (phighvt_L_0_18_W_1_00 OR |
| (phighvt_L_0_18_W_0_84 OR |
| (phighvt_L_0_18_W_0_82 OR |
| (phighvt_L_0_18_W_0_64 OR |
| (phighvt_L_0_18_W_0_42 OR |
| (phighvt_L_0_15_W_7_00 OR |
| (phighvt_L_0_15_W_5_00 OR |
| (phighvt_L_0_15_W_3_00 OR |
| (phighvt_L_0_15_W_2_00 OR |
| (phighvt_L_0_15_W_1_68 OR |
| (phighvt_L_0_15_W_1_65 OR |
| (phighvt_L_0_15_W_1_26 OR |
| (phighvt_L_0_15_W_1_12 OR |
| (phighvt_L_0_15_W_1_00 OR |
| (phighvt_L_0_15_W_0_94 OR |
| (phighvt_L_0_15_W_0_86 OR |
| (phighvt_L_0_15_W_0_84 OR |
| (phighvt_L_0_15_W_0_82 OR |
| (phighvt_L_0_15_W_0_79 OR |
| (phighvt_L_0_15_W_0_75 OR |
| (phighvt_L_0_15_W_0_70 OR |
| (phighvt_L_0_15_W_0_64 OR |
| (phighvt_L_0_15_W_0_63 OR |
| (phighvt_L_0_15_W_0_55 OR |
| (phighvt_L_0_15_W_0_54 OR |
| (phighvt_L_0_15_W_0_42 OR phighvt_L_0_15_W_0_36)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) |
| "k_116_phighvt_valid" { |
| @ keep: phighvt_valid - phighvt_valid |
| COPY phighvt_valid |
| } |
| phighvt_invalid = phighvt NOT (exemptDecaps OR phighvt_valid) |
| "r_575_Poly.X.1" { |
| @ Poly.X.1: This phighvt device has an invalid W/L. Please see MRGA |
| COPY phighvt_invalid |
| } |
| s8rf_pshort_W3p0_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_pshort_W3p0_L0p18_M2_b") |
| "k_117_s8rf_pshort_W3p0_L0p18_M2_b" { |
| @ keep: s8rf_pshort_W3p0_L0p18_M2_b - s8rf_pshort_W3p0_L0p18_M2_b |
| COPY s8rf_pshort_W3p0_L0p18_M2_b |
| } |
| s8rf_pshort_W3p0_L0p18_M2_b_L_0_18 = LENGTH (s8rf_pshort_W3p0_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_118_s8rf_pshort_W3p0_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_pshort_W3p0_L0p18_M2_b_L_0_18 - s8rf_pshort_W3p0_L0p18_M2_b_L_0_18 |
| COPY s8rf_pshort_W3p0_L0p18_M2_b_L_0_18 |
| } |
| s8rf_pshort_W3p0_L0p18_M2_b_L_0_18_W_3_01_tmp = INTERNAL s8rf_pshort_W3p0_L0p18_M2_b_L_0_18 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pshort_W3p0_L0p18_M2_b_L_0_18_W_3_01 = (WITH TEXT s8rf_pshort_W3p0_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_pshort_W3p0_L0p18_M2_b_L_0_18_W_3_01_tmp |
| s8rf_pshort_W3p0_L0p18_M2_b_valid = COPY s8rf_pshort_W3p0_L0p18_M2_b_L_0_18_W_3_01 |
| "k_119_s8rf_pshort_W3p0_L0p18_M2_b_valid" { |
| @ keep: s8rf_pshort_W3p0_L0p18_M2_b_valid - s8rf_pshort_W3p0_L0p18_M2_b_valid |
| COPY s8rf_pshort_W3p0_L0p18_M2_b_valid |
| } |
| s8rf_pshort_W3p0_L0p18_M2_b_invalid = s8rf_pshort_W3p0_L0p18_M2_b NOT (exemptDecaps OR s8rf_pshort_W3p0_L0p18_M2_b_valid) |
| "r_576_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pshort_W3p0_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_pshort_W3p0_L0p18_M2_b_invalid |
| } |
| s8rf_pmedlvt_W1p68_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_pmedlvt_W1p68_L0p15_2F") |
| "k_120_s8rf_pmedlvt_W1p68_L0p15_2F" { |
| @ keep: s8rf_pmedlvt_W1p68_L0p15_2F - s8rf_pmedlvt_W1p68_L0p15_2F |
| COPY s8rf_pmedlvt_W1p68_L0p15_2F |
| } |
| s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15 = LENGTH (s8rf_pmedlvt_W1p68_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_121_s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15" { |
| @ keep: s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15 - s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15 |
| COPY s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15 |
| } |
| s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15_W_1_68_tmp = INTERNAL s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15_W_1_68 = (WITH TEXT s8rf_pmedlvt_W1p68_L0p15_2F "dummy_poly" textlabel) OR s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15_W_1_68_tmp |
| s8rf_pmedlvt_W1p68_L0p15_2F_valid = COPY s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15_W_1_68 |
| "k_122_s8rf_pmedlvt_W1p68_L0p15_2F_valid" { |
| @ keep: s8rf_pmedlvt_W1p68_L0p15_2F_valid - s8rf_pmedlvt_W1p68_L0p15_2F_valid |
| COPY s8rf_pmedlvt_W1p68_L0p15_2F_valid |
| } |
| s8rf_pmedlvt_W1p68_L0p15_2F_invalid = s8rf_pmedlvt_W1p68_L0p15_2F NOT (exemptDecaps OR s8rf_pmedlvt_W1p68_L0p15_2F_valid) |
| "r_577_Poly.X.1" { |
| @ Poly.X.1: This s8rf_pmedlvt_W1p68_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_pmedlvt_W1p68_L0p15_2F_invalid |
| } |
| s8rf_nlowvt_W0p42_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_nlowvt_W0p42_L0p15_2F") |
| "k_123_s8rf_nlowvt_W0p42_L0p15_2F" { |
| @ keep: s8rf_nlowvt_W0p42_L0p15_2F - s8rf_nlowvt_W0p42_L0p15_2F |
| COPY s8rf_nlowvt_W0p42_L0p15_2F |
| } |
| s8rf_nlowvt_W0p42_L0p15_2F_L_0_15 = LENGTH (s8rf_nlowvt_W0p42_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_124_s8rf_nlowvt_W0p42_L0p15_2F_L_0_15" { |
| @ keep: s8rf_nlowvt_W0p42_L0p15_2F_L_0_15 - s8rf_nlowvt_W0p42_L0p15_2F_L_0_15 |
| COPY s8rf_nlowvt_W0p42_L0p15_2F_L_0_15 |
| } |
| s8rf_nlowvt_W0p42_L0p15_2F_L_0_15_W_0_42_tmp = INTERNAL s8rf_nlowvt_W0p42_L0p15_2F_L_0_15 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W0p42_L0p15_2F_L_0_15_W_0_42 = (WITH TEXT s8rf_nlowvt_W0p42_L0p15_2F "dummy_poly" textlabel) OR s8rf_nlowvt_W0p42_L0p15_2F_L_0_15_W_0_42_tmp |
| s8rf_nlowvt_W0p42_L0p15_2F_valid = COPY s8rf_nlowvt_W0p42_L0p15_2F_L_0_15_W_0_42 |
| "k_125_s8rf_nlowvt_W0p42_L0p15_2F_valid" { |
| @ keep: s8rf_nlowvt_W0p42_L0p15_2F_valid - s8rf_nlowvt_W0p42_L0p15_2F_valid |
| COPY s8rf_nlowvt_W0p42_L0p15_2F_valid |
| } |
| s8rf_nlowvt_W0p42_L0p15_2F_invalid = s8rf_nlowvt_W0p42_L0p15_2F NOT (exemptDecaps OR s8rf_nlowvt_W0p42_L0p15_2F_valid) |
| "r_578_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W0p42_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W0p42_L0p15_2F_invalid |
| } |
| s8rf_nlowvt_W0p84_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_nlowvt_W0p84_L0p15_2F") |
| "k_126_s8rf_nlowvt_W0p84_L0p15_2F" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_2F - s8rf_nlowvt_W0p84_L0p15_2F |
| COPY s8rf_nlowvt_W0p84_L0p15_2F |
| } |
| s8rf_nlowvt_W0p84_L0p15_2F_L_0_15 = LENGTH (s8rf_nlowvt_W0p84_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_127_s8rf_nlowvt_W0p84_L0p15_2F_L_0_15" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_2F_L_0_15 - s8rf_nlowvt_W0p84_L0p15_2F_L_0_15 |
| COPY s8rf_nlowvt_W0p84_L0p15_2F_L_0_15 |
| } |
| s8rf_nlowvt_W0p84_L0p15_2F_L_0_15_W_0_84_tmp = INTERNAL s8rf_nlowvt_W0p84_L0p15_2F_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W0p84_L0p15_2F_L_0_15_W_0_84 = (WITH TEXT s8rf_nlowvt_W0p84_L0p15_2F "dummy_poly" textlabel) OR s8rf_nlowvt_W0p84_L0p15_2F_L_0_15_W_0_84_tmp |
| s8rf_nlowvt_W0p84_L0p15_2F_valid = COPY s8rf_nlowvt_W0p84_L0p15_2F_L_0_15_W_0_84 |
| "k_128_s8rf_nlowvt_W0p84_L0p15_2F_valid" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_2F_valid - s8rf_nlowvt_W0p84_L0p15_2F_valid |
| COPY s8rf_nlowvt_W0p84_L0p15_2F_valid |
| } |
| s8rf_nlowvt_W0p84_L0p15_2F_invalid = s8rf_nlowvt_W0p84_L0p15_2F NOT (exemptDecaps OR s8rf_nlowvt_W0p84_L0p15_2F_valid) |
| "r_579_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W0p84_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W0p84_L0p15_2F_invalid |
| } |
| s8rf_nhv_W7p0_L0p5_M10_b = rfGate AND (EXTENT CELL "s8rf_nhv_W7p0_L0p5_M10_b") |
| "k_129_s8rf_nhv_W7p0_L0p5_M10_b" { |
| @ keep: s8rf_nhv_W7p0_L0p5_M10_b - s8rf_nhv_W7p0_L0p5_M10_b |
| COPY s8rf_nhv_W7p0_L0p5_M10_b |
| } |
| s8rf_nhv_W7p0_L0p5_M10_b_L_0_50 = LENGTH (s8rf_nhv_W7p0_L0p5_M10_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_130_s8rf_nhv_W7p0_L0p5_M10_b_L_0_50" { |
| @ keep: s8rf_nhv_W7p0_L0p5_M10_b_L_0_50 - s8rf_nhv_W7p0_L0p5_M10_b_L_0_50 |
| COPY s8rf_nhv_W7p0_L0p5_M10_b_L_0_50 |
| } |
| s8rf_nhv_W7p0_L0p5_M10_b_L_0_50_W_7_09_tmp = INTERNAL s8rf_nhv_W7p0_L0p5_M10_b_L_0_50 == 7.09 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W7p0_L0p5_M10_b_L_0_50_W_7_09 = (WITH TEXT s8rf_nhv_W7p0_L0p5_M10_b "dummy_poly" textlabel) OR s8rf_nhv_W7p0_L0p5_M10_b_L_0_50_W_7_09_tmp |
| s8rf_nhv_W7p0_L0p5_M10_b_valid = COPY s8rf_nhv_W7p0_L0p5_M10_b_L_0_50_W_7_09 |
| "k_131_s8rf_nhv_W7p0_L0p5_M10_b_valid" { |
| @ keep: s8rf_nhv_W7p0_L0p5_M10_b_valid - s8rf_nhv_W7p0_L0p5_M10_b_valid |
| COPY s8rf_nhv_W7p0_L0p5_M10_b_valid |
| } |
| s8rf_nhv_W7p0_L0p5_M10_b_invalid = s8rf_nhv_W7p0_L0p5_M10_b NOT (exemptDecaps OR s8rf_nhv_W7p0_L0p5_M10_b_valid) |
| "r_580_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W7p0_L0p5_M10_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W7p0_L0p5_M10_b_invalid |
| } |
| nhvnative_L_0_90 = LENGTH ("nhvnative" COINCIDENT INSIDE EDGE diff) == 0.9 |
| "k_132_nhvnative_L_0_90" { |
| @ keep: nhvnative_L_0_90 - nhvnative_L_0_90 |
| COPY nhvnative_L_0_90 |
| } |
| nhvnative_L_0_90_W_0_42_tmp = INTERNAL nhvnative_L_0_90 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_0_90_W_0_42 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_0_90_W_0_42_tmp |
| nhvnative_L_0_90_W_0_70_tmp = INTERNAL nhvnative_L_0_90 == 0.7 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_0_90_W_0_70 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_0_90_W_0_70_tmp |
| nhvnative_L_0_90_W_1_00_tmp = INTERNAL nhvnative_L_0_90 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_0_90_W_1_00 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_0_90_W_1_00_tmp |
| nhvnative_L_0_90_W_10_0_tmp = INTERNAL nhvnative_L_0_90 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_0_90_W_10_0 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_0_90_W_10_0_tmp |
| nhvnative_L_1_00 = LENGTH ("nhvnative" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_133_nhvnative_L_1_00" { |
| @ keep: nhvnative_L_1_00 - nhvnative_L_1_00 |
| COPY nhvnative_L_1_00 |
| } |
| nhvnative_L_1_00_W_0_42_tmp = INTERNAL nhvnative_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_1_00_W_0_42 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_1_00_W_0_42_tmp |
| nhvnative_L_2_00 = LENGTH ("nhvnative" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_134_nhvnative_L_2_00" { |
| @ keep: nhvnative_L_2_00 - nhvnative_L_2_00 |
| COPY nhvnative_L_2_00 |
| } |
| nhvnative_L_2_00_W_1_00_tmp = INTERNAL nhvnative_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_2_00_W_1_00 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_2_00_W_1_00_tmp |
| nhvnative_L_2_00_W_10_0_tmp = INTERNAL nhvnative_L_2_00 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_2_00_W_10_0 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_2_00_W_10_0_tmp |
| nhvnative_L_4_00 = LENGTH ("nhvnative" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_135_nhvnative_L_4_00" { |
| @ keep: nhvnative_L_4_00 - nhvnative_L_4_00 |
| COPY nhvnative_L_4_00 |
| } |
| nhvnative_L_4_00_W_1_00_tmp = INTERNAL nhvnative_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_4_00_W_1_00 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_4_00_W_1_00_tmp |
| nhvnative_L_4_00_W_10_0_tmp = INTERNAL nhvnative_L_4_00 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_4_00_W_10_0 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_4_00_W_10_0_tmp |
| nhvnative_L_8_00 = LENGTH ("nhvnative" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_136_nhvnative_L_8_00" { |
| @ keep: nhvnative_L_8_00 - nhvnative_L_8_00 |
| COPY nhvnative_L_8_00 |
| } |
| nhvnative_L_8_00_W_1_00_tmp = INTERNAL nhvnative_L_8_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_8_00_W_1_00 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_8_00_W_1_00_tmp |
| nhvnative_L_25_00 = LENGTH ("nhvnative" COINCIDENT INSIDE EDGE diff) == 25.0 |
| "k_137_nhvnative_L_25_00" { |
| @ keep: nhvnative_L_25_00 - nhvnative_L_25_00 |
| COPY nhvnative_L_25_00 |
| } |
| nhvnative_L_25_00_W_1_00_tmp = INTERNAL nhvnative_L_25_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnative_L_25_00_W_1_00 = (WITH TEXT "nhvnative" "dummy_poly" textlabel) OR nhvnative_L_25_00_W_1_00_tmp |
| nhvnative_valid = nhvnative_L_25_00_W_1_00 OR |
| (nhvnative_L_8_00_W_1_00 OR |
| (nhvnative_L_4_00_W_10_0 OR |
| (nhvnative_L_4_00_W_1_00 OR |
| (nhvnative_L_2_00_W_10_0 OR |
| (nhvnative_L_2_00_W_1_00 OR |
| (nhvnative_L_1_00_W_0_42 OR |
| (nhvnative_L_0_90_W_10_0 OR |
| (nhvnative_L_0_90_W_1_00 OR |
| (nhvnative_L_0_90_W_0_70 OR nhvnative_L_0_90_W_0_42))))))))) |
| "k_138_nhvnative_valid" { |
| @ keep: nhvnative_valid - nhvnative_valid |
| COPY nhvnative_valid |
| } |
| nhvnative_invalid = nhvnative NOT (exemptDecaps OR nhvnative_valid) |
| "r_581_Poly.X.1" { |
| @ Poly.X.1: This nhvnative device has an invalid W/L. Please see MRGA |
| COPY nhvnative_invalid |
| } |
| s8rf_nshort_W5p0_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W5p0_L0p25_M4_b") |
| "k_139_s8rf_nshort_W5p0_L0p25_M4_b" { |
| @ keep: s8rf_nshort_W5p0_L0p25_M4_b - s8rf_nshort_W5p0_L0p25_M4_b |
| COPY s8rf_nshort_W5p0_L0p25_M4_b |
| } |
| s8rf_nshort_W5p0_L0p25_M4_b_L_0_25 = LENGTH (s8rf_nshort_W5p0_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_140_s8rf_nshort_W5p0_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_nshort_W5p0_L0p25_M4_b_L_0_25 - s8rf_nshort_W5p0_L0p25_M4_b_L_0_25 |
| COPY s8rf_nshort_W5p0_L0p25_M4_b_L_0_25 |
| } |
| s8rf_nshort_W5p0_L0p25_M4_b_L_0_25_W_5_05_tmp = INTERNAL s8rf_nshort_W5p0_L0p25_M4_b_L_0_25 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W5p0_L0p25_M4_b_L_0_25_W_5_05 = (WITH TEXT s8rf_nshort_W5p0_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W5p0_L0p25_M4_b_L_0_25_W_5_05_tmp |
| s8rf_nshort_W5p0_L0p25_M4_b_valid = COPY s8rf_nshort_W5p0_L0p25_M4_b_L_0_25_W_5_05 |
| "k_141_s8rf_nshort_W5p0_L0p25_M4_b_valid" { |
| @ keep: s8rf_nshort_W5p0_L0p25_M4_b_valid - s8rf_nshort_W5p0_L0p25_M4_b_valid |
| COPY s8rf_nshort_W5p0_L0p25_M4_b_valid |
| } |
| s8rf_nshort_W5p0_L0p25_M4_b_invalid = s8rf_nshort_W5p0_L0p25_M4_b NOT (exemptDecaps OR s8rf_nshort_W5p0_L0p25_M4_b_valid) |
| "r_582_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W5p0_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W5p0_L0p25_M4_b_invalid |
| } |
| npass_L_0_15 = LENGTH ("npass" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_142_npass_L_0_15" { |
| @ keep: npass_L_0_15 - npass_L_0_15 |
| COPY npass_L_0_15 |
| } |
| npass_L_0_15_W_0_14_tmp = INTERNAL npass_L_0_15 == 0.14 OPPOSITE PARALLEL ONLY REGION |
| npass_L_0_15_W_0_14 = (WITH TEXT "npass" "dummy_poly" textlabel) OR npass_L_0_15_W_0_14_tmp |
| npass_valid = COPY npass_L_0_15_W_0_14 |
| "k_143_npass_valid" { |
| @ keep: npass_valid - npass_valid |
| COPY npass_valid |
| } |
| npass_invalid = npass NOT (exemptDecaps OR npass_valid) |
| "r_583_Poly.X.1" { |
| @ Poly.X.1: This npass device has an invalid W/L. Please see MRGA |
| COPY npass_invalid |
| } |
| s8rf_nlowvt_W1p65_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W1p65_L0p15_M2_b") |
| "k_144_s8rf_nlowvt_W1p65_L0p15_M2_b" { |
| @ keep: s8rf_nlowvt_W1p65_L0p15_M2_b - s8rf_nlowvt_W1p65_L0p15_M2_b |
| COPY s8rf_nlowvt_W1p65_L0p15_M2_b |
| } |
| s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15 = LENGTH (s8rf_nlowvt_W1p65_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_145_s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15 - s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15 |
| COPY s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15 |
| } |
| s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15_W_1_65_tmp = INTERNAL s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15_W_1_65 = (WITH TEXT s8rf_nlowvt_W1p65_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15_W_1_65_tmp |
| s8rf_nlowvt_W1p65_L0p15_M2_b_valid = COPY s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15_W_1_65 |
| "k_146_s8rf_nlowvt_W1p65_L0p15_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W1p65_L0p15_M2_b_valid - s8rf_nlowvt_W1p65_L0p15_M2_b_valid |
| COPY s8rf_nlowvt_W1p65_L0p15_M2_b_valid |
| } |
| s8rf_nlowvt_W1p65_L0p15_M2_b_invalid = s8rf_nlowvt_W1p65_L0p15_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W1p65_L0p15_M2_b_valid) |
| "r_584_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W1p65_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W1p65_L0p15_M2_b_invalid |
| } |
| s8rf_nhv_W3p0_L0p5_M10_b = rfGate AND (EXTENT CELL "s8rf_nhv_W3p0_L0p5_M10_b") |
| "k_147_s8rf_nhv_W3p0_L0p5_M10_b" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M10_b - s8rf_nhv_W3p0_L0p5_M10_b |
| COPY s8rf_nhv_W3p0_L0p5_M10_b |
| } |
| s8rf_nhv_W3p0_L0p5_M10_b_L_0_50 = LENGTH (s8rf_nhv_W3p0_L0p5_M10_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_148_s8rf_nhv_W3p0_L0p5_M10_b_L_0_50" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M10_b_L_0_50 - s8rf_nhv_W3p0_L0p5_M10_b_L_0_50 |
| COPY s8rf_nhv_W3p0_L0p5_M10_b_L_0_50 |
| } |
| s8rf_nhv_W3p0_L0p5_M10_b_L_0_50_W_3_01_tmp = INTERNAL s8rf_nhv_W3p0_L0p5_M10_b_L_0_50 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W3p0_L0p5_M10_b_L_0_50_W_3_01 = (WITH TEXT s8rf_nhv_W3p0_L0p5_M10_b "dummy_poly" textlabel) OR s8rf_nhv_W3p0_L0p5_M10_b_L_0_50_W_3_01_tmp |
| s8rf_nhv_W3p0_L0p5_M10_b_valid = COPY s8rf_nhv_W3p0_L0p5_M10_b_L_0_50_W_3_01 |
| "k_149_s8rf_nhv_W3p0_L0p5_M10_b_valid" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M10_b_valid - s8rf_nhv_W3p0_L0p5_M10_b_valid |
| COPY s8rf_nhv_W3p0_L0p5_M10_b_valid |
| } |
| s8rf_nhv_W3p0_L0p5_M10_b_invalid = s8rf_nhv_W3p0_L0p5_M10_b NOT (exemptDecaps OR s8rf_nhv_W3p0_L0p5_M10_b_valid) |
| "r_585_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W3p0_L0p5_M10_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W3p0_L0p5_M10_b_invalid |
| } |
| |
| //sonos_p_L_0_15 = LENGTH ("sonos_p" COINCIDENT INSIDE EDGE diff) == 0.15 |
| //"k_150_sonos_p_L_0_15" { |
| // @ keep: sonos_p_L_0_15 - sonos_p_L_0_15 |
| // COPY sonos_p_L_0_15 |
| // } |
| //sonos_p_L_0_15_W_0_35_tmp = INTERNAL sonos_p_L_0_15 == 0.35 OPPOSITE PARALLEL ONLY REGION |
| //sonos_p_L_0_15_W_0_35 = (WITH TEXT "sonos_p" "dummy_poly" textlabel) OR sonos_p_L_0_15_W_0_35_tmp |
| |
| |
| sonos_p_L_0_22 = LENGTH ("sonos_p" COINCIDENT INSIDE EDGE diff) == 0.22 |
| "k_150_sonos_p_L_0_22" { |
| @ keep: sonos_p_L_0_22 - sonos_p_L_0_22 |
| COPY sonos_p_L_0_22 |
| } |
| sonos_p_L_0_22_W_0_45_tmp = INTERNAL sonos_p_L_0_22 == 0.45 OPPOSITE PARALLEL ONLY REGION |
| sonos_p_L_0_22_W_0_45 = (WITH TEXT "sonos_p" "dummy_poly" textlabel) OR sonos_p_L_0_22_W_0_45_tmp |
| |
| sonos_p_L_0_50 = LENGTH ("sonos_p" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_151_sonos_p_L_0_50" { |
| @ keep: sonos_p_L_0_50 - sonos_p_L_0_50 |
| COPY sonos_p_L_0_50 |
| } |
| sonos_p_L_0_50_W_1_00_tmp = INTERNAL sonos_p_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| sonos_p_L_0_50_W_1_00 = (WITH TEXT "sonos_p" "dummy_poly" textlabel) OR sonos_p_L_0_50_W_1_00_tmp |
| sonos_p_valid = sonos_p_L_0_50_W_1_00 OR sonos_p_L_0_22_W_0_45 |
| "k_152_sonos_p_valid" { |
| @ keep: sonos_p_valid - sonos_p_valid |
| COPY sonos_p_valid |
| } |
| sonos_p_invalid = sonos_p NOT (exemptDecaps OR sonos_p_valid) |
| "r_586_Poly.X.1" { |
| @ Poly.X.1: This sonos_p device has an invalid W/L. Please see MRGA |
| COPY sonos_p_invalid |
| } |
| nhvnativeesd_L_0_90 = LENGTH ("nhvnativeesd" COINCIDENT INSIDE EDGE diff) == 0.9 |
| "k_153_nhvnativeesd_L_0_90" { |
| @ keep: nhvnativeesd_L_0_90 - nhvnativeesd_L_0_90 |
| COPY nhvnativeesd_L_0_90 |
| } |
| nhvnativeesd_L_0_90_W_10_0_tmp = INTERNAL nhvnativeesd_L_0_90 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnativeesd_L_0_90_W_10_0 = (WITH TEXT "nhvnativeesd" "dummy_poly" textlabel) OR nhvnativeesd_L_0_90_W_10_0_tmp |
| nhvnativeesd_L_2_00 = LENGTH ("nhvnativeesd" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_154_nhvnativeesd_L_2_00" { |
| @ keep: nhvnativeesd_L_2_00 - nhvnativeesd_L_2_00 |
| COPY nhvnativeesd_L_2_00 |
| } |
| nhvnativeesd_L_2_00_W_10_0_tmp = INTERNAL nhvnativeesd_L_2_00 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnativeesd_L_2_00_W_10_0 = (WITH TEXT "nhvnativeesd" "dummy_poly" textlabel) OR nhvnativeesd_L_2_00_W_10_0_tmp |
| nhvnativeesd_L_4_00 = LENGTH ("nhvnativeesd" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_155_nhvnativeesd_L_4_00" { |
| @ keep: nhvnativeesd_L_4_00 - nhvnativeesd_L_4_00 |
| COPY nhvnativeesd_L_4_00 |
| } |
| nhvnativeesd_L_4_00_W_10_0_tmp = INTERNAL nhvnativeesd_L_4_00 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| nhvnativeesd_L_4_00_W_10_0 = (WITH TEXT "nhvnativeesd" "dummy_poly" textlabel) OR nhvnativeesd_L_4_00_W_10_0_tmp |
| nhvnativeesd_valid = nhvnativeesd_L_4_00_W_10_0 OR |
| (nhvnativeesd_L_2_00_W_10_0 OR nhvnativeesd_L_0_90_W_10_0) |
| "k_156_nhvnativeesd_valid" { |
| @ keep: nhvnativeesd_valid - nhvnativeesd_valid |
| COPY nhvnativeesd_valid |
| } |
| nhvnativeesd_invalid = nhvnativeesd NOT (exemptDecaps OR nhvnativeesd_valid) |
| "r_587_Poly.X.1" { |
| @ Poly.X.1: This nhvnativeesd device has an invalid W/L. Please see MRGA |
| COPY nhvnativeesd_invalid |
| } |
| npd_L_0_15 = LENGTH ("npd" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_157_npd_L_0_15" { |
| @ keep: npd_L_0_15 - npd_L_0_15 |
| COPY npd_L_0_15 |
| } |
| npd_L_0_15_W_0_21_tmp = INTERNAL npd_L_0_15 == 0.21 OPPOSITE PARALLEL ONLY REGION |
| npd_L_0_15_W_0_21 = (WITH TEXT "npd" "dummy_poly" textlabel) OR npd_L_0_15_W_0_21_tmp |
| npd_valid = COPY npd_L_0_15_W_0_21 |
| "k_158_npd_valid" { |
| @ keep: npd_valid - npd_valid |
| COPY npd_valid |
| } |
| npd_invalid = npd NOT (exemptDecaps OR npd_valid) |
| "r_588_Poly.X.1" { |
| @ Poly.X.1: This npd device has an invalid W/L. Please see MRGA |
| COPY npd_invalid |
| } |
| ntvnative_L_0_50 = LENGTH ("ntvnative" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_159_ntvnative_L_0_50" { |
| @ keep: ntvnative_L_0_50 - ntvnative_L_0_50 |
| COPY ntvnative_L_0_50 |
| } |
| ntvnative_L_0_50_W_0_42_tmp = INTERNAL ntvnative_L_0_50 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_50_W_0_42 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_50_W_0_42_tmp |
| ntvnative_L_0_50_W_0_70_tmp = INTERNAL ntvnative_L_0_50 == 0.7 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_50_W_0_70 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_50_W_0_70_tmp |
| ntvnative_L_0_50_W_1_00_tmp = INTERNAL ntvnative_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_50_W_1_00 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_50_W_1_00_tmp |
| ntvnative_L_0_50_W_4_00_tmp = INTERNAL ntvnative_L_0_50 == 4.0 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_50_W_4_00 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_50_W_4_00_tmp |
| ntvnative_L_0_50_W_10_0_tmp = INTERNAL ntvnative_L_0_50 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_50_W_10_0 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_50_W_10_0_tmp |
| ntvnative_L_0_60 = LENGTH ("ntvnative" COINCIDENT INSIDE EDGE diff) == 0.6 |
| "k_160_ntvnative_L_0_60" { |
| @ keep: ntvnative_L_0_60 - ntvnative_L_0_60 |
| COPY ntvnative_L_0_60 |
| } |
| ntvnative_L_0_60_W_0_42_tmp = INTERNAL ntvnative_L_0_60 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_60_W_0_42 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_60_W_0_42_tmp |
| ntvnative_L_0_60_W_0_70_tmp = INTERNAL ntvnative_L_0_60 == 0.7 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_60_W_0_70 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_60_W_0_70_tmp |
| ntvnative_L_0_60_W_1_00_tmp = INTERNAL ntvnative_L_0_60 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_60_W_1_00 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_60_W_1_00_tmp |
| ntvnative_L_0_80 = LENGTH ("ntvnative" COINCIDENT INSIDE EDGE diff) == 0.8 |
| "k_161_ntvnative_L_0_80" { |
| @ keep: ntvnative_L_0_80 - ntvnative_L_0_80 |
| COPY ntvnative_L_0_80 |
| } |
| ntvnative_L_0_80_W_0_42_tmp = INTERNAL ntvnative_L_0_80 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| ntvnative_L_0_80_W_0_42 = (WITH TEXT "ntvnative" "dummy_poly" textlabel) OR ntvnative_L_0_80_W_0_42_tmp |
| ntvnative_valid = ntvnative_L_0_80_W_0_42 OR |
| (ntvnative_L_0_60_W_1_00 OR |
| (ntvnative_L_0_60_W_0_70 OR |
| (ntvnative_L_0_60_W_0_42 OR |
| (ntvnative_L_0_50_W_10_0 OR |
| (ntvnative_L_0_50_W_4_00 OR |
| (ntvnative_L_0_50_W_1_00 OR |
| (ntvnative_L_0_50_W_0_70 OR ntvnative_L_0_50_W_0_42))))))) |
| "k_162_ntvnative_valid" { |
| @ keep: ntvnative_valid - ntvnative_valid |
| COPY ntvnative_valid |
| } |
| ntvnative_invalid = ntvnative NOT (exemptDecaps OR ntvnative_valid) |
| "r_589_Poly.X.1" { |
| @ Poly.X.1: This ntvnative device has an invalid W/L. Please see MRGA |
| COPY ntvnative_invalid |
| } |
| s8rf_nhv_W5p0_L0p5_M4_b = rfGate AND (EXTENT CELL "s8rf_nhv_W5p0_L0p5_M4_b") |
| "k_163_s8rf_nhv_W5p0_L0p5_M4_b" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M4_b - s8rf_nhv_W5p0_L0p5_M4_b |
| COPY s8rf_nhv_W5p0_L0p5_M4_b |
| } |
| s8rf_nhv_W5p0_L0p5_M4_b_L_0_50 = LENGTH (s8rf_nhv_W5p0_L0p5_M4_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_164_s8rf_nhv_W5p0_L0p5_M4_b_L_0_50" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M4_b_L_0_50 - s8rf_nhv_W5p0_L0p5_M4_b_L_0_50 |
| COPY s8rf_nhv_W5p0_L0p5_M4_b_L_0_50 |
| } |
| s8rf_nhv_W5p0_L0p5_M4_b_L_0_50_W_5_05_tmp = INTERNAL s8rf_nhv_W5p0_L0p5_M4_b_L_0_50 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W5p0_L0p5_M4_b_L_0_50_W_5_05 = (WITH TEXT s8rf_nhv_W5p0_L0p5_M4_b "dummy_poly" textlabel) OR s8rf_nhv_W5p0_L0p5_M4_b_L_0_50_W_5_05_tmp |
| s8rf_nhv_W5p0_L0p5_M4_b_valid = COPY s8rf_nhv_W5p0_L0p5_M4_b_L_0_50_W_5_05 |
| "k_165_s8rf_nhv_W5p0_L0p5_M4_b_valid" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M4_b_valid - s8rf_nhv_W5p0_L0p5_M4_b_valid |
| COPY s8rf_nhv_W5p0_L0p5_M4_b_valid |
| } |
| s8rf_nhv_W5p0_L0p5_M4_b_invalid = s8rf_nhv_W5p0_L0p5_M4_b NOT (exemptDecaps OR s8rf_nhv_W5p0_L0p5_M4_b_valid) |
| "r_590_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W5p0_L0p5_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W5p0_L0p5_M4_b_invalid |
| } |
| s8rf_nshort_W1p65_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W1p65_L0p18_M4_b") |
| "k_166_s8rf_nshort_W1p65_L0p18_M4_b" { |
| @ keep: s8rf_nshort_W1p65_L0p18_M4_b - s8rf_nshort_W1p65_L0p18_M4_b |
| COPY s8rf_nshort_W1p65_L0p18_M4_b |
| } |
| s8rf_nshort_W1p65_L0p18_M4_b_L_0_18 = LENGTH (s8rf_nshort_W1p65_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_167_s8rf_nshort_W1p65_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_nshort_W1p65_L0p18_M4_b_L_0_18 - s8rf_nshort_W1p65_L0p18_M4_b_L_0_18 |
| COPY s8rf_nshort_W1p65_L0p18_M4_b_L_0_18 |
| } |
| s8rf_nshort_W1p65_L0p18_M4_b_L_0_18_W_1_65_tmp = INTERNAL s8rf_nshort_W1p65_L0p18_M4_b_L_0_18 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W1p65_L0p18_M4_b_L_0_18_W_1_65 = (WITH TEXT s8rf_nshort_W1p65_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W1p65_L0p18_M4_b_L_0_18_W_1_65_tmp |
| s8rf_nshort_W1p65_L0p18_M4_b_valid = COPY s8rf_nshort_W1p65_L0p18_M4_b_L_0_18_W_1_65 |
| "k_168_s8rf_nshort_W1p65_L0p18_M4_b_valid" { |
| @ keep: s8rf_nshort_W1p65_L0p18_M4_b_valid - s8rf_nshort_W1p65_L0p18_M4_b_valid |
| COPY s8rf_nshort_W1p65_L0p18_M4_b_valid |
| } |
| s8rf_nshort_W1p65_L0p18_M4_b_invalid = s8rf_nshort_W1p65_L0p18_M4_b NOT (exemptDecaps OR s8rf_nshort_W1p65_L0p18_M4_b_valid) |
| "r_591_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W1p65_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W1p65_L0p18_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p15_4F = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p15_4F") |
| "k_169_s8rf_nlowvt_W3p0_L0p15_4F" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_4F - s8rf_nlowvt_W3p0_L0p15_4F |
| COPY s8rf_nlowvt_W3p0_L0p15_4F |
| } |
| s8rf_nlowvt_W3p0_L0p15_4F_L_0_15 = LENGTH (s8rf_nlowvt_W3p0_L0p15_4F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_170_s8rf_nlowvt_W3p0_L0p15_4F_L_0_15" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_4F_L_0_15 - s8rf_nlowvt_W3p0_L0p15_4F_L_0_15 |
| COPY s8rf_nlowvt_W3p0_L0p15_4F_L_0_15 |
| } |
| s8rf_nlowvt_W3p0_L0p15_4F_L_0_15_W_3_00_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p15_4F_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p15_4F_L_0_15_W_3_00 = (WITH TEXT s8rf_nlowvt_W3p0_L0p15_4F "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p15_4F_L_0_15_W_3_00_tmp |
| s8rf_nlowvt_W3p0_L0p15_4F_valid = COPY s8rf_nlowvt_W3p0_L0p15_4F_L_0_15_W_3_00 |
| "k_171_s8rf_nlowvt_W3p0_L0p15_4F_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_4F_valid - s8rf_nlowvt_W3p0_L0p15_4F_valid |
| COPY s8rf_nlowvt_W3p0_L0p15_4F_valid |
| } |
| s8rf_nlowvt_W3p0_L0p15_4F_invalid = s8rf_nlowvt_W3p0_L0p15_4F NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p15_4F_valid) |
| "r_592_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p15_4F device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p15_4F_invalid |
| } |
| fnpass_L_0_15 = LENGTH ("fnpass" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_172_fnpass_L_0_15" { |
| @ keep: fnpass_L_0_15 - fnpass_L_0_15 |
| COPY fnpass_L_0_15 |
| } |
| //fnpass_L_0_15_W_0_35_tmp = INTERNAL fnpass_L_0_15 == 0.35 OPPOSITE PARALLEL ONLY REGION |
| //fnpass_L_0_15_W_0_35 = (WITH TEXT "fnpass" "dummy_poly" textlabel) OR fnpass_L_0_15_W_0_35_tmp |
| fnpass_L_0_15_W_0_45_tmp = INTERNAL fnpass_L_0_15 == 0.45 OPPOSITE PARALLEL ONLY REGION |
| fnpass_L_0_15_W_0_45 = (WITH TEXT "fnpass" "dummy_poly" textlabel) OR fnpass_L_0_15_W_0_45_tmp |
| fnpass_valid = COPY fnpass_L_0_15_W_0_45 |
| "k_173_fnpass_valid" { |
| @ keep: fnpass_valid - fnpass_valid |
| COPY fnpass_valid |
| } |
| fnpass_invalid = fnpass NOT (exemptDecaps OR fnpass_valid) |
| "r_593_Poly.X.1" { |
| @ Poly.X.1: This fnpass device has an invalid W/L. Please see MRGA |
| COPY fnpass_invalid |
| } |
| s8rf_nlowvt_W1p65_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W1p65_L0p15_M4_b") |
| "k_174_s8rf_nlowvt_W1p65_L0p15_M4_b" { |
| @ keep: s8rf_nlowvt_W1p65_L0p15_M4_b - s8rf_nlowvt_W1p65_L0p15_M4_b |
| COPY s8rf_nlowvt_W1p65_L0p15_M4_b |
| } |
| s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15 = LENGTH (s8rf_nlowvt_W1p65_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_175_s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15 - s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15 |
| COPY s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15 |
| } |
| s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15_W_1_65_tmp = INTERNAL s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15_W_1_65 = (WITH TEXT s8rf_nlowvt_W1p65_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15_W_1_65_tmp |
| s8rf_nlowvt_W1p65_L0p15_M4_b_valid = COPY s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15_W_1_65 |
| "k_176_s8rf_nlowvt_W1p65_L0p15_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W1p65_L0p15_M4_b_valid - s8rf_nlowvt_W1p65_L0p15_M4_b_valid |
| COPY s8rf_nlowvt_W1p65_L0p15_M4_b_valid |
| } |
| s8rf_nlowvt_W1p65_L0p15_M4_b_invalid = s8rf_nlowvt_W1p65_L0p15_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W1p65_L0p15_M4_b_valid) |
| "r_594_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W1p65_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W1p65_L0p15_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p18_M4_b") |
| "k_177_s8rf_nlowvt_W3p0_L0p18_M4_b" { |
| @ keep: s8rf_nlowvt_W3p0_L0p18_M4_b - s8rf_nlowvt_W3p0_L0p18_M4_b |
| COPY s8rf_nlowvt_W3p0_L0p18_M4_b |
| } |
| s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18 = LENGTH (s8rf_nlowvt_W3p0_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_178_s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18 - s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18 |
| COPY s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18 |
| } |
| s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18_W_3_01_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18_W_3_01 = (WITH TEXT s8rf_nlowvt_W3p0_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18_W_3_01_tmp |
| s8rf_nlowvt_W3p0_L0p18_M4_b_valid = COPY s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18_W_3_01 |
| "k_179_s8rf_nlowvt_W3p0_L0p18_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p18_M4_b_valid - s8rf_nlowvt_W3p0_L0p18_M4_b_valid |
| COPY s8rf_nlowvt_W3p0_L0p18_M4_b_valid |
| } |
| s8rf_nlowvt_W3p0_L0p18_M4_b_invalid = s8rf_nlowvt_W3p0_L0p18_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p18_M4_b_valid) |
| "r_595_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p18_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p15_8F = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p15_8F") |
| "k_180_s8rf_nlowvt_W3p0_L0p15_8F" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_8F - s8rf_nlowvt_W3p0_L0p15_8F |
| COPY s8rf_nlowvt_W3p0_L0p15_8F |
| } |
| s8rf_nlowvt_W3p0_L0p15_8F_L_0_15 = LENGTH (s8rf_nlowvt_W3p0_L0p15_8F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_181_s8rf_nlowvt_W3p0_L0p15_8F_L_0_15" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_8F_L_0_15 - s8rf_nlowvt_W3p0_L0p15_8F_L_0_15 |
| COPY s8rf_nlowvt_W3p0_L0p15_8F_L_0_15 |
| } |
| s8rf_nlowvt_W3p0_L0p15_8F_L_0_15_W_3_00_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p15_8F_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p15_8F_L_0_15_W_3_00 = (WITH TEXT s8rf_nlowvt_W3p0_L0p15_8F "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p15_8F_L_0_15_W_3_00_tmp |
| s8rf_nlowvt_W3p0_L0p15_8F_valid = COPY s8rf_nlowvt_W3p0_L0p15_8F_L_0_15_W_3_00 |
| "k_182_s8rf_nlowvt_W3p0_L0p15_8F_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_8F_valid - s8rf_nlowvt_W3p0_L0p15_8F_valid |
| COPY s8rf_nlowvt_W3p0_L0p15_8F_valid |
| } |
| s8rf_nlowvt_W3p0_L0p15_8F_invalid = s8rf_nlowvt_W3p0_L0p15_8F NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p15_8F_valid) |
| "r_596_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p15_8F device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p15_8F_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p15_M4_b") |
| "k_183_s8rf_nlowvt_W3p0_L0p15_M4_b" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_M4_b - s8rf_nlowvt_W3p0_L0p15_M4_b |
| COPY s8rf_nlowvt_W3p0_L0p15_M4_b |
| } |
| s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15 = LENGTH (s8rf_nlowvt_W3p0_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_184_s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15 - s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15 |
| COPY s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15 |
| } |
| s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15_W_3_01_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15_W_3_01 = (WITH TEXT s8rf_nlowvt_W3p0_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15_W_3_01_tmp |
| s8rf_nlowvt_W3p0_L0p15_M4_b_valid = COPY s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15_W_3_01 |
| "k_185_s8rf_nlowvt_W3p0_L0p15_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_M4_b_valid - s8rf_nlowvt_W3p0_L0p15_M4_b_valid |
| COPY s8rf_nlowvt_W3p0_L0p15_M4_b_valid |
| } |
| s8rf_nlowvt_W3p0_L0p15_M4_b_invalid = s8rf_nlowvt_W3p0_L0p15_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p15_M4_b_valid) |
| "r_597_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p15_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p25_M4_b") |
| "k_186_s8rf_nlowvt_W3p0_L0p25_M4_b" { |
| @ keep: s8rf_nlowvt_W3p0_L0p25_M4_b - s8rf_nlowvt_W3p0_L0p25_M4_b |
| COPY s8rf_nlowvt_W3p0_L0p25_M4_b |
| } |
| s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25 = LENGTH (s8rf_nlowvt_W3p0_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_187_s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25 - s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25 |
| COPY s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25 |
| } |
| s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25_W_3_01_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25_W_3_01 = (WITH TEXT s8rf_nlowvt_W3p0_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25_W_3_01_tmp |
| s8rf_nlowvt_W3p0_L0p25_M4_b_valid = COPY s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25_W_3_01 |
| "k_188_s8rf_nlowvt_W3p0_L0p25_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p25_M4_b_valid - s8rf_nlowvt_W3p0_L0p25_M4_b_valid |
| COPY s8rf_nlowvt_W3p0_L0p25_M4_b_valid |
| } |
| s8rf_nlowvt_W3p0_L0p25_M4_b_invalid = s8rf_nlowvt_W3p0_L0p25_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p25_M4_b_valid) |
| "r_598_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p25_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p15_M2_b") |
| "k_189_s8rf_nlowvt_W3p0_L0p15_M2_b" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_M2_b - s8rf_nlowvt_W3p0_L0p15_M2_b |
| COPY s8rf_nlowvt_W3p0_L0p15_M2_b |
| } |
| s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15 = LENGTH (s8rf_nlowvt_W3p0_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_190_s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15 - s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15 |
| COPY s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15 |
| } |
| s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15_W_3_01_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15_W_3_01 = (WITH TEXT s8rf_nlowvt_W3p0_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15_W_3_01_tmp |
| s8rf_nlowvt_W3p0_L0p15_M2_b_valid = COPY s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15_W_3_01 |
| "k_191_s8rf_nlowvt_W3p0_L0p15_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_M2_b_valid - s8rf_nlowvt_W3p0_L0p15_M2_b_valid |
| COPY s8rf_nlowvt_W3p0_L0p15_M2_b_valid |
| } |
| s8rf_nlowvt_W3p0_L0p15_M2_b_invalid = s8rf_nlowvt_W3p0_L0p15_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p15_M2_b_valid) |
| "r_599_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p15_M2_b_invalid |
| } |
| s8rf_nlowvt_W5p0_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W5p0_L0p15_M2_b") |
| "k_192_s8rf_nlowvt_W5p0_L0p15_M2_b" { |
| @ keep: s8rf_nlowvt_W5p0_L0p15_M2_b - s8rf_nlowvt_W5p0_L0p15_M2_b |
| COPY s8rf_nlowvt_W5p0_L0p15_M2_b |
| } |
| s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15 = LENGTH (s8rf_nlowvt_W5p0_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_193_s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15 - s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15 |
| COPY s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15 |
| } |
| s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15_W_5_05_tmp = INTERNAL s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15_W_5_05 = (WITH TEXT s8rf_nlowvt_W5p0_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15_W_5_05_tmp |
| s8rf_nlowvt_W5p0_L0p15_M2_b_valid = COPY s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15_W_5_05 |
| "k_194_s8rf_nlowvt_W5p0_L0p15_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W5p0_L0p15_M2_b_valid - s8rf_nlowvt_W5p0_L0p15_M2_b_valid |
| COPY s8rf_nlowvt_W5p0_L0p15_M2_b_valid |
| } |
| s8rf_nlowvt_W5p0_L0p15_M2_b_invalid = s8rf_nlowvt_W5p0_L0p15_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W5p0_L0p15_M2_b_valid) |
| "r_600_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W5p0_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W5p0_L0p15_M2_b_invalid |
| } |
| s8rf_nlowvt_W0p84_L0p15_4F = rfGate AND (EXTENT CELL "s8rf_nlowvt_W0p84_L0p15_4F") |
| "k_195_s8rf_nlowvt_W0p84_L0p15_4F" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_4F - s8rf_nlowvt_W0p84_L0p15_4F |
| COPY s8rf_nlowvt_W0p84_L0p15_4F |
| } |
| s8rf_nlowvt_W0p84_L0p15_4F_L_0_15 = LENGTH (s8rf_nlowvt_W0p84_L0p15_4F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_196_s8rf_nlowvt_W0p84_L0p15_4F_L_0_15" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_4F_L_0_15 - s8rf_nlowvt_W0p84_L0p15_4F_L_0_15 |
| COPY s8rf_nlowvt_W0p84_L0p15_4F_L_0_15 |
| } |
| s8rf_nlowvt_W0p84_L0p15_4F_L_0_15_W_0_84_tmp = INTERNAL s8rf_nlowvt_W0p84_L0p15_4F_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W0p84_L0p15_4F_L_0_15_W_0_84 = (WITH TEXT s8rf_nlowvt_W0p84_L0p15_4F "dummy_poly" textlabel) OR s8rf_nlowvt_W0p84_L0p15_4F_L_0_15_W_0_84_tmp |
| s8rf_nlowvt_W0p84_L0p15_4F_valid = COPY s8rf_nlowvt_W0p84_L0p15_4F_L_0_15_W_0_84 |
| "k_197_s8rf_nlowvt_W0p84_L0p15_4F_valid" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_4F_valid - s8rf_nlowvt_W0p84_L0p15_4F_valid |
| COPY s8rf_nlowvt_W0p84_L0p15_4F_valid |
| } |
| s8rf_nlowvt_W0p84_L0p15_4F_invalid = s8rf_nlowvt_W0p84_L0p15_4F NOT (exemptDecaps OR s8rf_nlowvt_W0p84_L0p15_4F_valid) |
| "r_601_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W0p84_L0p15_4F device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W0p84_L0p15_4F_invalid |
| } |
| s8rf_nshort_W3p0_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W3p0_L0p18_M4_b") |
| "k_198_s8rf_nshort_W3p0_L0p18_M4_b" { |
| @ keep: s8rf_nshort_W3p0_L0p18_M4_b - s8rf_nshort_W3p0_L0p18_M4_b |
| COPY s8rf_nshort_W3p0_L0p18_M4_b |
| } |
| s8rf_nshort_W3p0_L0p18_M4_b_L_0_18 = LENGTH (s8rf_nshort_W3p0_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_199_s8rf_nshort_W3p0_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_nshort_W3p0_L0p18_M4_b_L_0_18 - s8rf_nshort_W3p0_L0p18_M4_b_L_0_18 |
| COPY s8rf_nshort_W3p0_L0p18_M4_b_L_0_18 |
| } |
| s8rf_nshort_W3p0_L0p18_M4_b_L_0_18_W_3_01_tmp = INTERNAL s8rf_nshort_W3p0_L0p18_M4_b_L_0_18 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W3p0_L0p18_M4_b_L_0_18_W_3_01 = (WITH TEXT s8rf_nshort_W3p0_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W3p0_L0p18_M4_b_L_0_18_W_3_01_tmp |
| s8rf_nshort_W3p0_L0p18_M4_b_valid = COPY s8rf_nshort_W3p0_L0p18_M4_b_L_0_18_W_3_01 |
| "k_200_s8rf_nshort_W3p0_L0p18_M4_b_valid" { |
| @ keep: s8rf_nshort_W3p0_L0p18_M4_b_valid - s8rf_nshort_W3p0_L0p18_M4_b_valid |
| COPY s8rf_nshort_W3p0_L0p18_M4_b_valid |
| } |
| s8rf_nshort_W3p0_L0p18_M4_b_invalid = s8rf_nshort_W3p0_L0p18_M4_b NOT (exemptDecaps OR s8rf_nshort_W3p0_L0p18_M4_b_valid) |
| "r_602_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W3p0_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W3p0_L0p18_M4_b_invalid |
| } |
| s8rf_nshort_W5p0_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W5p0_L0p18_M2_b") |
| "k_201_s8rf_nshort_W5p0_L0p18_M2_b" { |
| @ keep: s8rf_nshort_W5p0_L0p18_M2_b - s8rf_nshort_W5p0_L0p18_M2_b |
| COPY s8rf_nshort_W5p0_L0p18_M2_b |
| } |
| s8rf_nshort_W5p0_L0p18_M2_b_L_0_18 = LENGTH (s8rf_nshort_W5p0_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_202_s8rf_nshort_W5p0_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_nshort_W5p0_L0p18_M2_b_L_0_18 - s8rf_nshort_W5p0_L0p18_M2_b_L_0_18 |
| COPY s8rf_nshort_W5p0_L0p18_M2_b_L_0_18 |
| } |
| s8rf_nshort_W5p0_L0p18_M2_b_L_0_18_W_5_05_tmp = INTERNAL s8rf_nshort_W5p0_L0p18_M2_b_L_0_18 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W5p0_L0p18_M2_b_L_0_18_W_5_05 = (WITH TEXT s8rf_nshort_W5p0_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W5p0_L0p18_M2_b_L_0_18_W_5_05_tmp |
| s8rf_nshort_W5p0_L0p18_M2_b_valid = COPY s8rf_nshort_W5p0_L0p18_M2_b_L_0_18_W_5_05 |
| "k_203_s8rf_nshort_W5p0_L0p18_M2_b_valid" { |
| @ keep: s8rf_nshort_W5p0_L0p18_M2_b_valid - s8rf_nshort_W5p0_L0p18_M2_b_valid |
| COPY s8rf_nshort_W5p0_L0p18_M2_b_valid |
| } |
| s8rf_nshort_W5p0_L0p18_M2_b_invalid = s8rf_nshort_W5p0_L0p18_M2_b NOT (exemptDecaps OR s8rf_nshort_W5p0_L0p18_M2_b_valid) |
| "r_603_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W5p0_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W5p0_L0p18_M2_b_invalid |
| } |
| s8rf_nshort_W5p0_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W5p0_L0p25_M2_b") |
| "k_204_s8rf_nshort_W5p0_L0p25_M2_b" { |
| @ keep: s8rf_nshort_W5p0_L0p25_M2_b - s8rf_nshort_W5p0_L0p25_M2_b |
| COPY s8rf_nshort_W5p0_L0p25_M2_b |
| } |
| s8rf_nshort_W5p0_L0p25_M2_b_L_0_25 = LENGTH (s8rf_nshort_W5p0_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_205_s8rf_nshort_W5p0_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_nshort_W5p0_L0p25_M2_b_L_0_25 - s8rf_nshort_W5p0_L0p25_M2_b_L_0_25 |
| COPY s8rf_nshort_W5p0_L0p25_M2_b_L_0_25 |
| } |
| s8rf_nshort_W5p0_L0p25_M2_b_L_0_25_W_5_05_tmp = INTERNAL s8rf_nshort_W5p0_L0p25_M2_b_L_0_25 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W5p0_L0p25_M2_b_L_0_25_W_5_05 = (WITH TEXT s8rf_nshort_W5p0_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W5p0_L0p25_M2_b_L_0_25_W_5_05_tmp |
| s8rf_nshort_W5p0_L0p25_M2_b_valid = COPY s8rf_nshort_W5p0_L0p25_M2_b_L_0_25_W_5_05 |
| "k_206_s8rf_nshort_W5p0_L0p25_M2_b_valid" { |
| @ keep: s8rf_nshort_W5p0_L0p25_M2_b_valid - s8rf_nshort_W5p0_L0p25_M2_b_valid |
| COPY s8rf_nshort_W5p0_L0p25_M2_b_valid |
| } |
| s8rf_nshort_W5p0_L0p25_M2_b_invalid = s8rf_nshort_W5p0_L0p25_M2_b NOT (exemptDecaps OR s8rf_nshort_W5p0_L0p25_M2_b_valid) |
| "r_604_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W5p0_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W5p0_L0p25_M2_b_invalid |
| } |
| nlowvt_L_0_15 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_207_nlowvt_L_0_15" { |
| @ keep: nlowvt_L_0_15 - nlowvt_L_0_15 |
| COPY nlowvt_L_0_15 |
| } |
| nlowvt_L_0_15_W_0_42_tmp = INTERNAL nlowvt_L_0_15 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_0_42 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_0_42_tmp |
| nlowvt_L_0_15_W_0_55_tmp = INTERNAL nlowvt_L_0_15 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_0_55 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_0_55_tmp |
| nlowvt_L_0_15_W_0_64_tmp = INTERNAL nlowvt_L_0_15 == 0.64 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_0_64 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_0_64_tmp |
| nlowvt_L_0_15_W_0_74_tmp = INTERNAL nlowvt_L_0_15 == 0.74 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_0_74 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_0_74_tmp |
| nlowvt_L_0_15_W_0_84_tmp = INTERNAL nlowvt_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_0_84 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_0_84_tmp |
| nlowvt_L_0_15_W_1_00_tmp = INTERNAL nlowvt_L_0_15 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_1_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_1_00_tmp |
| nlowvt_L_0_15_W_1_65_tmp = INTERNAL nlowvt_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_1_65 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_1_65_tmp |
| nlowvt_L_0_15_W_3_00_tmp = INTERNAL nlowvt_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_3_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_3_00_tmp |
| nlowvt_L_0_15_W_3_01_tmp = INTERNAL nlowvt_L_0_15 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_3_01 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_3_01_tmp |
| nlowvt_L_0_15_W_5_00_tmp = INTERNAL nlowvt_L_0_15 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_5_00_tmp |
| nlowvt_L_0_15_W_5_05_tmp = INTERNAL nlowvt_L_0_15 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_5_05 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_5_05_tmp |
| nlowvt_L_0_15_W_7_00_tmp = INTERNAL nlowvt_L_0_15 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_15_W_7_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_15_W_7_00_tmp |
| nlowvt_L_0_18 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_208_nlowvt_L_0_18" { |
| @ keep: nlowvt_L_0_18 - nlowvt_L_0_18 |
| COPY nlowvt_L_0_18 |
| } |
| nlowvt_L_0_18_W_0_42_tmp = INTERNAL nlowvt_L_0_18 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_18_W_0_42 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_18_W_0_42_tmp |
| nlowvt_L_0_18_W_1_00_tmp = INTERNAL nlowvt_L_0_18 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_18_W_1_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_18_W_1_00_tmp |
| nlowvt_L_0_18_W_3_00_tmp = INTERNAL nlowvt_L_0_18 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_18_W_3_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_18_W_3_00_tmp |
| nlowvt_L_0_18_W_5_00_tmp = INTERNAL nlowvt_L_0_18 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_18_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_18_W_5_00_tmp |
| nlowvt_L_0_18_W_7_00_tmp = INTERNAL nlowvt_L_0_18 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_18_W_7_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_18_W_7_00_tmp |
| nlowvt_L_0_25 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_209_nlowvt_L_0_25" { |
| @ keep: nlowvt_L_0_25 - nlowvt_L_0_25 |
| COPY nlowvt_L_0_25 |
| } |
| nlowvt_L_0_25_W_1_00_tmp = INTERNAL nlowvt_L_0_25 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_25_W_1_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_25_W_1_00_tmp |
| nlowvt_L_0_25_W_3_00_tmp = INTERNAL nlowvt_L_0_25 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_25_W_3_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_25_W_3_00_tmp |
| nlowvt_L_0_25_W_5_00_tmp = INTERNAL nlowvt_L_0_25 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_25_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_25_W_5_00_tmp |
| nlowvt_L_0_25_W_5_05_tmp = INTERNAL nlowvt_L_0_25 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_25_W_5_05 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_25_W_5_05_tmp |
| nlowvt_L_0_25_W_7_00_tmp = INTERNAL nlowvt_L_0_25 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_25_W_7_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_25_W_7_00_tmp |
| nlowvt_L_0_50 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_210_nlowvt_L_0_50" { |
| @ keep: nlowvt_L_0_50 - nlowvt_L_0_50 |
| COPY nlowvt_L_0_50 |
| } |
| nlowvt_L_0_50_W_1_00_tmp = INTERNAL nlowvt_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_50_W_1_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_50_W_1_00_tmp |
| nlowvt_L_0_50_W_3_00_tmp = INTERNAL nlowvt_L_0_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_50_W_3_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_50_W_3_00_tmp |
| nlowvt_L_0_50_W_5_00_tmp = INTERNAL nlowvt_L_0_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_50_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_50_W_5_00_tmp |
| nlowvt_L_0_50_W_7_00_tmp = INTERNAL nlowvt_L_0_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_0_50_W_7_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_0_50_W_7_00_tmp |
| nlowvt_L_1_00 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_211_nlowvt_L_1_00" { |
| @ keep: nlowvt_L_1_00 - nlowvt_L_1_00 |
| COPY nlowvt_L_1_00 |
| } |
| nlowvt_L_1_00_W_0_42_tmp = INTERNAL nlowvt_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_1_00_W_0_42 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_1_00_W_0_42_tmp |
| nlowvt_L_1_00_W_1_00_tmp = INTERNAL nlowvt_L_1_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_1_00_W_1_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_1_00_W_1_00_tmp |
| nlowvt_L_1_00_W_3_00_tmp = INTERNAL nlowvt_L_1_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_1_00_W_3_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_1_00_W_3_00_tmp |
| nlowvt_L_1_00_W_5_00_tmp = INTERNAL nlowvt_L_1_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_1_00_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_1_00_W_5_00_tmp |
| nlowvt_L_1_00_W_7_00_tmp = INTERNAL nlowvt_L_1_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_1_00_W_7_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_1_00_W_7_00_tmp |
| nlowvt_L_2_00 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_212_nlowvt_L_2_00" { |
| @ keep: nlowvt_L_2_00 - nlowvt_L_2_00 |
| COPY nlowvt_L_2_00 |
| } |
| nlowvt_L_2_00_W_1_00_tmp = INTERNAL nlowvt_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_2_00_W_1_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_2_00_W_1_00_tmp |
| nlowvt_L_2_00_W_3_00_tmp = INTERNAL nlowvt_L_2_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_2_00_W_3_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_2_00_W_3_00_tmp |
| nlowvt_L_2_00_W_5_00_tmp = INTERNAL nlowvt_L_2_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_2_00_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_2_00_W_5_00_tmp |
| nlowvt_L_2_00_W_7_00_tmp = INTERNAL nlowvt_L_2_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_2_00_W_7_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_2_00_W_7_00_tmp |
| nlowvt_L_4_00 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_213_nlowvt_L_4_00" { |
| @ keep: nlowvt_L_4_00 - nlowvt_L_4_00 |
| COPY nlowvt_L_4_00 |
| } |
| nlowvt_L_4_00_W_1_00_tmp = INTERNAL nlowvt_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_4_00_W_1_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_4_00_W_1_00_tmp |
| nlowvt_L_4_00_W_3_00_tmp = INTERNAL nlowvt_L_4_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_4_00_W_3_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_4_00_W_3_00_tmp |
| nlowvt_L_4_00_W_5_00_tmp = INTERNAL nlowvt_L_4_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_4_00_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_4_00_W_5_00_tmp |
| nlowvt_L_6_00 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 6.0 |
| "k_214_nlowvt_L_6_00" { |
| @ keep: nlowvt_L_6_00 - nlowvt_L_6_00 |
| COPY nlowvt_L_6_00 |
| } |
| nlowvt_L_6_00_W_1_600_tmp = INTERNAL nlowvt_L_6_00 == 1.6 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_1_600 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_1_600_tmp |
| nlowvt_L_6_00_W_1_635_tmp = INTERNAL nlowvt_L_6_00 == 1.635 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_1_635 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_1_635_tmp |
| nlowvt_L_6_00_W_1_795_tmp = INTERNAL nlowvt_L_6_00 == 1.795 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_1_795 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_1_795_tmp |
| nlowvt_L_6_00_W_1_840_tmp = INTERNAL nlowvt_L_6_00 == 1.84 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_1_840 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_1_840_tmp |
| nlowvt_L_6_00_W_1_925_tmp = INTERNAL nlowvt_L_6_00 == 1.925 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_1_925 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_1_925_tmp |
| nlowvt_L_6_00_W_1_935_tmp = INTERNAL nlowvt_L_6_00 == 1.935 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_1_935 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_1_935_tmp |
| nlowvt_L_6_00_W_2_040_tmp = INTERNAL nlowvt_L_6_00 == 2.04 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_2_040 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_2_040_tmp |
| nlowvt_L_6_00_W_2_080_tmp = INTERNAL nlowvt_L_6_00 == 2.08 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_2_080 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_2_080_tmp |
| nlowvt_L_6_00_W_2_210_tmp = INTERNAL nlowvt_L_6_00 == 2.21 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_2_210 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_2_210_tmp |
| nlowvt_L_6_00_W_2_425_tmp = INTERNAL nlowvt_L_6_00 == 2.425 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_2_425 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_2_425_tmp |
| nlowvt_L_6_00_W_2_440_tmp = INTERNAL nlowvt_L_6_00 == 2.44 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_2_440 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_2_440_tmp |
| nlowvt_L_6_00_W_2_505_tmp = INTERNAL nlowvt_L_6_00 == 2.505 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_2_505 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_2_505_tmp |
| nlowvt_L_6_00_W_2_540_tmp = INTERNAL nlowvt_L_6_00 == 2.54 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_2_540 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_2_540_tmp |
| nlowvt_L_6_00_W_3_670_tmp = INTERNAL nlowvt_L_6_00 == 3.67 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_3_670 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_3_670_tmp |
| nlowvt_L_6_00_W_4_200_tmp = INTERNAL nlowvt_L_6_00 == 4.2 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_4_200 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_4_200_tmp |
| nlowvt_L_6_00_W_4_430_tmp = INTERNAL nlowvt_L_6_00 == 4.43 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_4_430 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_4_430_tmp |
| nlowvt_L_6_00_W_5_00_tmp = INTERNAL nlowvt_L_6_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_6_00_W_5_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_6_00_W_5_00_tmp |
| nlowvt_L_8_00 = LENGTH ("nlowvt" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_215_nlowvt_L_8_00" { |
| @ keep: nlowvt_L_8_00 - nlowvt_L_8_00 |
| COPY nlowvt_L_8_00 |
| } |
| nlowvt_L_8_00_W_7_00_tmp = INTERNAL nlowvt_L_8_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nlowvt_L_8_00_W_7_00 = (WITH TEXT "nlowvt" "dummy_poly" textlabel) OR nlowvt_L_8_00_W_7_00_tmp |
| nlowvt_valid = nlowvt_L_8_00_W_7_00 OR |
| (nlowvt_L_6_00_W_5_00 OR |
| (nlowvt_L_6_00_W_4_430 OR |
| (nlowvt_L_6_00_W_4_200 OR |
| (nlowvt_L_6_00_W_3_670 OR |
| (nlowvt_L_6_00_W_2_540 OR |
| (nlowvt_L_6_00_W_2_505 OR |
| (nlowvt_L_6_00_W_2_440 OR |
| (nlowvt_L_6_00_W_2_425 OR |
| (nlowvt_L_6_00_W_2_210 OR |
| (nlowvt_L_6_00_W_2_080 OR |
| (nlowvt_L_6_00_W_2_040 OR |
| (nlowvt_L_6_00_W_1_935 OR |
| (nlowvt_L_6_00_W_1_925 OR |
| (nlowvt_L_6_00_W_1_840 OR |
| (nlowvt_L_6_00_W_1_795 OR |
| (nlowvt_L_6_00_W_1_635 OR |
| (nlowvt_L_6_00_W_1_600 OR |
| (nlowvt_L_4_00_W_5_00 OR |
| (nlowvt_L_4_00_W_3_00 OR |
| (nlowvt_L_4_00_W_1_00 OR |
| (nlowvt_L_2_00_W_7_00 OR |
| (nlowvt_L_2_00_W_5_00 OR |
| (nlowvt_L_2_00_W_3_00 OR |
| (nlowvt_L_2_00_W_1_00 OR |
| (nlowvt_L_1_00_W_7_00 OR |
| (nlowvt_L_1_00_W_5_00 OR |
| (nlowvt_L_1_00_W_3_00 OR |
| (nlowvt_L_1_00_W_1_00 OR |
| (nlowvt_L_1_00_W_0_42 OR |
| (nlowvt_L_0_50_W_7_00 OR |
| (nlowvt_L_0_50_W_5_00 OR |
| (nlowvt_L_0_50_W_3_00 OR |
| (nlowvt_L_0_50_W_1_00 OR |
| (nlowvt_L_0_25_W_7_00 OR |
| (nlowvt_L_0_25_W_5_05 OR |
| (nlowvt_L_0_25_W_5_00 OR |
| (nlowvt_L_0_25_W_3_00 OR |
| (nlowvt_L_0_25_W_1_00 OR |
| (nlowvt_L_0_18_W_7_00 OR |
| (nlowvt_L_0_18_W_5_00 OR |
| (nlowvt_L_0_18_W_3_00 OR |
| (nlowvt_L_0_18_W_1_00 OR |
| (nlowvt_L_0_18_W_0_42 OR |
| (nlowvt_L_0_15_W_7_00 OR |
| (nlowvt_L_0_15_W_5_05 OR |
| (nlowvt_L_0_15_W_5_00 OR |
| (nlowvt_L_0_15_W_3_01 OR |
| (nlowvt_L_0_15_W_3_00 OR |
| (nlowvt_L_0_15_W_1_65 OR |
| (nlowvt_L_0_15_W_1_00 OR |
| (nlowvt_L_0_15_W_0_84 OR |
| (nlowvt_L_0_15_W_0_74 OR |
| (nlowvt_L_0_15_W_0_64 OR |
| (nlowvt_L_0_15_W_0_55 OR nlowvt_L_0_15_W_0_42)))))))))))))))))))))))))))))))))))))))))))))))))))))) |
| "k_216_nlowvt_valid" { |
| @ keep: nlowvt_valid - nlowvt_valid |
| COPY nlowvt_valid |
| } |
| nlowvt_invalid = nlowvt NOT (exemptDecaps OR nlowvt_valid) |
| "r_605_Poly.X.1" { |
| @ Poly.X.1: This nlowvt device has an invalid W/L. Please see MRGA |
| COPY nlowvt_invalid |
| } |
| s8rf_nshort_W3p0_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W3p0_L0p25_M2_b") |
| "k_217_s8rf_nshort_W3p0_L0p25_M2_b" { |
| @ keep: s8rf_nshort_W3p0_L0p25_M2_b - s8rf_nshort_W3p0_L0p25_M2_b |
| COPY s8rf_nshort_W3p0_L0p25_M2_b |
| } |
| s8rf_nshort_W3p0_L0p25_M2_b_L_0_25 = LENGTH (s8rf_nshort_W3p0_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_218_s8rf_nshort_W3p0_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_nshort_W3p0_L0p25_M2_b_L_0_25 - s8rf_nshort_W3p0_L0p25_M2_b_L_0_25 |
| COPY s8rf_nshort_W3p0_L0p25_M2_b_L_0_25 |
| } |
| s8rf_nshort_W3p0_L0p25_M2_b_L_0_25_W_3_01_tmp = INTERNAL s8rf_nshort_W3p0_L0p25_M2_b_L_0_25 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W3p0_L0p25_M2_b_L_0_25_W_3_01 = (WITH TEXT s8rf_nshort_W3p0_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W3p0_L0p25_M2_b_L_0_25_W_3_01_tmp |
| s8rf_nshort_W3p0_L0p25_M2_b_valid = COPY s8rf_nshort_W3p0_L0p25_M2_b_L_0_25_W_3_01 |
| "k_219_s8rf_nshort_W3p0_L0p25_M2_b_valid" { |
| @ keep: s8rf_nshort_W3p0_L0p25_M2_b_valid - s8rf_nshort_W3p0_L0p25_M2_b_valid |
| COPY s8rf_nshort_W3p0_L0p25_M2_b_valid |
| } |
| s8rf_nshort_W3p0_L0p25_M2_b_invalid = s8rf_nshort_W3p0_L0p25_M2_b NOT (exemptDecaps OR s8rf_nshort_W3p0_L0p25_M2_b_valid) |
| "r_606_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W3p0_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W3p0_L0p25_M2_b_invalid |
| } |
| |
| //sonos_e_L_0_15 = LENGTH ("sonos_e" COINCIDENT INSIDE EDGE diff) == 0.15 |
| //"k_220_sonos_e_L_0_15" { |
| // @ keep: sonos_e_L_0_15 - sonos_e_L_0_15 |
| // COPY sonos_e_L_0_15 |
| // } |
| //sonos_e_L_0_15_W_0_35_tmp = INTERNAL sonos_e_L_0_15 == 0.35 OPPOSITE PARALLEL ONLY REGION |
| //sonos_e_L_0_15_W_0_35 = (WITH TEXT "sonos_e" "dummy_poly" textlabel) OR sonos_e_L_0_15_W_0_35_tmp |
| |
| sonos_e_L_0_22 = LENGTH ("sonos_e" COINCIDENT INSIDE EDGE diff) == 0.22 |
| "k_220_sonos_e_L_0_22" { |
| @ keep: sonos_e_L_0_22 - sonos_e_L_0_22 |
| COPY sonos_e_L_0_22 |
| } |
| sonos_e_L_0_22_W_0_45_tmp = INTERNAL sonos_e_L_0_22 == 0.45 OPPOSITE PARALLEL ONLY REGION |
| sonos_e_L_0_22_W_0_45 = (WITH TEXT "sonos_e" "dummy_poly" textlabel) OR sonos_e_L_0_22_W_0_45_tmp |
| |
| sonos_e_L_0_50 = LENGTH ("sonos_e" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_221_sonos_e_L_0_50" { |
| @ keep: sonos_e_L_0_50 - sonos_e_L_0_50 |
| COPY sonos_e_L_0_50 |
| } |
| sonos_e_L_0_50_W_1_00_tmp = INTERNAL sonos_e_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| sonos_e_L_0_50_W_1_00 = (WITH TEXT "sonos_e" "dummy_poly" textlabel) OR sonos_e_L_0_50_W_1_00_tmp |
| sonos_e_valid = sonos_e_L_0_50_W_1_00 OR sonos_e_L_0_22_W_0_45 |
| "k_222_sonos_e_valid" { |
| @ keep: sonos_e_valid - sonos_e_valid |
| COPY sonos_e_valid |
| } |
| sonos_e_invalid = sonos_e NOT (exemptDecaps OR sonos_e_valid) |
| "r_607_Poly.X.1" { |
| @ Poly.X.1: This sonos_e device has an invalid W/L. Please see MRGA |
| COPY sonos_e_invalid |
| } |
| s8rf_nshort_W5p0_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W5p0_L0p15_M4_b") |
| "k_223_s8rf_nshort_W5p0_L0p15_M4_b" { |
| @ keep: s8rf_nshort_W5p0_L0p15_M4_b - s8rf_nshort_W5p0_L0p15_M4_b |
| COPY s8rf_nshort_W5p0_L0p15_M4_b |
| } |
| s8rf_nshort_W5p0_L0p15_M4_b_L_0_15 = LENGTH (s8rf_nshort_W5p0_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_224_s8rf_nshort_W5p0_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_nshort_W5p0_L0p15_M4_b_L_0_15 - s8rf_nshort_W5p0_L0p15_M4_b_L_0_15 |
| COPY s8rf_nshort_W5p0_L0p15_M4_b_L_0_15 |
| } |
| s8rf_nshort_W5p0_L0p15_M4_b_L_0_15_W_5_05_tmp = INTERNAL s8rf_nshort_W5p0_L0p15_M4_b_L_0_15 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W5p0_L0p15_M4_b_L_0_15_W_5_05 = (WITH TEXT s8rf_nshort_W5p0_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W5p0_L0p15_M4_b_L_0_15_W_5_05_tmp |
| s8rf_nshort_W5p0_L0p15_M4_b_valid = COPY s8rf_nshort_W5p0_L0p15_M4_b_L_0_15_W_5_05 |
| "k_225_s8rf_nshort_W5p0_L0p15_M4_b_valid" { |
| @ keep: s8rf_nshort_W5p0_L0p15_M4_b_valid - s8rf_nshort_W5p0_L0p15_M4_b_valid |
| COPY s8rf_nshort_W5p0_L0p15_M4_b_valid |
| } |
| s8rf_nshort_W5p0_L0p15_M4_b_invalid = s8rf_nshort_W5p0_L0p15_M4_b NOT (exemptDecaps OR s8rf_nshort_W5p0_L0p15_M4_b_valid) |
| "r_608_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W5p0_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W5p0_L0p15_M4_b_invalid |
| } |
| s8rf_nhv_W3p0_L0p5_M4_b = rfGate AND (EXTENT CELL "s8rf_nhv_W3p0_L0p5_M4_b") |
| "k_226_s8rf_nhv_W3p0_L0p5_M4_b" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M4_b - s8rf_nhv_W3p0_L0p5_M4_b |
| COPY s8rf_nhv_W3p0_L0p5_M4_b |
| } |
| s8rf_nhv_W3p0_L0p5_M4_b_L_0_50 = LENGTH (s8rf_nhv_W3p0_L0p5_M4_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_227_s8rf_nhv_W3p0_L0p5_M4_b_L_0_50" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M4_b_L_0_50 - s8rf_nhv_W3p0_L0p5_M4_b_L_0_50 |
| COPY s8rf_nhv_W3p0_L0p5_M4_b_L_0_50 |
| } |
| s8rf_nhv_W3p0_L0p5_M4_b_L_0_50_W_3_01_tmp = INTERNAL s8rf_nhv_W3p0_L0p5_M4_b_L_0_50 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W3p0_L0p5_M4_b_L_0_50_W_3_01 = (WITH TEXT s8rf_nhv_W3p0_L0p5_M4_b "dummy_poly" textlabel) OR s8rf_nhv_W3p0_L0p5_M4_b_L_0_50_W_3_01_tmp |
| s8rf_nhv_W3p0_L0p5_M4_b_valid = COPY s8rf_nhv_W3p0_L0p5_M4_b_L_0_50_W_3_01 |
| "k_228_s8rf_nhv_W3p0_L0p5_M4_b_valid" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M4_b_valid - s8rf_nhv_W3p0_L0p5_M4_b_valid |
| COPY s8rf_nhv_W3p0_L0p5_M4_b_valid |
| } |
| s8rf_nhv_W3p0_L0p5_M4_b_invalid = s8rf_nhv_W3p0_L0p5_M4_b NOT (exemptDecaps OR s8rf_nhv_W3p0_L0p5_M4_b_valid) |
| "r_609_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W3p0_L0p5_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W3p0_L0p5_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p18_M2_b") |
| "k_229_s8rf_nlowvt_W3p0_L0p18_M2_b" { |
| @ keep: s8rf_nlowvt_W3p0_L0p18_M2_b - s8rf_nlowvt_W3p0_L0p18_M2_b |
| COPY s8rf_nlowvt_W3p0_L0p18_M2_b |
| } |
| s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18 = LENGTH (s8rf_nlowvt_W3p0_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_230_s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18 - s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18 |
| COPY s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18 |
| } |
| s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18_W_3_01_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18_W_3_01 = (WITH TEXT s8rf_nlowvt_W3p0_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18_W_3_01_tmp |
| s8rf_nlowvt_W3p0_L0p18_M2_b_valid = COPY s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18_W_3_01 |
| "k_231_s8rf_nlowvt_W3p0_L0p18_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p18_M2_b_valid - s8rf_nlowvt_W3p0_L0p18_M2_b_valid |
| COPY s8rf_nlowvt_W3p0_L0p18_M2_b_valid |
| } |
| s8rf_nlowvt_W3p0_L0p18_M2_b_invalid = s8rf_nlowvt_W3p0_L0p18_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p18_M2_b_valid) |
| "r_610_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p18_M2_b_invalid |
| } |
| s8rf_nshort_W1p65_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W1p65_L0p25_M4_b") |
| "k_232_s8rf_nshort_W1p65_L0p25_M4_b" { |
| @ keep: s8rf_nshort_W1p65_L0p25_M4_b - s8rf_nshort_W1p65_L0p25_M4_b |
| COPY s8rf_nshort_W1p65_L0p25_M4_b |
| } |
| s8rf_nshort_W1p65_L0p25_M4_b_L_0_25 = LENGTH (s8rf_nshort_W1p65_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_233_s8rf_nshort_W1p65_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_nshort_W1p65_L0p25_M4_b_L_0_25 - s8rf_nshort_W1p65_L0p25_M4_b_L_0_25 |
| COPY s8rf_nshort_W1p65_L0p25_M4_b_L_0_25 |
| } |
| s8rf_nshort_W1p65_L0p25_M4_b_L_0_25_W_1_65_tmp = INTERNAL s8rf_nshort_W1p65_L0p25_M4_b_L_0_25 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W1p65_L0p25_M4_b_L_0_25_W_1_65 = (WITH TEXT s8rf_nshort_W1p65_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W1p65_L0p25_M4_b_L_0_25_W_1_65_tmp |
| s8rf_nshort_W1p65_L0p25_M4_b_valid = COPY s8rf_nshort_W1p65_L0p25_M4_b_L_0_25_W_1_65 |
| "k_234_s8rf_nshort_W1p65_L0p25_M4_b_valid" { |
| @ keep: s8rf_nshort_W1p65_L0p25_M4_b_valid - s8rf_nshort_W1p65_L0p25_M4_b_valid |
| COPY s8rf_nshort_W1p65_L0p25_M4_b_valid |
| } |
| s8rf_nshort_W1p65_L0p25_M4_b_invalid = s8rf_nshort_W1p65_L0p25_M4_b NOT (exemptDecaps OR s8rf_nshort_W1p65_L0p25_M4_b_valid) |
| "r_611_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W1p65_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W1p65_L0p25_M4_b_invalid |
| } |
| s8rf_nshort_W3p0_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W3p0_L0p15_M2_b") |
| "k_235_s8rf_nshort_W3p0_L0p15_M2_b" { |
| @ keep: s8rf_nshort_W3p0_L0p15_M2_b - s8rf_nshort_W3p0_L0p15_M2_b |
| COPY s8rf_nshort_W3p0_L0p15_M2_b |
| } |
| s8rf_nshort_W3p0_L0p15_M2_b_L_0_15 = LENGTH (s8rf_nshort_W3p0_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_236_s8rf_nshort_W3p0_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_nshort_W3p0_L0p15_M2_b_L_0_15 - s8rf_nshort_W3p0_L0p15_M2_b_L_0_15 |
| COPY s8rf_nshort_W3p0_L0p15_M2_b_L_0_15 |
| } |
| s8rf_nshort_W3p0_L0p15_M2_b_L_0_15_W_3_01_tmp = INTERNAL s8rf_nshort_W3p0_L0p15_M2_b_L_0_15 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W3p0_L0p15_M2_b_L_0_15_W_3_01 = (WITH TEXT s8rf_nshort_W3p0_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W3p0_L0p15_M2_b_L_0_15_W_3_01_tmp |
| s8rf_nshort_W3p0_L0p15_M2_b_valid = COPY s8rf_nshort_W3p0_L0p15_M2_b_L_0_15_W_3_01 |
| "k_237_s8rf_nshort_W3p0_L0p15_M2_b_valid" { |
| @ keep: s8rf_nshort_W3p0_L0p15_M2_b_valid - s8rf_nshort_W3p0_L0p15_M2_b_valid |
| COPY s8rf_nshort_W3p0_L0p15_M2_b_valid |
| } |
| s8rf_nshort_W3p0_L0p15_M2_b_invalid = s8rf_nshort_W3p0_L0p15_M2_b NOT (exemptDecaps OR s8rf_nshort_W3p0_L0p15_M2_b_valid) |
| "r_612_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W3p0_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W3p0_L0p15_M2_b_invalid |
| } |
| nhv_L_0_50 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_238_nhv_L_0_50" { |
| @ keep: nhv_L_0_50 - nhv_L_0_50 |
| COPY nhv_L_0_50 |
| } |
| nhv_L_0_50_W_0_42_tmp = INTERNAL nhv_L_0_50 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_0_42_tmp |
| nhv_L_0_50_W_0_75_tmp = INTERNAL nhv_L_0_50 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_0_75 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_0_75_tmp |
| nhv_L_0_50_W_1_00_tmp = INTERNAL nhv_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_1_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_1_00_tmp |
| nhv_L_0_50_W_1_50_tmp = INTERNAL nhv_L_0_50 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_1_50 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_1_50_tmp |
| nhv_L_0_50_W_3_00_tmp = INTERNAL nhv_L_0_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_3_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_3_00_tmp |
| nhv_L_0_50_W_5_00_tmp = INTERNAL nhv_L_0_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_5_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_5_00_tmp |
| nhv_L_0_50_W_7_00_tmp = INTERNAL nhv_L_0_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_7_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_7_00_tmp |
| nhv_L_0_50_W_10_0_tmp = INTERNAL nhv_L_0_50 == 10.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_10_0 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_10_0_tmp |
| nhv_L_0_50_W_15_0_tmp = INTERNAL nhv_L_0_50 == 15.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_15_0 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_15_0_tmp |
| nhv_L_0_50_W_20_0_tmp = INTERNAL nhv_L_0_50 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_50_W_20_0 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_50_W_20_0_tmp |
| nhv_L_0_60 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 0.6 |
| "k_239_nhv_L_0_60" { |
| @ keep: nhv_L_0_60 - nhv_L_0_60 |
| COPY nhv_L_0_60 |
| } |
| nhv_L_0_60_W_0_42_tmp = INTERNAL nhv_L_0_60 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_60_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_60_W_0_42_tmp |
| nhv_L_0_60_W_0_70_tmp = INTERNAL nhv_L_0_60 == 0.7 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_60_W_0_70 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_60_W_0_70_tmp |
| nhv_L_0_60_W_1_00_tmp = INTERNAL nhv_L_0_60 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_60_W_1_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_60_W_1_00_tmp |
| nhv_L_0_60_W_3_00_tmp = INTERNAL nhv_L_0_60 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_60_W_3_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_60_W_3_00_tmp |
| nhv_L_0_60_W_5_00_tmp = INTERNAL nhv_L_0_60 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_60_W_5_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_60_W_5_00_tmp |
| nhv_L_0_80 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 0.8 |
| "k_240_nhv_L_0_80" { |
| @ keep: nhv_L_0_80 - nhv_L_0_80 |
| COPY nhv_L_0_80 |
| } |
| nhv_L_0_80_W_0_42_tmp = INTERNAL nhv_L_0_80 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_80_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_80_W_0_42_tmp |
| nhv_L_0_80_W_0_75_tmp = INTERNAL nhv_L_0_80 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_80_W_0_75 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_80_W_0_75_tmp |
| nhv_L_0_80_W_1_00_tmp = INTERNAL nhv_L_0_80 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_80_W_1_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_80_W_1_00_tmp |
| nhv_L_0_80_W_5_00_tmp = INTERNAL nhv_L_0_80 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_80_W_5_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_80_W_5_00_tmp |
| nhv_L_0_80_W_7_00_tmp = INTERNAL nhv_L_0_80 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_0_80_W_7_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_0_80_W_7_00_tmp |
| nhv_L_1_00 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_241_nhv_L_1_00" { |
| @ keep: nhv_L_1_00 - nhv_L_1_00 |
| COPY nhv_L_1_00 |
| } |
| nhv_L_1_00_W_0_42_tmp = INTERNAL nhv_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_0_42_tmp |
| nhv_L_1_00_W_0_75_tmp = INTERNAL nhv_L_1_00 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_0_75 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_0_75_tmp |
| nhv_L_1_00_W_1_00_tmp = INTERNAL nhv_L_1_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_1_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_1_00_tmp |
| nhv_L_1_00_W_1_50_tmp = INTERNAL nhv_L_1_00 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_1_50 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_1_50_tmp |
| nhv_L_1_00_W_3_00_tmp = INTERNAL nhv_L_1_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_3_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_3_00_tmp |
| nhv_L_1_00_W_5_00_tmp = INTERNAL nhv_L_1_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_5_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_5_00_tmp |
| nhv_L_1_00_W_7_00_tmp = INTERNAL nhv_L_1_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_7_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_7_00_tmp |
| nhv_L_1_00_W_15_0_tmp = INTERNAL nhv_L_1_00 == 15.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_15_0 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_15_0_tmp |
| nhv_L_1_00_W_20_0_tmp = INTERNAL nhv_L_1_00 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_1_00_W_20_0 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_1_00_W_20_0_tmp |
| nhv_L_2_00 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_242_nhv_L_2_00" { |
| @ keep: nhv_L_2_00 - nhv_L_2_00 |
| COPY nhv_L_2_00 |
| } |
| nhv_L_2_00_W_0_42_tmp = INTERNAL nhv_L_2_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_2_00_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_2_00_W_0_42_tmp |
| nhv_L_2_00_W_0_75_tmp = INTERNAL nhv_L_2_00 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_2_00_W_0_75 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_2_00_W_0_75_tmp |
| nhv_L_2_00_W_1_00_tmp = INTERNAL nhv_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_2_00_W_1_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_2_00_W_1_00_tmp |
| nhv_L_2_00_W_1_50_tmp = INTERNAL nhv_L_2_00 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_2_00_W_1_50 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_2_00_W_1_50_tmp |
| nhv_L_2_00_W_3_00_tmp = INTERNAL nhv_L_2_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_2_00_W_3_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_2_00_W_3_00_tmp |
| nhv_L_2_00_W_5_00_tmp = INTERNAL nhv_L_2_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_2_00_W_5_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_2_00_W_5_00_tmp |
| nhv_L_2_00_W_7_00_tmp = INTERNAL nhv_L_2_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_2_00_W_7_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_2_00_W_7_00_tmp |
| nhv_L_4_00 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_243_nhv_L_4_00" { |
| @ keep: nhv_L_4_00 - nhv_L_4_00 |
| COPY nhv_L_4_00 |
| } |
| nhv_L_4_00_W_0_42_tmp = INTERNAL nhv_L_4_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_4_00_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_4_00_W_0_42_tmp |
| nhv_L_4_00_W_0_75_tmp = INTERNAL nhv_L_4_00 == 0.75 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_4_00_W_0_75 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_4_00_W_0_75_tmp |
| nhv_L_4_00_W_1_00_tmp = INTERNAL nhv_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_4_00_W_1_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_4_00_W_1_00_tmp |
| nhv_L_4_00_W_1_50_tmp = INTERNAL nhv_L_4_00 == 1.5 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_4_00_W_1_50 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_4_00_W_1_50_tmp |
| nhv_L_4_00_W_3_00_tmp = INTERNAL nhv_L_4_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_4_00_W_3_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_4_00_W_3_00_tmp |
| nhv_L_4_00_W_5_00_tmp = INTERNAL nhv_L_4_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_4_00_W_5_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_4_00_W_5_00_tmp |
| nhv_L_4_00_W_7_00_tmp = INTERNAL nhv_L_4_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_4_00_W_7_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_4_00_W_7_00_tmp |
| nhv_L_8_00 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_244_nhv_L_8_00" { |
| @ keep: nhv_L_8_00 - nhv_L_8_00 |
| COPY nhv_L_8_00 |
| } |
| nhv_L_8_00_W_0_42_tmp = INTERNAL nhv_L_8_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_8_00_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_8_00_W_0_42_tmp |
| nhv_L_8_00_W_1_00_tmp = INTERNAL nhv_L_8_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_8_00_W_1_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_8_00_W_1_00_tmp |
| nhv_L_8_00_W_3_00_tmp = INTERNAL nhv_L_8_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_8_00_W_3_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_8_00_W_3_00_tmp |
| nhv_L_8_00_W_5_00_tmp = INTERNAL nhv_L_8_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_8_00_W_5_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_8_00_W_5_00_tmp |
| nhv_L_8_00_W_7_00_tmp = INTERNAL nhv_L_8_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_8_00_W_7_00 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_8_00_W_7_00_tmp |
| nhv_L_20_0 = LENGTH ("nhv" COINCIDENT INSIDE EDGE diff) == 20.0 |
| "k_245_nhv_L_20_0" { |
| @ keep: nhv_L_20_0 - nhv_L_20_0 |
| COPY nhv_L_20_0 |
| } |
| nhv_L_20_0_W_0_42_tmp = INTERNAL nhv_L_20_0 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nhv_L_20_0_W_0_42 = (WITH TEXT "nhv" "dummy_poly" textlabel) OR nhv_L_20_0_W_0_42_tmp |
| nhv_valid = nhv_L_20_0_W_0_42 OR |
| (nhv_L_8_00_W_7_00 OR |
| (nhv_L_8_00_W_5_00 OR |
| (nhv_L_8_00_W_3_00 OR |
| (nhv_L_8_00_W_1_00 OR |
| (nhv_L_8_00_W_0_42 OR |
| (nhv_L_4_00_W_7_00 OR |
| (nhv_L_4_00_W_5_00 OR |
| (nhv_L_4_00_W_3_00 OR |
| (nhv_L_4_00_W_1_50 OR |
| (nhv_L_4_00_W_1_00 OR |
| (nhv_L_4_00_W_0_75 OR |
| (nhv_L_4_00_W_0_42 OR |
| (nhv_L_2_00_W_7_00 OR |
| (nhv_L_2_00_W_5_00 OR |
| (nhv_L_2_00_W_3_00 OR |
| (nhv_L_2_00_W_1_50 OR |
| (nhv_L_2_00_W_1_00 OR |
| (nhv_L_2_00_W_0_75 OR |
| (nhv_L_2_00_W_0_42 OR |
| (nhv_L_1_00_W_20_0 OR |
| (nhv_L_1_00_W_15_0 OR |
| (nhv_L_1_00_W_7_00 OR |
| (nhv_L_1_00_W_5_00 OR |
| (nhv_L_1_00_W_3_00 OR |
| (nhv_L_1_00_W_1_50 OR |
| (nhv_L_1_00_W_1_00 OR |
| (nhv_L_1_00_W_0_75 OR |
| (nhv_L_1_00_W_0_42 OR |
| (nhv_L_0_80_W_7_00 OR |
| (nhv_L_0_80_W_5_00 OR |
| (nhv_L_0_80_W_1_00 OR |
| (nhv_L_0_80_W_0_75 OR |
| (nhv_L_0_80_W_0_42 OR |
| (nhv_L_0_60_W_5_00 OR |
| (nhv_L_0_60_W_3_00 OR |
| (nhv_L_0_60_W_1_00 OR |
| (nhv_L_0_60_W_0_70 OR |
| (nhv_L_0_60_W_0_42 OR |
| (nhv_L_0_50_W_20_0 OR |
| (nhv_L_0_50_W_15_0 OR |
| (nhv_L_0_50_W_10_0 OR |
| (nhv_L_0_50_W_7_00 OR |
| (nhv_L_0_50_W_5_00 OR |
| (nhv_L_0_50_W_3_00 OR |
| (nhv_L_0_50_W_1_50 OR |
| (nhv_L_0_50_W_1_00 OR |
| (nhv_L_0_50_W_0_75 OR nhv_L_0_50_W_0_42))))))))))))))))))))))))))))))))))))))))))))))) |
| "k_246_nhv_valid" { |
| @ keep: nhv_valid - nhv_valid |
| COPY nhv_valid |
| } |
| nhv_invalid = nhv NOT (exemptDecaps OR nhv_valid) |
| "r_613_Poly.X.1" { |
| @ Poly.X.1: This nhv device has an invalid W/L. Please see MRGA |
| COPY nhv_invalid |
| } |
| s8rf_nshort_W5p0_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W5p0_L0p15_M2_b") |
| "k_247_s8rf_nshort_W5p0_L0p15_M2_b" { |
| @ keep: s8rf_nshort_W5p0_L0p15_M2_b - s8rf_nshort_W5p0_L0p15_M2_b |
| COPY s8rf_nshort_W5p0_L0p15_M2_b |
| } |
| s8rf_nshort_W5p0_L0p15_M2_b_L_0_15 = LENGTH (s8rf_nshort_W5p0_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_248_s8rf_nshort_W5p0_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_nshort_W5p0_L0p15_M2_b_L_0_15 - s8rf_nshort_W5p0_L0p15_M2_b_L_0_15 |
| COPY s8rf_nshort_W5p0_L0p15_M2_b_L_0_15 |
| } |
| s8rf_nshort_W5p0_L0p15_M2_b_L_0_15_W_5_05_tmp = INTERNAL s8rf_nshort_W5p0_L0p15_M2_b_L_0_15 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W5p0_L0p15_M2_b_L_0_15_W_5_05 = (WITH TEXT s8rf_nshort_W5p0_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W5p0_L0p15_M2_b_L_0_15_W_5_05_tmp |
| s8rf_nshort_W5p0_L0p15_M2_b_valid = COPY s8rf_nshort_W5p0_L0p15_M2_b_L_0_15_W_5_05 |
| "k_249_s8rf_nshort_W5p0_L0p15_M2_b_valid" { |
| @ keep: s8rf_nshort_W5p0_L0p15_M2_b_valid - s8rf_nshort_W5p0_L0p15_M2_b_valid |
| COPY s8rf_nshort_W5p0_L0p15_M2_b_valid |
| } |
| s8rf_nshort_W5p0_L0p15_M2_b_invalid = s8rf_nshort_W5p0_L0p15_M2_b NOT (exemptDecaps OR s8rf_nshort_W5p0_L0p15_M2_b_valid) |
| "r_614_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W5p0_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W5p0_L0p15_M2_b_invalid |
| } |
| s8rf_nhv_W5p0_L0p5_M2_b = rfGate AND (EXTENT CELL "s8rf_nhv_W5p0_L0p5_M2_b") |
| "k_250_s8rf_nhv_W5p0_L0p5_M2_b" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M2_b - s8rf_nhv_W5p0_L0p5_M2_b |
| COPY s8rf_nhv_W5p0_L0p5_M2_b |
| } |
| s8rf_nhv_W5p0_L0p5_M2_b_L_0_50 = LENGTH (s8rf_nhv_W5p0_L0p5_M2_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_251_s8rf_nhv_W5p0_L0p5_M2_b_L_0_50" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M2_b_L_0_50 - s8rf_nhv_W5p0_L0p5_M2_b_L_0_50 |
| COPY s8rf_nhv_W5p0_L0p5_M2_b_L_0_50 |
| } |
| s8rf_nhv_W5p0_L0p5_M2_b_L_0_50_W_5_05_tmp = INTERNAL s8rf_nhv_W5p0_L0p5_M2_b_L_0_50 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W5p0_L0p5_M2_b_L_0_50_W_5_05 = (WITH TEXT s8rf_nhv_W5p0_L0p5_M2_b "dummy_poly" textlabel) OR s8rf_nhv_W5p0_L0p5_M2_b_L_0_50_W_5_05_tmp |
| s8rf_nhv_W5p0_L0p5_M2_b_valid = COPY s8rf_nhv_W5p0_L0p5_M2_b_L_0_50_W_5_05 |
| "k_252_s8rf_nhv_W5p0_L0p5_M2_b_valid" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M2_b_valid - s8rf_nhv_W5p0_L0p5_M2_b_valid |
| COPY s8rf_nhv_W5p0_L0p5_M2_b_valid |
| } |
| s8rf_nhv_W5p0_L0p5_M2_b_invalid = s8rf_nhv_W5p0_L0p5_M2_b NOT (exemptDecaps OR s8rf_nhv_W5p0_L0p5_M2_b_valid) |
| "r_615_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W5p0_L0p5_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W5p0_L0p5_M2_b_invalid |
| } |
| s8rf_nlowvt_W0p84_L0p15_8F = rfGate AND (EXTENT CELL "s8rf_nlowvt_W0p84_L0p15_8F") |
| "k_253_s8rf_nlowvt_W0p84_L0p15_8F" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_8F - s8rf_nlowvt_W0p84_L0p15_8F |
| COPY s8rf_nlowvt_W0p84_L0p15_8F |
| } |
| s8rf_nlowvt_W0p84_L0p15_8F_L_0_15 = LENGTH (s8rf_nlowvt_W0p84_L0p15_8F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_254_s8rf_nlowvt_W0p84_L0p15_8F_L_0_15" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_8F_L_0_15 - s8rf_nlowvt_W0p84_L0p15_8F_L_0_15 |
| COPY s8rf_nlowvt_W0p84_L0p15_8F_L_0_15 |
| } |
| s8rf_nlowvt_W0p84_L0p15_8F_L_0_15_W_0_84_tmp = INTERNAL s8rf_nlowvt_W0p84_L0p15_8F_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W0p84_L0p15_8F_L_0_15_W_0_84 = (WITH TEXT s8rf_nlowvt_W0p84_L0p15_8F "dummy_poly" textlabel) OR s8rf_nlowvt_W0p84_L0p15_8F_L_0_15_W_0_84_tmp |
| s8rf_nlowvt_W0p84_L0p15_8F_valid = COPY s8rf_nlowvt_W0p84_L0p15_8F_L_0_15_W_0_84 |
| "k_255_s8rf_nlowvt_W0p84_L0p15_8F_valid" { |
| @ keep: s8rf_nlowvt_W0p84_L0p15_8F_valid - s8rf_nlowvt_W0p84_L0p15_8F_valid |
| COPY s8rf_nlowvt_W0p84_L0p15_8F_valid |
| } |
| s8rf_nlowvt_W0p84_L0p15_8F_invalid = s8rf_nlowvt_W0p84_L0p15_8F NOT (exemptDecaps OR s8rf_nlowvt_W0p84_L0p15_8F_valid) |
| "r_616_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W0p84_L0p15_8F device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W0p84_L0p15_8F_invalid |
| } |
| s8rf_nshort_W1p65_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W1p65_L0p15_M4_b") |
| "k_256_s8rf_nshort_W1p65_L0p15_M4_b" { |
| @ keep: s8rf_nshort_W1p65_L0p15_M4_b - s8rf_nshort_W1p65_L0p15_M4_b |
| COPY s8rf_nshort_W1p65_L0p15_M4_b |
| } |
| s8rf_nshort_W1p65_L0p15_M4_b_L_0_15 = LENGTH (s8rf_nshort_W1p65_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_257_s8rf_nshort_W1p65_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_nshort_W1p65_L0p15_M4_b_L_0_15 - s8rf_nshort_W1p65_L0p15_M4_b_L_0_15 |
| COPY s8rf_nshort_W1p65_L0p15_M4_b_L_0_15 |
| } |
| s8rf_nshort_W1p65_L0p15_M4_b_L_0_15_W_1_65_tmp = INTERNAL s8rf_nshort_W1p65_L0p15_M4_b_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W1p65_L0p15_M4_b_L_0_15_W_1_65 = (WITH TEXT s8rf_nshort_W1p65_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W1p65_L0p15_M4_b_L_0_15_W_1_65_tmp |
| s8rf_nshort_W1p65_L0p15_M4_b_valid = COPY s8rf_nshort_W1p65_L0p15_M4_b_L_0_15_W_1_65 |
| "k_258_s8rf_nshort_W1p65_L0p15_M4_b_valid" { |
| @ keep: s8rf_nshort_W1p65_L0p15_M4_b_valid - s8rf_nshort_W1p65_L0p15_M4_b_valid |
| COPY s8rf_nshort_W1p65_L0p15_M4_b_valid |
| } |
| s8rf_nshort_W1p65_L0p15_M4_b_invalid = s8rf_nshort_W1p65_L0p15_M4_b NOT (exemptDecaps OR s8rf_nshort_W1p65_L0p15_M4_b_valid) |
| "r_617_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W1p65_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W1p65_L0p15_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p25_M2_b") |
| "k_259_s8rf_nlowvt_W3p0_L0p25_M2_b" { |
| @ keep: s8rf_nlowvt_W3p0_L0p25_M2_b - s8rf_nlowvt_W3p0_L0p25_M2_b |
| COPY s8rf_nlowvt_W3p0_L0p25_M2_b |
| } |
| s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25 = LENGTH (s8rf_nlowvt_W3p0_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_260_s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25 - s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25 |
| COPY s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25 |
| } |
| s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25_W_3_01_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25_W_3_01 = (WITH TEXT s8rf_nlowvt_W3p0_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25_W_3_01_tmp |
| s8rf_nlowvt_W3p0_L0p25_M2_b_valid = COPY s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25_W_3_01 |
| "k_261_s8rf_nlowvt_W3p0_L0p25_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p25_M2_b_valid - s8rf_nlowvt_W3p0_L0p25_M2_b_valid |
| COPY s8rf_nlowvt_W3p0_L0p25_M2_b_valid |
| } |
| s8rf_nlowvt_W3p0_L0p25_M2_b_invalid = s8rf_nlowvt_W3p0_L0p25_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p25_M2_b_valid) |
| "r_618_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p25_M2_b_invalid |
| } |
| s8rf_nlowvt_W5p0_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W5p0_L0p25_M4_b") |
| "k_262_s8rf_nlowvt_W5p0_L0p25_M4_b" { |
| @ keep: s8rf_nlowvt_W5p0_L0p25_M4_b - s8rf_nlowvt_W5p0_L0p25_M4_b |
| COPY s8rf_nlowvt_W5p0_L0p25_M4_b |
| } |
| s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25 = LENGTH (s8rf_nlowvt_W5p0_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_263_s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25 - s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25 |
| COPY s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25 |
| } |
| s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25_W_5_05_tmp = INTERNAL s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25_W_5_05 = (WITH TEXT s8rf_nlowvt_W5p0_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25_W_5_05_tmp |
| s8rf_nlowvt_W5p0_L0p25_M4_b_valid = COPY s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25_W_5_05 |
| "k_264_s8rf_nlowvt_W5p0_L0p25_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W5p0_L0p25_M4_b_valid - s8rf_nlowvt_W5p0_L0p25_M4_b_valid |
| COPY s8rf_nlowvt_W5p0_L0p25_M4_b_valid |
| } |
| s8rf_nlowvt_W5p0_L0p25_M4_b_invalid = s8rf_nlowvt_W5p0_L0p25_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W5p0_L0p25_M4_b_valid) |
| "r_619_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W5p0_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W5p0_L0p25_M4_b_invalid |
| } |
| nshortesd_L_0_165 = LENGTH ("nshortesd" COINCIDENT INSIDE EDGE diff) == 0.165 |
| "k_265_nshortesd_L_0_165" { |
| @ keep: nshortesd_L_0_165 - nshortesd_L_0_165 |
| COPY nshortesd_L_0_165 |
| } |
| nshortesd_L_0_165_W_20_35_tmp = INTERNAL nshortesd_L_0_165 == 20.35 OPPOSITE PARALLEL ONLY REGION |
| nshortesd_L_0_165_W_20_35 = (WITH TEXT "nshortesd" "dummy_poly" textlabel) OR nshortesd_L_0_165_W_20_35_tmp |
| nshortesd_L_0_165_W_40_31_tmp = INTERNAL nshortesd_L_0_165 == 40.31 OPPOSITE PARALLEL ONLY REGION |
| nshortesd_L_0_165_W_40_31 = (WITH TEXT "nshortesd" "dummy_poly" textlabel) OR nshortesd_L_0_165_W_40_31_tmp |
| nshortesd_L_0_18 = LENGTH ("nshortesd" COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_266_nshortesd_L_0_18" { |
| @ keep: nshortesd_L_0_18 - nshortesd_L_0_18 |
| COPY nshortesd_L_0_18 |
| } |
| nshortesd_L_0_18_W_5_40_tmp = INTERNAL nshortesd_L_0_18 == 5.4 OPPOSITE PARALLEL ONLY REGION |
| nshortesd_L_0_18_W_5_40 = (WITH TEXT "nshortesd" "dummy_poly" textlabel) OR nshortesd_L_0_18_W_5_40_tmp |
| nshortesd_valid = nshortesd_L_0_18_W_5_40 OR |
| (nshortesd_L_0_165_W_40_31 OR nshortesd_L_0_165_W_20_35) |
| "k_267_nshortesd_valid" { |
| @ keep: nshortesd_valid - nshortesd_valid |
| COPY nshortesd_valid |
| } |
| nshortesd_invalid = nshortesd NOT (exemptDecaps OR nshortesd_valid) |
| "r_620_Poly.X.1" { |
| @ Poly.X.1: This nshortesd device has an invalid W/L. Please see MRGA |
| COPY nshortesd_invalid |
| } |
| s8rf_nlowvt_W5p0_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W5p0_L0p25_M2_b") |
| "k_268_s8rf_nlowvt_W5p0_L0p25_M2_b" { |
| @ keep: s8rf_nlowvt_W5p0_L0p25_M2_b - s8rf_nlowvt_W5p0_L0p25_M2_b |
| COPY s8rf_nlowvt_W5p0_L0p25_M2_b |
| } |
| s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25 = LENGTH (s8rf_nlowvt_W5p0_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_269_s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25 - s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25 |
| COPY s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25 |
| } |
| s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25_W_5_05_tmp = INTERNAL s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25_W_5_05 = (WITH TEXT s8rf_nlowvt_W5p0_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25_W_5_05_tmp |
| s8rf_nlowvt_W5p0_L0p25_M2_b_valid = COPY s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25_W_5_05 |
| "k_270_s8rf_nlowvt_W5p0_L0p25_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W5p0_L0p25_M2_b_valid - s8rf_nlowvt_W5p0_L0p25_M2_b_valid |
| COPY s8rf_nlowvt_W5p0_L0p25_M2_b_valid |
| } |
| s8rf_nlowvt_W5p0_L0p25_M2_b_invalid = s8rf_nlowvt_W5p0_L0p25_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W5p0_L0p25_M2_b_valid) |
| "r_621_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W5p0_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W5p0_L0p25_M2_b_invalid |
| } |
| s8rf_nshort_W3p0_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W3p0_L0p15_M4_b") |
| "k_271_s8rf_nshort_W3p0_L0p15_M4_b" { |
| @ keep: s8rf_nshort_W3p0_L0p15_M4_b - s8rf_nshort_W3p0_L0p15_M4_b |
| COPY s8rf_nshort_W3p0_L0p15_M4_b |
| } |
| s8rf_nshort_W3p0_L0p15_M4_b_L_0_15 = LENGTH (s8rf_nshort_W3p0_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_272_s8rf_nshort_W3p0_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_nshort_W3p0_L0p15_M4_b_L_0_15 - s8rf_nshort_W3p0_L0p15_M4_b_L_0_15 |
| COPY s8rf_nshort_W3p0_L0p15_M4_b_L_0_15 |
| } |
| s8rf_nshort_W3p0_L0p15_M4_b_L_0_15_W_3_01_tmp = INTERNAL s8rf_nshort_W3p0_L0p15_M4_b_L_0_15 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W3p0_L0p15_M4_b_L_0_15_W_3_01 = (WITH TEXT s8rf_nshort_W3p0_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W3p0_L0p15_M4_b_L_0_15_W_3_01_tmp |
| s8rf_nshort_W3p0_L0p15_M4_b_valid = COPY s8rf_nshort_W3p0_L0p15_M4_b_L_0_15_W_3_01 |
| "k_273_s8rf_nshort_W3p0_L0p15_M4_b_valid" { |
| @ keep: s8rf_nshort_W3p0_L0p15_M4_b_valid - s8rf_nshort_W3p0_L0p15_M4_b_valid |
| COPY s8rf_nshort_W3p0_L0p15_M4_b_valid |
| } |
| s8rf_nshort_W3p0_L0p15_M4_b_invalid = s8rf_nshort_W3p0_L0p15_M4_b NOT (exemptDecaps OR s8rf_nshort_W3p0_L0p15_M4_b_valid) |
| "r_622_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W3p0_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W3p0_L0p15_M4_b_invalid |
| } |
| nshort_L_0_15 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_274_nshort_L_0_15" { |
| @ keep: nshort_L_0_15 - nshort_L_0_15 |
| COPY nshort_L_0_15 |
| } |
| nshort_L_0_15_W_0_36_tmp = INTERNAL nshort_L_0_15 == 0.36 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_36 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_36_tmp |
| nshort_L_0_15_W_0_39_tmp = INTERNAL nshort_L_0_15 == 0.39 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_39 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_39_tmp |
| nshort_L_0_15_W_0_42_tmp = INTERNAL nshort_L_0_15 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_42_tmp |
| nshort_L_0_15_W_0_52_tmp = INTERNAL nshort_L_0_15 == 0.52 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_52 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_52_tmp |
| nshort_L_0_15_W_0_54_tmp = INTERNAL nshort_L_0_15 == 0.54 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_54 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_54_tmp |
| nshort_L_0_15_W_0_55_tmp = INTERNAL nshort_L_0_15 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_55 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_55_tmp |
| nshort_L_0_15_W_0_58_tmp = INTERNAL nshort_L_0_15 == 0.58 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_58 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_58_tmp |
| nshort_L_0_15_W_0_60_tmp = INTERNAL nshort_L_0_15 == 0.6 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_60 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_60_tmp |
| nshort_L_0_15_W_0_61_tmp = INTERNAL nshort_L_0_15 == 0.61 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_61 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_61_tmp |
| nshort_L_0_15_W_0_64_tmp = INTERNAL nshort_L_0_15 == 0.64 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_64 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_64_tmp |
| nshort_L_0_15_W_0_65_tmp = INTERNAL nshort_L_0_15 == 0.65 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_65 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_65_tmp |
| nshort_L_0_15_W_0_74_tmp = INTERNAL nshort_L_0_15 == 0.74 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_74 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_74_tmp |
| nshort_L_0_15_W_0_84_tmp = INTERNAL nshort_L_0_15 == 0.84 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_0_84 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_0_84_tmp |
| nshort_L_0_15_W_1_00_tmp = INTERNAL nshort_L_0_15 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_1_00_tmp |
| nshort_L_0_15_W_1_26_tmp = INTERNAL nshort_L_0_15 == 1.26 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_1_26 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_1_26_tmp |
| nshort_L_0_15_W_1_68_tmp = INTERNAL nshort_L_0_15 == 1.68 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_1_68 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_1_68_tmp |
| nshort_L_0_15_W_2_00_tmp = INTERNAL nshort_L_0_15 == 2.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_2_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_2_00_tmp |
| nshort_L_0_15_W_3_00_tmp = INTERNAL nshort_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_3_00_tmp |
| nshort_L_0_15_W_5_00_tmp = INTERNAL nshort_L_0_15 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_5_00_tmp |
| nshort_L_0_15_W_7_00_tmp = INTERNAL nshort_L_0_15 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_15_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_15_W_7_00_tmp |
| nshort_L_0_18 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_275_nshort_L_0_18" { |
| @ keep: nshort_L_0_18 - nshort_L_0_18 |
| COPY nshort_L_0_18 |
| } |
| nshort_L_0_18_W_0_42_tmp = INTERNAL nshort_L_0_18 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_18_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_18_W_0_42_tmp |
| nshort_L_0_18_W_0_65_tmp = INTERNAL nshort_L_0_18 == 0.65 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_18_W_0_65 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_18_W_0_65_tmp |
| nshort_L_0_18_W_1_00_tmp = INTERNAL nshort_L_0_18 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_18_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_18_W_1_00_tmp |
| nshort_L_0_18_W_3_00_tmp = INTERNAL nshort_L_0_18 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_18_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_18_W_3_00_tmp |
| nshort_L_0_18_W_5_00_tmp = INTERNAL nshort_L_0_18 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_18_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_18_W_5_00_tmp |
| nshort_L_0_18_W_7_00_tmp = INTERNAL nshort_L_0_18 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_18_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_18_W_7_00_tmp |
| nshort_L_0_25 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_276_nshort_L_0_25" { |
| @ keep: nshort_L_0_25 - nshort_L_0_25 |
| COPY nshort_L_0_25 |
| } |
| nshort_L_0_25_W_0_65_tmp = INTERNAL nshort_L_0_25 == 0.65 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_25_W_0_65 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_25_W_0_65_tmp |
| nshort_L_0_25_W_1_00_tmp = INTERNAL nshort_L_0_25 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_25_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_25_W_1_00_tmp |
| nshort_L_0_25_W_3_00_tmp = INTERNAL nshort_L_0_25 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_25_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_25_W_3_00_tmp |
| nshort_L_0_25_W_5_00_tmp = INTERNAL nshort_L_0_25 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_25_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_25_W_5_00_tmp |
| nshort_L_0_25_W_7_00_tmp = INTERNAL nshort_L_0_25 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_25_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_25_W_7_00_tmp |
| nshort_L_0_50 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_277_nshort_L_0_50" { |
| @ keep: nshort_L_0_50 - nshort_L_0_50 |
| COPY nshort_L_0_50 |
| } |
| nshort_L_0_50_W_0_42_tmp = INTERNAL nshort_L_0_50 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_50_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_50_W_0_42_tmp |
| nshort_L_0_50_W_0_55_tmp = INTERNAL nshort_L_0_50 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_50_W_0_55 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_50_W_0_55_tmp |
| nshort_L_0_50_W_0_65_tmp = INTERNAL nshort_L_0_50 == 0.65 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_50_W_0_65 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_50_W_0_65_tmp |
| nshort_L_0_50_W_1_00_tmp = INTERNAL nshort_L_0_50 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_50_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_50_W_1_00_tmp |
| nshort_L_0_50_W_3_00_tmp = INTERNAL nshort_L_0_50 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_50_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_50_W_3_00_tmp |
| nshort_L_0_50_W_5_00_tmp = INTERNAL nshort_L_0_50 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_50_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_50_W_5_00_tmp |
| nshort_L_0_50_W_7_00_tmp = INTERNAL nshort_L_0_50 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_0_50_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_0_50_W_7_00_tmp |
| nshort_L_1_00 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_278_nshort_L_1_00" { |
| @ keep: nshort_L_1_00 - nshort_L_1_00 |
| COPY nshort_L_1_00 |
| } |
| nshort_L_1_00_W_0_42_tmp = INTERNAL nshort_L_1_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_1_00_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_1_00_W_0_42_tmp |
| nshort_L_1_00_W_0_55_tmp = INTERNAL nshort_L_1_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_1_00_W_0_55 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_1_00_W_0_55_tmp |
| nshort_L_1_00_W_1_00_tmp = INTERNAL nshort_L_1_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_1_00_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_1_00_W_1_00_tmp |
| nshort_L_1_00_W_3_00_tmp = INTERNAL nshort_L_1_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_1_00_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_1_00_W_3_00_tmp |
| nshort_L_1_00_W_5_00_tmp = INTERNAL nshort_L_1_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_1_00_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_1_00_W_5_00_tmp |
| nshort_L_1_00_W_7_00_tmp = INTERNAL nshort_L_1_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_1_00_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_1_00_W_7_00_tmp |
| nshort_L_2_00 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 2.0 |
| "k_279_nshort_L_2_00" { |
| @ keep: nshort_L_2_00 - nshort_L_2_00 |
| COPY nshort_L_2_00 |
| } |
| nshort_L_2_00_W_0_42_tmp = INTERNAL nshort_L_2_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_2_00_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_2_00_W_0_42_tmp |
| nshort_L_2_00_W_0_55_tmp = INTERNAL nshort_L_2_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_2_00_W_0_55 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_2_00_W_0_55_tmp |
| nshort_L_2_00_W_1_00_tmp = INTERNAL nshort_L_2_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_2_00_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_2_00_W_1_00_tmp |
| nshort_L_2_00_W_3_00_tmp = INTERNAL nshort_L_2_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_2_00_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_2_00_W_3_00_tmp |
| nshort_L_2_00_W_5_00_tmp = INTERNAL nshort_L_2_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_2_00_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_2_00_W_5_00_tmp |
| nshort_L_2_00_W_7_00_tmp = INTERNAL nshort_L_2_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_2_00_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_2_00_W_7_00_tmp |
| nshort_L_4_00 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 4.0 |
| "k_280_nshort_L_4_00" { |
| @ keep: nshort_L_4_00 - nshort_L_4_00 |
| COPY nshort_L_4_00 |
| } |
| nshort_L_4_00_W_0_42_tmp = INTERNAL nshort_L_4_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_4_00_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_4_00_W_0_42_tmp |
| nshort_L_4_00_W_0_55_tmp = INTERNAL nshort_L_4_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_4_00_W_0_55 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_4_00_W_0_55_tmp |
| nshort_L_4_00_W_1_00_tmp = INTERNAL nshort_L_4_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_4_00_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_4_00_W_1_00_tmp |
| nshort_L_4_00_W_3_00_tmp = INTERNAL nshort_L_4_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_4_00_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_4_00_W_3_00_tmp |
| nshort_L_4_00_W_5_00_tmp = INTERNAL nshort_L_4_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_4_00_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_4_00_W_5_00_tmp |
| nshort_L_4_00_W_7_00_tmp = INTERNAL nshort_L_4_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_4_00_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_4_00_W_7_00_tmp |
| nshort_L_8_00 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 8.0 |
| "k_281_nshort_L_8_00" { |
| @ keep: nshort_L_8_00 - nshort_L_8_00 |
| COPY nshort_L_8_00 |
| } |
| nshort_L_8_00_W_0_42_tmp = INTERNAL nshort_L_8_00 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_8_00_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_8_00_W_0_42_tmp |
| nshort_L_8_00_W_0_55_tmp = INTERNAL nshort_L_8_00 == 0.55 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_8_00_W_0_55 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_8_00_W_0_55_tmp |
| nshort_L_8_00_W_1_00_tmp = INTERNAL nshort_L_8_00 == 1.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_8_00_W_1_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_8_00_W_1_00_tmp |
| nshort_L_8_00_W_3_00_tmp = INTERNAL nshort_L_8_00 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_8_00_W_3_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_8_00_W_3_00_tmp |
| nshort_L_8_00_W_5_00_tmp = INTERNAL nshort_L_8_00 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_8_00_W_5_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_8_00_W_5_00_tmp |
| nshort_L_8_00_W_7_00_tmp = INTERNAL nshort_L_8_00 == 7.0 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_8_00_W_7_00 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_8_00_W_7_00_tmp |
| nshort_L_20_0 = LENGTH ("nshort" COINCIDENT INSIDE EDGE diff) == 20.0 |
| "k_282_nshort_L_20_0" { |
| @ keep: nshort_L_20_0 - nshort_L_20_0 |
| COPY nshort_L_20_0 |
| } |
| nshort_L_20_0_W_0_42_tmp = INTERNAL nshort_L_20_0 == 0.42 OPPOSITE PARALLEL ONLY REGION |
| nshort_L_20_0_W_0_42 = (WITH TEXT "nshort" "dummy_poly" textlabel) OR nshort_L_20_0_W_0_42_tmp |
| nshort_valid = nshort_L_20_0_W_0_42 OR |
| (nshort_L_8_00_W_7_00 OR |
| (nshort_L_8_00_W_5_00 OR |
| (nshort_L_8_00_W_3_00 OR |
| (nshort_L_8_00_W_1_00 OR |
| (nshort_L_8_00_W_0_55 OR |
| (nshort_L_8_00_W_0_42 OR |
| (nshort_L_4_00_W_7_00 OR |
| (nshort_L_4_00_W_5_00 OR |
| (nshort_L_4_00_W_3_00 OR |
| (nshort_L_4_00_W_1_00 OR |
| (nshort_L_4_00_W_0_55 OR |
| (nshort_L_4_00_W_0_42 OR |
| (nshort_L_2_00_W_7_00 OR |
| (nshort_L_2_00_W_5_00 OR |
| (nshort_L_2_00_W_3_00 OR |
| (nshort_L_2_00_W_1_00 OR |
| (nshort_L_2_00_W_0_55 OR |
| (nshort_L_2_00_W_0_42 OR |
| (nshort_L_1_00_W_7_00 OR |
| (nshort_L_1_00_W_5_00 OR |
| (nshort_L_1_00_W_3_00 OR |
| (nshort_L_1_00_W_1_00 OR |
| (nshort_L_1_00_W_0_55 OR |
| (nshort_L_1_00_W_0_42 OR |
| (nshort_L_0_50_W_7_00 OR |
| (nshort_L_0_50_W_5_00 OR |
| (nshort_L_0_50_W_3_00 OR |
| (nshort_L_0_50_W_1_00 OR |
| (nshort_L_0_50_W_0_65 OR |
| (nshort_L_0_50_W_0_55 OR |
| (nshort_L_0_50_W_0_42 OR |
| (nshort_L_0_25_W_7_00 OR |
| (nshort_L_0_25_W_5_00 OR |
| (nshort_L_0_25_W_3_00 OR |
| (nshort_L_0_25_W_1_00 OR |
| (nshort_L_0_25_W_0_65 OR |
| (nshort_L_0_18_W_7_00 OR |
| (nshort_L_0_18_W_5_00 OR |
| (nshort_L_0_18_W_3_00 OR |
| (nshort_L_0_18_W_1_00 OR |
| (nshort_L_0_18_W_0_65 OR |
| (nshort_L_0_18_W_0_42 OR |
| (nshort_L_0_15_W_7_00 OR |
| (nshort_L_0_15_W_5_00 OR |
| (nshort_L_0_15_W_3_00 OR |
| (nshort_L_0_15_W_2_00 OR |
| (nshort_L_0_15_W_1_68 OR |
| (nshort_L_0_15_W_1_26 OR |
| (nshort_L_0_15_W_1_00 OR |
| (nshort_L_0_15_W_0_84 OR |
| (nshort_L_0_15_W_0_74 OR |
| (nshort_L_0_15_W_0_65 OR |
| (nshort_L_0_15_W_0_64 OR |
| (nshort_L_0_15_W_0_61 OR |
| (nshort_L_0_15_W_0_60 OR |
| (nshort_L_0_15_W_0_58 OR |
| (nshort_L_0_15_W_0_55 OR |
| (nshort_L_0_15_W_0_54 OR |
| (nshort_L_0_15_W_0_52 OR |
| (nshort_L_0_15_W_0_42 OR |
| (nshort_L_0_15_W_0_39 OR nshort_L_0_15_W_0_36))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) |
| "k_283_nshort_valid" { |
| @ keep: nshort_valid - nshort_valid |
| COPY nshort_valid |
| } |
| nshort_invalid = nshort NOT (exemptDecaps OR nshort_valid) |
| "r_623_Poly.X.1" { |
| @ Poly.X.1: This nshort device has an invalid W/L. Please see MRGA |
| COPY nshort_invalid |
| } |
| s8rf_nshort_W5p0_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W5p0_L0p18_M4_b") |
| "k_284_s8rf_nshort_W5p0_L0p18_M4_b" { |
| @ keep: s8rf_nshort_W5p0_L0p18_M4_b - s8rf_nshort_W5p0_L0p18_M4_b |
| COPY s8rf_nshort_W5p0_L0p18_M4_b |
| } |
| s8rf_nshort_W5p0_L0p18_M4_b_L_0_18 = LENGTH (s8rf_nshort_W5p0_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_285_s8rf_nshort_W5p0_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_nshort_W5p0_L0p18_M4_b_L_0_18 - s8rf_nshort_W5p0_L0p18_M4_b_L_0_18 |
| COPY s8rf_nshort_W5p0_L0p18_M4_b_L_0_18 |
| } |
| s8rf_nshort_W5p0_L0p18_M4_b_L_0_18_W_5_05_tmp = INTERNAL s8rf_nshort_W5p0_L0p18_M4_b_L_0_18 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W5p0_L0p18_M4_b_L_0_18_W_5_05 = (WITH TEXT s8rf_nshort_W5p0_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W5p0_L0p18_M4_b_L_0_18_W_5_05_tmp |
| s8rf_nshort_W5p0_L0p18_M4_b_valid = COPY s8rf_nshort_W5p0_L0p18_M4_b_L_0_18_W_5_05 |
| "k_286_s8rf_nshort_W5p0_L0p18_M4_b_valid" { |
| @ keep: s8rf_nshort_W5p0_L0p18_M4_b_valid - s8rf_nshort_W5p0_L0p18_M4_b_valid |
| COPY s8rf_nshort_W5p0_L0p18_M4_b_valid |
| } |
| s8rf_nshort_W5p0_L0p18_M4_b_invalid = s8rf_nshort_W5p0_L0p18_M4_b NOT (exemptDecaps OR s8rf_nshort_W5p0_L0p18_M4_b_valid) |
| "r_624_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W5p0_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W5p0_L0p18_M4_b_invalid |
| } |
| s8rf_nlowvt_W1p65_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W1p65_L0p25_M2_b") |
| "k_287_s8rf_nlowvt_W1p65_L0p25_M2_b" { |
| @ keep: s8rf_nlowvt_W1p65_L0p25_M2_b - s8rf_nlowvt_W1p65_L0p25_M2_b |
| COPY s8rf_nlowvt_W1p65_L0p25_M2_b |
| } |
| s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25 = LENGTH (s8rf_nlowvt_W1p65_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_288_s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25 - s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25 |
| COPY s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25 |
| } |
| s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25_W_1_65_tmp = INTERNAL s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25_W_1_65 = (WITH TEXT s8rf_nlowvt_W1p65_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25_W_1_65_tmp |
| s8rf_nlowvt_W1p65_L0p25_M2_b_valid = COPY s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25_W_1_65 |
| "k_289_s8rf_nlowvt_W1p65_L0p25_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W1p65_L0p25_M2_b_valid - s8rf_nlowvt_W1p65_L0p25_M2_b_valid |
| COPY s8rf_nlowvt_W1p65_L0p25_M2_b_valid |
| } |
| s8rf_nlowvt_W1p65_L0p25_M2_b_invalid = s8rf_nlowvt_W1p65_L0p25_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W1p65_L0p25_M2_b_valid) |
| "r_625_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W1p65_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W1p65_L0p25_M2_b_invalid |
| } |
| s8rf_nhv_W5p0_L0p5_M10_b = rfGate AND (EXTENT CELL "s8rf_nhv_W5p0_L0p5_M10_b") |
| "k_290_s8rf_nhv_W5p0_L0p5_M10_b" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M10_b - s8rf_nhv_W5p0_L0p5_M10_b |
| COPY s8rf_nhv_W5p0_L0p5_M10_b |
| } |
| s8rf_nhv_W5p0_L0p5_M10_b_L_0_50 = LENGTH (s8rf_nhv_W5p0_L0p5_M10_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_291_s8rf_nhv_W5p0_L0p5_M10_b_L_0_50" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M10_b_L_0_50 - s8rf_nhv_W5p0_L0p5_M10_b_L_0_50 |
| COPY s8rf_nhv_W5p0_L0p5_M10_b_L_0_50 |
| } |
| s8rf_nhv_W5p0_L0p5_M10_b_L_0_50_W_5_05_tmp = INTERNAL s8rf_nhv_W5p0_L0p5_M10_b_L_0_50 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W5p0_L0p5_M10_b_L_0_50_W_5_05 = (WITH TEXT s8rf_nhv_W5p0_L0p5_M10_b "dummy_poly" textlabel) OR s8rf_nhv_W5p0_L0p5_M10_b_L_0_50_W_5_05_tmp |
| s8rf_nhv_W5p0_L0p5_M10_b_valid = COPY s8rf_nhv_W5p0_L0p5_M10_b_L_0_50_W_5_05 |
| "k_292_s8rf_nhv_W5p0_L0p5_M10_b_valid" { |
| @ keep: s8rf_nhv_W5p0_L0p5_M10_b_valid - s8rf_nhv_W5p0_L0p5_M10_b_valid |
| COPY s8rf_nhv_W5p0_L0p5_M10_b_valid |
| } |
| s8rf_nhv_W5p0_L0p5_M10_b_invalid = s8rf_nhv_W5p0_L0p5_M10_b NOT (exemptDecaps OR s8rf_nhv_W5p0_L0p5_M10_b_valid) |
| "r_626_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W5p0_L0p5_M10_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W5p0_L0p5_M10_b_invalid |
| } |
| s8rf_nshort_W3p0_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_nshort_W3p0_L0p25_M4_b") |
| "k_293_s8rf_nshort_W3p0_L0p25_M4_b" { |
| @ keep: s8rf_nshort_W3p0_L0p25_M4_b - s8rf_nshort_W3p0_L0p25_M4_b |
| COPY s8rf_nshort_W3p0_L0p25_M4_b |
| } |
| s8rf_nshort_W3p0_L0p25_M4_b_L_0_25 = LENGTH (s8rf_nshort_W3p0_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_294_s8rf_nshort_W3p0_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_nshort_W3p0_L0p25_M4_b_L_0_25 - s8rf_nshort_W3p0_L0p25_M4_b_L_0_25 |
| COPY s8rf_nshort_W3p0_L0p25_M4_b_L_0_25 |
| } |
| s8rf_nshort_W3p0_L0p25_M4_b_L_0_25_W_3_01_tmp = INTERNAL s8rf_nshort_W3p0_L0p25_M4_b_L_0_25 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W3p0_L0p25_M4_b_L_0_25_W_3_01 = (WITH TEXT s8rf_nshort_W3p0_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_nshort_W3p0_L0p25_M4_b_L_0_25_W_3_01_tmp |
| s8rf_nshort_W3p0_L0p25_M4_b_valid = COPY s8rf_nshort_W3p0_L0p25_M4_b_L_0_25_W_3_01 |
| "k_295_s8rf_nshort_W3p0_L0p25_M4_b_valid" { |
| @ keep: s8rf_nshort_W3p0_L0p25_M4_b_valid - s8rf_nshort_W3p0_L0p25_M4_b_valid |
| COPY s8rf_nshort_W3p0_L0p25_M4_b_valid |
| } |
| s8rf_nshort_W3p0_L0p25_M4_b_invalid = s8rf_nshort_W3p0_L0p25_M4_b NOT (exemptDecaps OR s8rf_nshort_W3p0_L0p25_M4_b_valid) |
| "r_627_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W3p0_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W3p0_L0p25_M4_b_invalid |
| } |
| s8rf_nhv_W3p0_L0p5_M2_b = rfGate AND (EXTENT CELL "s8rf_nhv_W3p0_L0p5_M2_b") |
| "k_296_s8rf_nhv_W3p0_L0p5_M2_b" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M2_b - s8rf_nhv_W3p0_L0p5_M2_b |
| COPY s8rf_nhv_W3p0_L0p5_M2_b |
| } |
| s8rf_nhv_W3p0_L0p5_M2_b_L_0_50 = LENGTH (s8rf_nhv_W3p0_L0p5_M2_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_297_s8rf_nhv_W3p0_L0p5_M2_b_L_0_50" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M2_b_L_0_50 - s8rf_nhv_W3p0_L0p5_M2_b_L_0_50 |
| COPY s8rf_nhv_W3p0_L0p5_M2_b_L_0_50 |
| } |
| s8rf_nhv_W3p0_L0p5_M2_b_L_0_50_W_3_01_tmp = INTERNAL s8rf_nhv_W3p0_L0p5_M2_b_L_0_50 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W3p0_L0p5_M2_b_L_0_50_W_3_01 = (WITH TEXT s8rf_nhv_W3p0_L0p5_M2_b "dummy_poly" textlabel) OR s8rf_nhv_W3p0_L0p5_M2_b_L_0_50_W_3_01_tmp |
| s8rf_nhv_W3p0_L0p5_M2_b_valid = COPY s8rf_nhv_W3p0_L0p5_M2_b_L_0_50_W_3_01 |
| "k_298_s8rf_nhv_W3p0_L0p5_M2_b_valid" { |
| @ keep: s8rf_nhv_W3p0_L0p5_M2_b_valid - s8rf_nhv_W3p0_L0p5_M2_b_valid |
| COPY s8rf_nhv_W3p0_L0p5_M2_b_valid |
| } |
| s8rf_nhv_W3p0_L0p5_M2_b_invalid = s8rf_nhv_W3p0_L0p5_M2_b NOT (exemptDecaps OR s8rf_nhv_W3p0_L0p5_M2_b_valid) |
| "r_628_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W3p0_L0p5_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W3p0_L0p5_M2_b_invalid |
| } |
| s8rf_nlowvt_W1p65_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W1p65_L0p18_M2_b") |
| "k_299_s8rf_nlowvt_W1p65_L0p18_M2_b" { |
| @ keep: s8rf_nlowvt_W1p65_L0p18_M2_b - s8rf_nlowvt_W1p65_L0p18_M2_b |
| COPY s8rf_nlowvt_W1p65_L0p18_M2_b |
| } |
| s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18 = LENGTH (s8rf_nlowvt_W1p65_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_300_s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18 - s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18 |
| COPY s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18 |
| } |
| s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18_W_1_65_tmp = INTERNAL s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18_W_1_65 = (WITH TEXT s8rf_nlowvt_W1p65_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18_W_1_65_tmp |
| s8rf_nlowvt_W1p65_L0p18_M2_b_valid = COPY s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18_W_1_65 |
| "k_301_s8rf_nlowvt_W1p65_L0p18_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W1p65_L0p18_M2_b_valid - s8rf_nlowvt_W1p65_L0p18_M2_b_valid |
| COPY s8rf_nlowvt_W1p65_L0p18_M2_b_valid |
| } |
| s8rf_nlowvt_W1p65_L0p18_M2_b_invalid = s8rf_nlowvt_W1p65_L0p18_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W1p65_L0p18_M2_b_valid) |
| "r_629_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W1p65_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W1p65_L0p18_M2_b_invalid |
| } |
| nlvtpass_L_0_15 = LENGTH ("nlvtpass" COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_302_nlvtpass_L_0_15" { |
| @ keep: nlvtpass_L_0_15 - nlvtpass_L_0_15 |
| COPY nlvtpass_L_0_15 |
| } |
| nlvtpass_L_0_15_W_0_30_tmp = INTERNAL nlvtpass_L_0_15 == 0.3 OPPOSITE PARALLEL ONLY REGION |
| nlvtpass_L_0_15_W_0_30 = (WITH TEXT "nlvtpass" "dummy_poly" textlabel) OR nlvtpass_L_0_15_W_0_30_tmp |
| nlvtpass_valid = COPY nlvtpass_L_0_15_W_0_30 |
| "k_303_nlvtpass_valid" { |
| @ keep: nlvtpass_valid - nlvtpass_valid |
| COPY nlvtpass_valid |
| } |
| nlvtpass_invalid = nlvtpass NOT (exemptDecaps OR nlvtpass_valid) |
| "r_630_Poly.X.1" { |
| @ Poly.X.1: This nlvtpass device has an invalid W/L. Please see MRGA |
| COPY nlvtpass_invalid |
| } |
| s8rf_nshort_W1p65_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W1p65_L0p18_M2_b") |
| "k_304_s8rf_nshort_W1p65_L0p18_M2_b" { |
| @ keep: s8rf_nshort_W1p65_L0p18_M2_b - s8rf_nshort_W1p65_L0p18_M2_b |
| COPY s8rf_nshort_W1p65_L0p18_M2_b |
| } |
| s8rf_nshort_W1p65_L0p18_M2_b_L_0_18 = LENGTH (s8rf_nshort_W1p65_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_305_s8rf_nshort_W1p65_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_nshort_W1p65_L0p18_M2_b_L_0_18 - s8rf_nshort_W1p65_L0p18_M2_b_L_0_18 |
| COPY s8rf_nshort_W1p65_L0p18_M2_b_L_0_18 |
| } |
| s8rf_nshort_W1p65_L0p18_M2_b_L_0_18_W_1_65_tmp = INTERNAL s8rf_nshort_W1p65_L0p18_M2_b_L_0_18 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W1p65_L0p18_M2_b_L_0_18_W_1_65 = (WITH TEXT s8rf_nshort_W1p65_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W1p65_L0p18_M2_b_L_0_18_W_1_65_tmp |
| s8rf_nshort_W1p65_L0p18_M2_b_valid = COPY s8rf_nshort_W1p65_L0p18_M2_b_L_0_18_W_1_65 |
| "k_306_s8rf_nshort_W1p65_L0p18_M2_b_valid" { |
| @ keep: s8rf_nshort_W1p65_L0p18_M2_b_valid - s8rf_nshort_W1p65_L0p18_M2_b_valid |
| COPY s8rf_nshort_W1p65_L0p18_M2_b_valid |
| } |
| s8rf_nshort_W1p65_L0p18_M2_b_invalid = s8rf_nshort_W1p65_L0p18_M2_b NOT (exemptDecaps OR s8rf_nshort_W1p65_L0p18_M2_b_valid) |
| "r_631_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W1p65_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W1p65_L0p18_M2_b_invalid |
| } |
| s8rf_nlowvt_W5p0_L0p15_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W5p0_L0p15_M4_b") |
| "k_307_s8rf_nlowvt_W5p0_L0p15_M4_b" { |
| @ keep: s8rf_nlowvt_W5p0_L0p15_M4_b - s8rf_nlowvt_W5p0_L0p15_M4_b |
| COPY s8rf_nlowvt_W5p0_L0p15_M4_b |
| } |
| s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15 = LENGTH (s8rf_nlowvt_W5p0_L0p15_M4_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_308_s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15" { |
| @ keep: s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15 - s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15 |
| COPY s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15 |
| } |
| s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15_W_5_05_tmp = INTERNAL s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15_W_5_05 = (WITH TEXT s8rf_nlowvt_W5p0_L0p15_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15_W_5_05_tmp |
| s8rf_nlowvt_W5p0_L0p15_M4_b_valid = COPY s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15_W_5_05 |
| "k_309_s8rf_nlowvt_W5p0_L0p15_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W5p0_L0p15_M4_b_valid - s8rf_nlowvt_W5p0_L0p15_M4_b_valid |
| COPY s8rf_nlowvt_W5p0_L0p15_M4_b_valid |
| } |
| s8rf_nlowvt_W5p0_L0p15_M4_b_invalid = s8rf_nlowvt_W5p0_L0p15_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W5p0_L0p15_M4_b_valid) |
| "r_632_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W5p0_L0p15_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W5p0_L0p15_M4_b_invalid |
| } |
| s8rf_nlowvt_W1p65_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W1p65_L0p18_M4_b") |
| "k_310_s8rf_nlowvt_W1p65_L0p18_M4_b" { |
| @ keep: s8rf_nlowvt_W1p65_L0p18_M4_b - s8rf_nlowvt_W1p65_L0p18_M4_b |
| COPY s8rf_nlowvt_W1p65_L0p18_M4_b |
| } |
| s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18 = LENGTH (s8rf_nlowvt_W1p65_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_311_s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18 - s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18 |
| COPY s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18 |
| } |
| s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18_W_1_65_tmp = INTERNAL s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18_W_1_65 = (WITH TEXT s8rf_nlowvt_W1p65_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18_W_1_65_tmp |
| s8rf_nlowvt_W1p65_L0p18_M4_b_valid = COPY s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18_W_1_65 |
| "k_312_s8rf_nlowvt_W1p65_L0p18_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W1p65_L0p18_M4_b_valid - s8rf_nlowvt_W1p65_L0p18_M4_b_valid |
| COPY s8rf_nlowvt_W1p65_L0p18_M4_b_valid |
| } |
| s8rf_nlowvt_W1p65_L0p18_M4_b_invalid = s8rf_nlowvt_W1p65_L0p18_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W1p65_L0p18_M4_b_valid) |
| "r_633_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W1p65_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W1p65_L0p18_M4_b_invalid |
| } |
| s8rf_nlowvt_W5p0_L0p18_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W5p0_L0p18_M4_b") |
| "k_313_s8rf_nlowvt_W5p0_L0p18_M4_b" { |
| @ keep: s8rf_nlowvt_W5p0_L0p18_M4_b - s8rf_nlowvt_W5p0_L0p18_M4_b |
| COPY s8rf_nlowvt_W5p0_L0p18_M4_b |
| } |
| s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18 = LENGTH (s8rf_nlowvt_W5p0_L0p18_M4_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_314_s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18" { |
| @ keep: s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18 - s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18 |
| COPY s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18 |
| } |
| s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18_W_5_05_tmp = INTERNAL s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18_W_5_05 = (WITH TEXT s8rf_nlowvt_W5p0_L0p18_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18_W_5_05_tmp |
| s8rf_nlowvt_W5p0_L0p18_M4_b_valid = COPY s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18_W_5_05 |
| "k_315_s8rf_nlowvt_W5p0_L0p18_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W5p0_L0p18_M4_b_valid - s8rf_nlowvt_W5p0_L0p18_M4_b_valid |
| COPY s8rf_nlowvt_W5p0_L0p18_M4_b_valid |
| } |
| s8rf_nlowvt_W5p0_L0p18_M4_b_invalid = s8rf_nlowvt_W5p0_L0p18_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W5p0_L0p18_M4_b_valid) |
| "r_634_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W5p0_L0p18_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W5p0_L0p18_M4_b_invalid |
| } |
| s8rf_nlowvt_W3p0_L0p15_2F = rfGate AND (EXTENT CELL "s8rf_nlowvt_W3p0_L0p15_2F") |
| "k_316_s8rf_nlowvt_W3p0_L0p15_2F" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_2F - s8rf_nlowvt_W3p0_L0p15_2F |
| COPY s8rf_nlowvt_W3p0_L0p15_2F |
| } |
| s8rf_nlowvt_W3p0_L0p15_2F_L_0_15 = LENGTH (s8rf_nlowvt_W3p0_L0p15_2F COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_317_s8rf_nlowvt_W3p0_L0p15_2F_L_0_15" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_2F_L_0_15 - s8rf_nlowvt_W3p0_L0p15_2F_L_0_15 |
| COPY s8rf_nlowvt_W3p0_L0p15_2F_L_0_15 |
| } |
| s8rf_nlowvt_W3p0_L0p15_2F_L_0_15_W_3_00_tmp = INTERNAL s8rf_nlowvt_W3p0_L0p15_2F_L_0_15 == 3.0 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W3p0_L0p15_2F_L_0_15_W_3_00 = (WITH TEXT s8rf_nlowvt_W3p0_L0p15_2F "dummy_poly" textlabel) OR s8rf_nlowvt_W3p0_L0p15_2F_L_0_15_W_3_00_tmp |
| s8rf_nlowvt_W3p0_L0p15_2F_valid = COPY s8rf_nlowvt_W3p0_L0p15_2F_L_0_15_W_3_00 |
| "k_318_s8rf_nlowvt_W3p0_L0p15_2F_valid" { |
| @ keep: s8rf_nlowvt_W3p0_L0p15_2F_valid - s8rf_nlowvt_W3p0_L0p15_2F_valid |
| COPY s8rf_nlowvt_W3p0_L0p15_2F_valid |
| } |
| s8rf_nlowvt_W3p0_L0p15_2F_invalid = s8rf_nlowvt_W3p0_L0p15_2F NOT (exemptDecaps OR s8rf_nlowvt_W3p0_L0p15_2F_valid) |
| "r_635_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W3p0_L0p15_2F device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W3p0_L0p15_2F_invalid |
| } |
| s8rf_nshort_W3p0_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W3p0_L0p18_M2_b") |
| "k_319_s8rf_nshort_W3p0_L0p18_M2_b" { |
| @ keep: s8rf_nshort_W3p0_L0p18_M2_b - s8rf_nshort_W3p0_L0p18_M2_b |
| COPY s8rf_nshort_W3p0_L0p18_M2_b |
| } |
| s8rf_nshort_W3p0_L0p18_M2_b_L_0_18 = LENGTH (s8rf_nshort_W3p0_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_320_s8rf_nshort_W3p0_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_nshort_W3p0_L0p18_M2_b_L_0_18 - s8rf_nshort_W3p0_L0p18_M2_b_L_0_18 |
| COPY s8rf_nshort_W3p0_L0p18_M2_b_L_0_18 |
| } |
| s8rf_nshort_W3p0_L0p18_M2_b_L_0_18_W_3_01_tmp = INTERNAL s8rf_nshort_W3p0_L0p18_M2_b_L_0_18 == 3.01 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W3p0_L0p18_M2_b_L_0_18_W_3_01 = (WITH TEXT s8rf_nshort_W3p0_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W3p0_L0p18_M2_b_L_0_18_W_3_01_tmp |
| s8rf_nshort_W3p0_L0p18_M2_b_valid = COPY s8rf_nshort_W3p0_L0p18_M2_b_L_0_18_W_3_01 |
| "k_321_s8rf_nshort_W3p0_L0p18_M2_b_valid" { |
| @ keep: s8rf_nshort_W3p0_L0p18_M2_b_valid - s8rf_nshort_W3p0_L0p18_M2_b_valid |
| COPY s8rf_nshort_W3p0_L0p18_M2_b_valid |
| } |
| s8rf_nshort_W3p0_L0p18_M2_b_invalid = s8rf_nshort_W3p0_L0p18_M2_b NOT (exemptDecaps OR s8rf_nshort_W3p0_L0p18_M2_b_valid) |
| "r_636_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W3p0_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W3p0_L0p18_M2_b_invalid |
| } |
| s8rf_nlowvt_W5p0_L0p18_M2_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W5p0_L0p18_M2_b") |
| "k_322_s8rf_nlowvt_W5p0_L0p18_M2_b" { |
| @ keep: s8rf_nlowvt_W5p0_L0p18_M2_b - s8rf_nlowvt_W5p0_L0p18_M2_b |
| COPY s8rf_nlowvt_W5p0_L0p18_M2_b |
| } |
| s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18 = LENGTH (s8rf_nlowvt_W5p0_L0p18_M2_b COINCIDENT INSIDE EDGE diff) == 0.18 |
| "k_323_s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18" { |
| @ keep: s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18 - s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18 |
| COPY s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18 |
| } |
| s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18_W_5_05_tmp = INTERNAL s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18 == 5.05 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18_W_5_05 = (WITH TEXT s8rf_nlowvt_W5p0_L0p18_M2_b "dummy_poly" textlabel) OR s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18_W_5_05_tmp |
| s8rf_nlowvt_W5p0_L0p18_M2_b_valid = COPY s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18_W_5_05 |
| "k_324_s8rf_nlowvt_W5p0_L0p18_M2_b_valid" { |
| @ keep: s8rf_nlowvt_W5p0_L0p18_M2_b_valid - s8rf_nlowvt_W5p0_L0p18_M2_b_valid |
| COPY s8rf_nlowvt_W5p0_L0p18_M2_b_valid |
| } |
| s8rf_nlowvt_W5p0_L0p18_M2_b_invalid = s8rf_nlowvt_W5p0_L0p18_M2_b NOT (exemptDecaps OR s8rf_nlowvt_W5p0_L0p18_M2_b_valid) |
| "r_637_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W5p0_L0p18_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W5p0_L0p18_M2_b_invalid |
| } |
| s8rf_nhv_W7p0_L0p5_M4_b = rfGate AND (EXTENT CELL "s8rf_nhv_W7p0_L0p5_M4_b") |
| "k_325_s8rf_nhv_W7p0_L0p5_M4_b" { |
| @ keep: s8rf_nhv_W7p0_L0p5_M4_b - s8rf_nhv_W7p0_L0p5_M4_b |
| COPY s8rf_nhv_W7p0_L0p5_M4_b |
| } |
| s8rf_nhv_W7p0_L0p5_M4_b_L_0_50 = LENGTH (s8rf_nhv_W7p0_L0p5_M4_b COINCIDENT INSIDE EDGE diff) == 0.5 |
| "k_326_s8rf_nhv_W7p0_L0p5_M4_b_L_0_50" { |
| @ keep: s8rf_nhv_W7p0_L0p5_M4_b_L_0_50 - s8rf_nhv_W7p0_L0p5_M4_b_L_0_50 |
| COPY s8rf_nhv_W7p0_L0p5_M4_b_L_0_50 |
| } |
| s8rf_nhv_W7p0_L0p5_M4_b_L_0_50_W_7_09_tmp = INTERNAL s8rf_nhv_W7p0_L0p5_M4_b_L_0_50 == 7.09 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nhv_W7p0_L0p5_M4_b_L_0_50_W_7_09 = (WITH TEXT s8rf_nhv_W7p0_L0p5_M4_b "dummy_poly" textlabel) OR s8rf_nhv_W7p0_L0p5_M4_b_L_0_50_W_7_09_tmp |
| s8rf_nhv_W7p0_L0p5_M4_b_valid = COPY s8rf_nhv_W7p0_L0p5_M4_b_L_0_50_W_7_09 |
| "k_327_s8rf_nhv_W7p0_L0p5_M4_b_valid" { |
| @ keep: s8rf_nhv_W7p0_L0p5_M4_b_valid - s8rf_nhv_W7p0_L0p5_M4_b_valid |
| COPY s8rf_nhv_W7p0_L0p5_M4_b_valid |
| } |
| s8rf_nhv_W7p0_L0p5_M4_b_invalid = s8rf_nhv_W7p0_L0p5_M4_b NOT (exemptDecaps OR s8rf_nhv_W7p0_L0p5_M4_b_valid) |
| "r_638_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nhv_W7p0_L0p5_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nhv_W7p0_L0p5_M4_b_invalid |
| } |
| nhvesd_L_0_55 = LENGTH ("nhvesd" COINCIDENT INSIDE EDGE diff) == 0.55 |
| "k_328_nhvesd_L_0_55" { |
| @ keep: nhvesd_L_0_55 - nhvesd_L_0_55 |
| COPY nhvesd_L_0_55 |
| } |
| nhvesd_L_0_55_W_17_50_tmp = INTERNAL nhvesd_L_0_55 == 17.5 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_17_50 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_17_50_tmp |
| nhvesd_L_0_55_W_19_50_tmp = INTERNAL nhvesd_L_0_55 == 19.5 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_19_50 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_19_50_tmp |
| nhvesd_L_0_55_W_21_50_tmp = INTERNAL nhvesd_L_0_55 == 21.5 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_21_50 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_21_50_tmp |
| nhvesd_L_0_55_W_23_50_tmp = INTERNAL nhvesd_L_0_55 == 23.5 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_23_50 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_23_50_tmp |
| nhvesd_L_0_55_W_26_50_tmp = INTERNAL nhvesd_L_0_55 == 26.5 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_26_50 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_26_50_tmp |
| nhvesd_L_0_55_W_30_25_tmp = INTERNAL nhvesd_L_0_55 == 30.25 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_30_25 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_30_25_tmp |
| nhvesd_L_0_55_W_40_31_tmp = INTERNAL nhvesd_L_0_55 == 40.31 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_40_31 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_40_31_tmp |
| nhvesd_L_0_55_W_50_99_tmp = INTERNAL nhvesd_L_0_55 == 50.99 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_55_W_50_99 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_55_W_50_99_tmp |
| nhvesd_L_0_60 = LENGTH ("nhvesd" COINCIDENT INSIDE EDGE diff) == 0.6 |
| "k_329_nhvesd_L_0_60" { |
| @ keep: nhvesd_L_0_60 - nhvesd_L_0_60 |
| COPY nhvesd_L_0_60 |
| } |
| nhvesd_L_0_60_W_5_40_tmp = INTERNAL nhvesd_L_0_60 == 5.4 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_0_60_W_5_40 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_0_60_W_5_40_tmp |
| nhvesd_L_1_00 = LENGTH ("nhvesd" COINCIDENT INSIDE EDGE diff) == 1.0 |
| "k_330_nhvesd_L_1_00" { |
| @ keep: nhvesd_L_1_00 - nhvesd_L_1_00 |
| COPY nhvesd_L_1_00 |
| } |
| nhvesd_L_1_00_W_30_25_tmp = INTERNAL nhvesd_L_1_00 == 30.25 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_1_00_W_30_25 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_1_00_W_30_25_tmp |
| nhvesd_L_1_00_W_50_99_tmp = INTERNAL nhvesd_L_1_00 == 50.99 OPPOSITE PARALLEL ONLY REGION |
| nhvesd_L_1_00_W_50_99 = (WITH TEXT "nhvesd" "dummy_poly" textlabel) OR nhvesd_L_1_00_W_50_99_tmp |
| nhvesd_valid = nhvesd_L_1_00_W_50_99 OR |
| (nhvesd_L_1_00_W_30_25 OR |
| (nhvesd_L_0_60_W_5_40 OR |
| (nhvesd_L_0_55_W_50_99 OR |
| (nhvesd_L_0_55_W_40_31 OR |
| (nhvesd_L_0_55_W_30_25 OR |
| (nhvesd_L_0_55_W_26_50 OR |
| (nhvesd_L_0_55_W_23_50 OR |
| (nhvesd_L_0_55_W_21_50 OR |
| (nhvesd_L_0_55_W_19_50 OR nhvesd_L_0_55_W_17_50))))))))) |
| "k_331_nhvesd_valid" { |
| @ keep: nhvesd_valid - nhvesd_valid |
| COPY nhvesd_valid |
| } |
| nhvesd_invalid = nhvesd NOT (exemptDecaps OR nhvesd_valid) |
| "r_639_Poly.X.1" { |
| @ Poly.X.1: This nhvesd device has an invalid W/L. Please see MRGA |
| COPY nhvesd_invalid |
| } |
| s8rf_nshort_W1p65_L0p25_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W1p65_L0p25_M2_b") |
| "k_332_s8rf_nshort_W1p65_L0p25_M2_b" { |
| @ keep: s8rf_nshort_W1p65_L0p25_M2_b - s8rf_nshort_W1p65_L0p25_M2_b |
| COPY s8rf_nshort_W1p65_L0p25_M2_b |
| } |
| s8rf_nshort_W1p65_L0p25_M2_b_L_0_25 = LENGTH (s8rf_nshort_W1p65_L0p25_M2_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_333_s8rf_nshort_W1p65_L0p25_M2_b_L_0_25" { |
| @ keep: s8rf_nshort_W1p65_L0p25_M2_b_L_0_25 - s8rf_nshort_W1p65_L0p25_M2_b_L_0_25 |
| COPY s8rf_nshort_W1p65_L0p25_M2_b_L_0_25 |
| } |
| s8rf_nshort_W1p65_L0p25_M2_b_L_0_25_W_1_65_tmp = INTERNAL s8rf_nshort_W1p65_L0p25_M2_b_L_0_25 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W1p65_L0p25_M2_b_L_0_25_W_1_65 = (WITH TEXT s8rf_nshort_W1p65_L0p25_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W1p65_L0p25_M2_b_L_0_25_W_1_65_tmp |
| s8rf_nshort_W1p65_L0p25_M2_b_valid = COPY s8rf_nshort_W1p65_L0p25_M2_b_L_0_25_W_1_65 |
| "k_334_s8rf_nshort_W1p65_L0p25_M2_b_valid" { |
| @ keep: s8rf_nshort_W1p65_L0p25_M2_b_valid - s8rf_nshort_W1p65_L0p25_M2_b_valid |
| COPY s8rf_nshort_W1p65_L0p25_M2_b_valid |
| } |
| s8rf_nshort_W1p65_L0p25_M2_b_invalid = s8rf_nshort_W1p65_L0p25_M2_b NOT (exemptDecaps OR s8rf_nshort_W1p65_L0p25_M2_b_valid) |
| "r_640_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W1p65_L0p25_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W1p65_L0p25_M2_b_invalid |
| } |
| s8rf_nlowvt_W1p65_L0p25_M4_b = rfGate AND (EXTENT CELL "s8rf_nlowvt_W1p65_L0p25_M4_b") |
| "k_335_s8rf_nlowvt_W1p65_L0p25_M4_b" { |
| @ keep: s8rf_nlowvt_W1p65_L0p25_M4_b - s8rf_nlowvt_W1p65_L0p25_M4_b |
| COPY s8rf_nlowvt_W1p65_L0p25_M4_b |
| } |
| s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25 = LENGTH (s8rf_nlowvt_W1p65_L0p25_M4_b COINCIDENT INSIDE EDGE diff) == 0.25 |
| "k_336_s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25" { |
| @ keep: s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25 - s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25 |
| COPY s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25 |
| } |
| s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25_W_1_65_tmp = INTERNAL s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25_W_1_65 = (WITH TEXT s8rf_nlowvt_W1p65_L0p25_M4_b "dummy_poly" textlabel) OR s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25_W_1_65_tmp |
| s8rf_nlowvt_W1p65_L0p25_M4_b_valid = COPY s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25_W_1_65 |
| "k_337_s8rf_nlowvt_W1p65_L0p25_M4_b_valid" { |
| @ keep: s8rf_nlowvt_W1p65_L0p25_M4_b_valid - s8rf_nlowvt_W1p65_L0p25_M4_b_valid |
| COPY s8rf_nlowvt_W1p65_L0p25_M4_b_valid |
| } |
| s8rf_nlowvt_W1p65_L0p25_M4_b_invalid = s8rf_nlowvt_W1p65_L0p25_M4_b NOT (exemptDecaps OR s8rf_nlowvt_W1p65_L0p25_M4_b_valid) |
| "r_641_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nlowvt_W1p65_L0p25_M4_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nlowvt_W1p65_L0p25_M4_b_invalid |
| } |
| s8rf_nshort_W1p65_L0p15_M2_b = rfGate AND (EXTENT CELL "s8rf_nshort_W1p65_L0p15_M2_b") |
| "k_338_s8rf_nshort_W1p65_L0p15_M2_b" { |
| @ keep: s8rf_nshort_W1p65_L0p15_M2_b - s8rf_nshort_W1p65_L0p15_M2_b |
| COPY s8rf_nshort_W1p65_L0p15_M2_b |
| } |
| s8rf_nshort_W1p65_L0p15_M2_b_L_0_15 = LENGTH (s8rf_nshort_W1p65_L0p15_M2_b COINCIDENT INSIDE EDGE diff) == 0.15 |
| "k_339_s8rf_nshort_W1p65_L0p15_M2_b_L_0_15" { |
| @ keep: s8rf_nshort_W1p65_L0p15_M2_b_L_0_15 - s8rf_nshort_W1p65_L0p15_M2_b_L_0_15 |
| COPY s8rf_nshort_W1p65_L0p15_M2_b_L_0_15 |
| } |
| s8rf_nshort_W1p65_L0p15_M2_b_L_0_15_W_1_65_tmp = INTERNAL s8rf_nshort_W1p65_L0p15_M2_b_L_0_15 == 1.65 OPPOSITE PARALLEL ONLY REGION |
| s8rf_nshort_W1p65_L0p15_M2_b_L_0_15_W_1_65 = (WITH TEXT s8rf_nshort_W1p65_L0p15_M2_b "dummy_poly" textlabel) OR s8rf_nshort_W1p65_L0p15_M2_b_L_0_15_W_1_65_tmp |
| s8rf_nshort_W1p65_L0p15_M2_b_valid = COPY s8rf_nshort_W1p65_L0p15_M2_b_L_0_15_W_1_65 |
| "k_340_s8rf_nshort_W1p65_L0p15_M2_b_valid" { |
| @ keep: s8rf_nshort_W1p65_L0p15_M2_b_valid - s8rf_nshort_W1p65_L0p15_M2_b_valid |
| COPY s8rf_nshort_W1p65_L0p15_M2_b_valid |
| } |
| s8rf_nshort_W1p65_L0p15_M2_b_invalid = s8rf_nshort_W1p65_L0p15_M2_b NOT (exemptDecaps OR s8rf_nshort_W1p65_L0p15_M2_b_valid) |
| "r_642_Poly.X.1" { |
| @ Poly.X.1: This s8rf_nshort_W1p65_L0p15_M2_b device has an invalid W/L. Please see MRGA |
| COPY s8rf_nshort_W1p65_L0p15_M2_b_invalid |
| } |
| pvhv_L_0_66 = LENGTH ("pvhv" COINCIDENT INSIDE EDGE diff) == 0.66 |
| "k_341_pvhv_L_0_66" { |
| @ keep: pvhv_L_0_66 - pvhv_L_0_66 |
| COPY pvhv_L_0_66 |
| } |
| pvhv_L_0_66_W_5_00_tmp = INTERNAL pvhv_L_0_66 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pvhv_L_0_66_W_5_00 = (WITH TEXT "pvhv" "dummy_poly" textlabel) OR pvhv_L_0_66_W_5_00_tmp |
| pvhv_L_0_66_W_20_00_tmp = INTERNAL pvhv_L_0_66 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| pvhv_L_0_66_W_20_00 = (WITH TEXT "pvhv" "dummy_poly" textlabel) OR pvhv_L_0_66_W_20_00_tmp |
| pvhv_L_0_66_W_50_00_tmp = INTERNAL pvhv_L_0_66 == 50.0 OPPOSITE PARALLEL ONLY REGION |
| pvhv_L_0_66_W_50_00 = (WITH TEXT "pvhv" "dummy_poly" textlabel) OR pvhv_L_0_66_W_50_00_tmp |
| pvhv_L_2_16 = LENGTH ("pvhv" COINCIDENT INSIDE EDGE diff) == 2.16 |
| "k_342_pvhv_L_2_16" { |
| @ keep: pvhv_L_2_16 - pvhv_L_2_16 |
| COPY pvhv_L_2_16 |
| } |
| pvhv_L_2_16_W_5_00_tmp = INTERNAL pvhv_L_2_16 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| pvhv_L_2_16_W_5_00 = (WITH TEXT "pvhv" "dummy_poly" textlabel) OR pvhv_L_2_16_W_5_00_tmp |
| pvhv_L_2_16_W_20_00_tmp = INTERNAL pvhv_L_2_16 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| pvhv_L_2_16_W_20_00 = (WITH TEXT "pvhv" "dummy_poly" textlabel) OR pvhv_L_2_16_W_20_00_tmp |
| pvhv_valid = pvhv_L_2_16_W_20_00 OR |
| (pvhv_L_2_16_W_5_00 OR |
| (pvhv_L_0_66_W_50_00 OR |
| (pvhv_L_0_66_W_20_00 OR pvhv_L_0_66_W_5_00))) |
| "k_343_pvhv_valid" { |
| @ keep: pvhv_valid - pvhv_valid |
| COPY pvhv_valid |
| } |
| pvhv_invalid = pvhv NOT (exemptDecaps OR pvhv_valid) |
| "r_643_Poly.X.1" { |
| @ Poly.X.1: This pvhv device has an invalid W/L. Please see MRGA |
| COPY pvhv_invalid |
| } |
| nvhv_L_0_70 = LENGTH ("nvhv" COINCIDENT INSIDE EDGE diff) == 0.7 |
| "k_344_nvhv_L_0_70" { |
| @ keep: nvhv_L_0_70 - nvhv_L_0_70 |
| COPY nvhv_L_0_70 |
| } |
| nvhv_L_0_70_W_5_00_tmp = INTERNAL nvhv_L_0_70 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nvhv_L_0_70_W_5_00 = (WITH TEXT "nvhv" "dummy_poly" textlabel) OR nvhv_L_0_70_W_5_00_tmp |
| nvhv_L_0_70_W_20_00_tmp = INTERNAL nvhv_L_0_70 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| nvhv_L_0_70_W_20_00 = (WITH TEXT "nvhv" "dummy_poly" textlabel) OR nvhv_L_0_70_W_20_00_tmp |
| nvhv_L_0_70_W_50_00_tmp = INTERNAL nvhv_L_0_70 == 50.0 OPPOSITE PARALLEL ONLY REGION |
| nvhv_L_0_70_W_50_00 = (WITH TEXT "nvhv" "dummy_poly" textlabel) OR nvhv_L_0_70_W_50_00_tmp |
| nvhv_L_0_70_W_60_00_tmp = INTERNAL nvhv_L_0_70 == 60.0 OPPOSITE PARALLEL ONLY REGION |
| nvhv_L_0_70_W_60_00 = (WITH TEXT "nvhv" "dummy_poly" textlabel) OR nvhv_L_0_70_W_60_00_tmp |
| nvhv_L_2_20 = LENGTH ("nvhv" COINCIDENT INSIDE EDGE diff) == 2.2 |
| "k_345_nvhv_L_2_20" { |
| @ keep: nvhv_L_2_20 - nvhv_L_2_20 |
| COPY nvhv_L_2_20 |
| } |
| nvhv_L_2_20_W_5_00_tmp = INTERNAL nvhv_L_2_20 == 5.0 OPPOSITE PARALLEL ONLY REGION |
| nvhv_L_2_20_W_5_00 = (WITH TEXT "nvhv" "dummy_poly" textlabel) OR nvhv_L_2_20_W_5_00_tmp |
| nvhv_L_2_20_W_20_00_tmp = INTERNAL nvhv_L_2_20 == 20.0 OPPOSITE PARALLEL ONLY REGION |
| nvhv_L_2_20_W_20_00 = (WITH TEXT "nvhv" "dummy_poly" textlabel) OR nvhv_L_2_20_W_20_00_tmp |
| nvhv_valid = nvhv_L_2_20_W_20_00 OR |
| (nvhv_L_2_20_W_5_00 OR |
| (nvhv_L_0_70_W_60_00 OR |
| (nvhv_L_0_70_W_50_00 OR |
| (nvhv_L_0_70_W_20_00 OR nvhv_L_0_70_W_5_00)))) |
| "k_346_nvhv_valid" { |
| @ keep: nvhv_valid - nvhv_valid |
| COPY nvhv_valid |
| } |
| nvhv_invalid = nvhv NOT (exemptDecaps OR nvhv_valid) |
| "r_644_Poly.X.1" { |
| @ Poly.X.1: This nvhv device has an invalid W/L. Please see MRGA |
| COPY nvhv_invalid |
| } |
| s8rf_nlowvt_W0p42_L0p15_2F_cell = INTERACT diff (INSIDE CELL diff s8rf_nlowvt_W0p42_L0p15_2F) |
| s8rf_nlowvt_W0p84_L0p15_2F_cell = INTERACT diff (INSIDE CELL diff s8rf_nlowvt_W0p84_L0p15_2F) |
| s8rf_nlowvt_W0p84_L0p15_4F_cell = INTERACT diff (INSIDE CELL diff s8rf_nlowvt_W0p84_L0p15_4F) |
| s8rf_nlowvt_W0p84_L0p15_8F_cell = INTERACT diff (INSIDE CELL diff s8rf_nlowvt_W0p84_L0p15_8F) |
| s8rf_nlowvt_W3p0_L0p15_2F_cell = INTERACT diff (INSIDE CELL diff s8rf_nlowvt_W3p0_L0p15_2F) |
| s8rf_nlowvt_W3p0_L0p15_4F_cell = INTERACT diff (INSIDE CELL diff s8rf_nlowvt_W3p0_L0p15_4F) |
| s8rf_nlowvt_W3p0_L0p15_8F_cell = INTERACT diff (INSIDE CELL diff s8rf_nlowvt_W3p0_L0p15_8F) |
| s8rf_pshort_W0p84_L0p15_2F_cell = INTERACT diff (INSIDE CELL diff s8rf_pshort_W0p84_L0p15_2F) |
| s8rf_pshort_W1p68_L0p15_2F_cell = INTERACT diff (INSIDE CELL diff s8rf_pshort_W1p68_L0p15_2F) |
| s8rf_pshort_W1p68_L0p15_4F_cell = INTERACT diff (INSIDE CELL diff s8rf_pshort_W1p68_L0p15_4F) |
| s8rf_pshort_W3p0_L0p15_2F_cell = INTERACT diff (INSIDE CELL diff s8rf_pshort_W3p0_L0p15_2F) |
| s8rf_pshort_W5p0_L0p15_2F_cell = INTERACT diff (INSIDE CELL diff s8rf_pshort_W5p0_L0p15_2F) |
| q0s8rf_nlowvt_W0p42_L0p15_2F_cell = NOT RECTANGLE s8rf_nlowvt_W0p42_L0p15_2F_cell ORTHOGONAL ONLY |
| "r_645_diff.13" { |
| @ diff.13: s8rf_nlowvt_W0p42_L0p15_2F_cell should be rectangular |
| COPY q0s8rf_nlowvt_W0p42_L0p15_2F_cell |
| } |
| q1s8rf_nlowvt_W0p42_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W0p42_L0p15_2F_cell < 0.42 REGION |
| "r_646_diff.13" { |
| @ diff.13: 0.42 min. width of s8rf_nlowvt_W0p42_L0p15_2F_cell |
| COPY q1s8rf_nlowvt_W0p42_L0p15_2F_cell |
| } |
| q2s8rf_nlowvt_W0p42_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W0p42_L0p15_2F_cell <= 0.42 REGION |
| q3s8rf_nlowvt_W0p42_L0p15_2F_cell = s8rf_nlowvt_W0p42_L0p15_2F_cell NOT q2s8rf_nlowvt_W0p42_L0p15_2F_cell |
| "r_647_diff.13" { |
| @ diff.13: 0.42 max. width of s8rf_nlowvt_W0p42_L0p15_2F_cell |
| COPY q3s8rf_nlowvt_W0p42_L0p15_2F_cell |
| } |
| q4s8rf_nlowvt_W0p42_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W0p42_L0p15_2F_cell < 1.14 PROJECTING < 1.14 REGION |
| "r_648_diff.13" { |
| @ diff.13: 1.14 min. length of s8rf_nlowvt_W0p42_L0p15_2F_cell |
| COPY q4s8rf_nlowvt_W0p42_L0p15_2F_cell |
| } |
| q5s8rf_nlowvt_W0p42_L0p15_2F_cell = s8rf_nlowvt_W0p42_L0p15_2F_cell WITH EDGE (LENGTH s8rf_nlowvt_W0p42_L0p15_2F_cell > 1.14) |
| "r_649_diff.13" { |
| @ diff.13: 1.14 max. length of s8rf_nlowvt_W0p42_L0p15_2F_cell |
| COPY q5s8rf_nlowvt_W0p42_L0p15_2F_cell |
| } |
| q0s8rf_nlowvt_W0p84_L0p15_2F_cell = NOT RECTANGLE s8rf_nlowvt_W0p84_L0p15_2F_cell ORTHOGONAL ONLY |
| "r_650_diff.13" { |
| @ diff.13: s8rf_nlowvt_W0p84_L0p15_2F_cell should be rectangular |
| COPY q0s8rf_nlowvt_W0p84_L0p15_2F_cell |
| } |
| q1s8rf_nlowvt_W0p84_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_2F_cell < 0.84 REGION |
| "r_651_diff.13" { |
| @ diff.13: 0.84 min. width of s8rf_nlowvt_W0p84_L0p15_2F_cell |
| COPY q1s8rf_nlowvt_W0p84_L0p15_2F_cell |
| } |
| q2s8rf_nlowvt_W0p84_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_2F_cell <= 0.84 REGION |
| q3s8rf_nlowvt_W0p84_L0p15_2F_cell = s8rf_nlowvt_W0p84_L0p15_2F_cell NOT q2s8rf_nlowvt_W0p84_L0p15_2F_cell |
| "r_652_diff.13" { |
| @ diff.13: 0.84 max. width of s8rf_nlowvt_W0p84_L0p15_2F_cell |
| COPY q3s8rf_nlowvt_W0p84_L0p15_2F_cell |
| } |
| q4s8rf_nlowvt_W0p84_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_2F_cell < 1.14 PROJECTING < 1.14 REGION |
| "r_653_diff.13" { |
| @ diff.13: 1.14 min. length of s8rf_nlowvt_W0p84_L0p15_2F_cell |
| COPY q4s8rf_nlowvt_W0p84_L0p15_2F_cell |
| } |
| q5s8rf_nlowvt_W0p84_L0p15_2F_cell = s8rf_nlowvt_W0p84_L0p15_2F_cell WITH EDGE (LENGTH s8rf_nlowvt_W0p84_L0p15_2F_cell > 1.14) |
| "r_654_diff.13" { |
| @ diff.13: 1.14 max. length of s8rf_nlowvt_W0p84_L0p15_2F_cell |
| COPY q5s8rf_nlowvt_W0p84_L0p15_2F_cell |
| } |
| q0s8rf_nlowvt_W0p84_L0p15_4F_cell = NOT RECTANGLE s8rf_nlowvt_W0p84_L0p15_4F_cell ORTHOGONAL ONLY |
| "r_655_diff.13" { |
| @ diff.13: s8rf_nlowvt_W0p84_L0p15_4F_cell should be rectangular |
| COPY q0s8rf_nlowvt_W0p84_L0p15_4F_cell |
| } |
| q1s8rf_nlowvt_W0p84_L0p15_4F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_4F_cell < 0.84 REGION |
| "r_656_diff.13" { |
| @ diff.13: 0.84 min. width of s8rf_nlowvt_W0p84_L0p15_4F_cell |
| COPY q1s8rf_nlowvt_W0p84_L0p15_4F_cell |
| } |
| q2s8rf_nlowvt_W0p84_L0p15_4F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_4F_cell <= 0.84 REGION |
| q3s8rf_nlowvt_W0p84_L0p15_4F_cell = s8rf_nlowvt_W0p84_L0p15_4F_cell NOT q2s8rf_nlowvt_W0p84_L0p15_4F_cell |
| "r_657_diff.13" { |
| @ diff.13: 0.84 max. width of s8rf_nlowvt_W0p84_L0p15_4F_cell |
| COPY q3s8rf_nlowvt_W0p84_L0p15_4F_cell |
| } |
| q4s8rf_nlowvt_W0p84_L0p15_4F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_4F_cell < 2.0 PROJECTING < 2.0 REGION |
| "r_658_diff.13" { |
| @ diff.13: 2 min. length of s8rf_nlowvt_W0p84_L0p15_4F_cell |
| COPY q4s8rf_nlowvt_W0p84_L0p15_4F_cell |
| } |
| q5s8rf_nlowvt_W0p84_L0p15_4F_cell = s8rf_nlowvt_W0p84_L0p15_4F_cell WITH EDGE (LENGTH s8rf_nlowvt_W0p84_L0p15_4F_cell > 2.0) |
| "r_659_diff.13" { |
| @ diff.13: 2 max. length of s8rf_nlowvt_W0p84_L0p15_4F_cell |
| COPY q5s8rf_nlowvt_W0p84_L0p15_4F_cell |
| } |
| q0s8rf_nlowvt_W0p84_L0p15_8F_cell = NOT RECTANGLE s8rf_nlowvt_W0p84_L0p15_8F_cell ORTHOGONAL ONLY |
| "r_660_diff.13" { |
| @ diff.13: s8rf_nlowvt_W0p84_L0p15_8F_cell should be rectangular |
| COPY q0s8rf_nlowvt_W0p84_L0p15_8F_cell |
| } |
| q1s8rf_nlowvt_W0p84_L0p15_8F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_8F_cell < 0.84 REGION |
| "r_661_diff.13" { |
| @ diff.13: 0.84 min. width of s8rf_nlowvt_W0p84_L0p15_8F_cell |
| COPY q1s8rf_nlowvt_W0p84_L0p15_8F_cell |
| } |
| q2s8rf_nlowvt_W0p84_L0p15_8F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_8F_cell <= 0.84 REGION |
| q3s8rf_nlowvt_W0p84_L0p15_8F_cell = s8rf_nlowvt_W0p84_L0p15_8F_cell NOT q2s8rf_nlowvt_W0p84_L0p15_8F_cell |
| "r_662_diff.13" { |
| @ diff.13: 0.84 max. width of s8rf_nlowvt_W0p84_L0p15_8F_cell |
| COPY q3s8rf_nlowvt_W0p84_L0p15_8F_cell |
| } |
| q4s8rf_nlowvt_W0p84_L0p15_8F_cell = INTERNAL s8rf_nlowvt_W0p84_L0p15_8F_cell < 3.72 PROJECTING < 3.72 REGION |
| "r_663_diff.13" { |
| @ diff.13: 3.72 min. length of s8rf_nlowvt_W0p84_L0p15_8F_cell |
| COPY q4s8rf_nlowvt_W0p84_L0p15_8F_cell |
| } |
| q5s8rf_nlowvt_W0p84_L0p15_8F_cell = s8rf_nlowvt_W0p84_L0p15_8F_cell WITH EDGE (LENGTH s8rf_nlowvt_W0p84_L0p15_8F_cell > 3.72) |
| "r_664_diff.13" { |
| @ diff.13: 3.72 max. length of s8rf_nlowvt_W0p84_L0p15_8F_cell |
| COPY q5s8rf_nlowvt_W0p84_L0p15_8F_cell |
| } |
| q0s8rf_nlowvt_W3p0_L0p15_2F_cell = NOT RECTANGLE s8rf_nlowvt_W3p0_L0p15_2F_cell ORTHOGONAL ONLY |
| "r_665_diff.13" { |
| @ diff.13: s8rf_nlowvt_W3p0_L0p15_2F_cell should be rectangular |
| COPY q0s8rf_nlowvt_W3p0_L0p15_2F_cell |
| } |
| q1s8rf_nlowvt_W3p0_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_2F_cell < 1.14 REGION |
| "r_666_diff.13" { |
| @ diff.13: 1.14 min. width of s8rf_nlowvt_W3p0_L0p15_2F_cell |
| COPY q1s8rf_nlowvt_W3p0_L0p15_2F_cell |
| } |
| q2s8rf_nlowvt_W3p0_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_2F_cell <= 1.14 REGION |
| q3s8rf_nlowvt_W3p0_L0p15_2F_cell = s8rf_nlowvt_W3p0_L0p15_2F_cell NOT q2s8rf_nlowvt_W3p0_L0p15_2F_cell |
| "r_667_diff.13" { |
| @ diff.13: 1.14 max. width of s8rf_nlowvt_W3p0_L0p15_2F_cell |
| COPY q3s8rf_nlowvt_W3p0_L0p15_2F_cell |
| } |
| q4s8rf_nlowvt_W3p0_L0p15_2F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_2F_cell < 3.0 PROJECTING < 3.0 REGION |
| "r_668_diff.13" { |
| @ diff.13: 3 min. length of s8rf_nlowvt_W3p0_L0p15_2F_cell |
| COPY q4s8rf_nlowvt_W3p0_L0p15_2F_cell |
| } |
| q5s8rf_nlowvt_W3p0_L0p15_2F_cell = s8rf_nlowvt_W3p0_L0p15_2F_cell WITH EDGE (LENGTH s8rf_nlowvt_W3p0_L0p15_2F_cell > 3.0) |
| "r_669_diff.13" { |
| @ diff.13: 3 max. length of s8rf_nlowvt_W3p0_L0p15_2F_cell |
| COPY q5s8rf_nlowvt_W3p0_L0p15_2F_cell |
| } |
| q0s8rf_nlowvt_W3p0_L0p15_4F_cell = NOT RECTANGLE s8rf_nlowvt_W3p0_L0p15_4F_cell ORTHOGONAL ONLY |
| "r_670_diff.13" { |
| @ diff.13: s8rf_nlowvt_W3p0_L0p15_4F_cell should be rectangular |
| COPY q0s8rf_nlowvt_W3p0_L0p15_4F_cell |
| } |
| q1s8rf_nlowvt_W3p0_L0p15_4F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_4F_cell < 2.0 REGION |
| "r_671_diff.13" { |
| @ diff.13: 2 min. width of s8rf_nlowvt_W3p0_L0p15_4F_cell |
| COPY q1s8rf_nlowvt_W3p0_L0p15_4F_cell |
| } |
| q2s8rf_nlowvt_W3p0_L0p15_4F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_4F_cell <= 2.0 REGION |
| q3s8rf_nlowvt_W3p0_L0p15_4F_cell = s8rf_nlowvt_W3p0_L0p15_4F_cell NOT q2s8rf_nlowvt_W3p0_L0p15_4F_cell |
| "r_672_diff.13" { |
| @ diff.13: 2 max. width of s8rf_nlowvt_W3p0_L0p15_4F_cell |
| COPY q3s8rf_nlowvt_W3p0_L0p15_4F_cell |
| } |
| q4s8rf_nlowvt_W3p0_L0p15_4F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_4F_cell < 3.0 PROJECTING < 3.0 REGION |
| "r_673_diff.13" { |
| @ diff.13: 3 min. length of s8rf_nlowvt_W3p0_L0p15_4F_cell |
| COPY q4s8rf_nlowvt_W3p0_L0p15_4F_cell |
| } |
| q5s8rf_nlowvt_W3p0_L0p15_4F_cell = s8rf_nlowvt_W3p0_L0p15_4F_cell WITH EDGE (LENGTH s8rf_nlowvt_W3p0_L0p15_4F_cell > 3.0) |
| "r_674_diff.13" { |
| @ diff.13: 3 max. length of s8rf_nlowvt_W3p0_L0p15_4F_cell |
| COPY q5s8rf_nlowvt_W3p0_L0p15_4F_cell |
| } |
| q0s8rf_nlowvt_W3p0_L0p15_8F_cell = NOT RECTANGLE s8rf_nlowvt_W3p0_L0p15_8F_cell ORTHOGONAL ONLY |
| "r_675_diff.13" { |
| @ diff.13: s8rf_nlowvt_W3p0_L0p15_8F_cell should be rectangular |
| COPY q0s8rf_nlowvt_W3p0_L0p15_8F_cell |
| } |
| q1s8rf_nlowvt_W3p0_L0p15_8F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_8F_cell < 3.0 REGION |
| "r_676_diff.13" { |
| @ diff.13: 3 min. width of s8rf_nlowvt_W3p0_L0p15_8F_cell |
| COPY q1s8rf_nlowvt_W3p0_L0p15_8F_cell |
| } |
| q2s8rf_nlowvt_W3p0_L0p15_8F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_8F_cell <= 3.0 REGION |
| q3s8rf_nlowvt_W3p0_L0p15_8F_cell = s8rf_nlowvt_W3p0_L0p15_8F_cell NOT q2s8rf_nlowvt_W3p0_L0p15_8F_cell |
| "r_677_diff.13" { |
| @ diff.13: 3 max. width of s8rf_nlowvt_W3p0_L0p15_8F_cell |
| COPY q3s8rf_nlowvt_W3p0_L0p15_8F_cell |
| } |
| q4s8rf_nlowvt_W3p0_L0p15_8F_cell = INTERNAL s8rf_nlowvt_W3p0_L0p15_8F_cell < 3.72 PROJECTING < 3.72 REGION |
| "r_678_diff.13" { |
| @ diff.13: 3.72 min. length of s8rf_nlowvt_W3p0_L0p15_8F_cell |
| COPY q4s8rf_nlowvt_W3p0_L0p15_8F_cell |
| } |
| q5s8rf_nlowvt_W3p0_L0p15_8F_cell = s8rf_nlowvt_W3p0_L0p15_8F_cell WITH EDGE (LENGTH s8rf_nlowvt_W3p0_L0p15_8F_cell > 3.72) |
| "r_679_diff.13" { |
| @ diff.13: 3.72 max. length of s8rf_nlowvt_W3p0_L0p15_8F_cell |
| COPY q5s8rf_nlowvt_W3p0_L0p15_8F_cell |
| } |
| q0s8rf_pshort_W0p84_L0p15_2F_cell = NOT RECTANGLE s8rf_pshort_W0p84_L0p15_2F_cell ORTHOGONAL ONLY |
| "r_680_diff.13" { |
| @ diff.13: s8rf_pshort_W0p84_L0p15_2F_cell should be rectangular |
| COPY q0s8rf_pshort_W0p84_L0p15_2F_cell |
| } |
| q1s8rf_pshort_W0p84_L0p15_2F_cell = INTERNAL s8rf_pshort_W0p84_L0p15_2F_cell < 0.84 REGION |
| "r_681_diff.13" { |
| @ diff.13: 0.84 min. width of s8rf_pshort_W0p84_L0p15_2F_cell |
| COPY q1s8rf_pshort_W0p84_L0p15_2F_cell |
| } |
| q2s8rf_pshort_W0p84_L0p15_2F_cell = INTERNAL s8rf_pshort_W0p84_L0p15_2F_cell <= 0.84 REGION |
| q3s8rf_pshort_W0p84_L0p15_2F_cell = s8rf_pshort_W0p84_L0p15_2F_cell NOT q2s8rf_pshort_W0p84_L0p15_2F_cell |
| "r_682_diff.13" { |
| @ diff.13: 0.84 max. width of s8rf_pshort_W0p84_L0p15_2F_cell |
| COPY q3s8rf_pshort_W0p84_L0p15_2F_cell |
| } |
| q4s8rf_pshort_W0p84_L0p15_2F_cell = INTERNAL s8rf_pshort_W0p84_L0p15_2F_cell < 1.11 PROJECTING < 1.11 REGION |
| "r_683_diff.13" { |
| @ diff.13: 1.11 min. length of s8rf_pshort_W0p84_L0p15_2F_cell |
| COPY q4s8rf_pshort_W0p84_L0p15_2F_cell |
| } |
| q5s8rf_pshort_W0p84_L0p15_2F_cell = s8rf_pshort_W0p84_L0p15_2F_cell WITH EDGE (LENGTH s8rf_pshort_W0p84_L0p15_2F_cell > 1.11) |
| "r_684_diff.13" { |
| @ diff.13: 1.11 max. length of s8rf_pshort_W0p84_L0p15_2F_cell |
| COPY q5s8rf_pshort_W0p84_L0p15_2F_cell |
| } |
| q0s8rf_pshort_W1p68_L0p15_2F_cell = NOT RECTANGLE s8rf_pshort_W1p68_L0p15_2F_cell ORTHOGONAL ONLY |
| "r_685_diff.13" { |
| @ diff.13: s8rf_pshort_W1p68_L0p15_2F_cell should be rectangular |
| COPY q0s8rf_pshort_W1p68_L0p15_2F_cell |
| } |
| q1s8rf_pshort_W1p68_L0p15_2F_cell = INTERNAL s8rf_pshort_W1p68_L0p15_2F_cell < 1.11 REGION |
| "r_686_diff.13" { |
| @ diff.13: 1.11 min. width of s8rf_pshort_W1p68_L0p15_2F_cell |
| COPY q1s8rf_pshort_W1p68_L0p15_2F_cell |
| } |
| q2s8rf_pshort_W1p68_L0p15_2F_cell = INTERNAL s8rf_pshort_W1p68_L0p15_2F_cell <= 1.11 REGION |
| q3s8rf_pshort_W1p68_L0p15_2F_cell = s8rf_pshort_W1p68_L0p15_2F_cell NOT q2s8rf_pshort_W1p68_L0p15_2F_cell |
| "r_687_diff.13" { |
| @ diff.13: 1.11 max. width of s8rf_pshort_W1p68_L0p15_2F_cell |
| COPY q3s8rf_pshort_W1p68_L0p15_2F_cell |
| } |
| q4s8rf_pshort_W1p68_L0p15_2F_cell = INTERNAL s8rf_pshort_W1p68_L0p15_2F_cell < 1.68 PROJECTING < 1.68 REGION |
| "r_688_diff.13" { |
| @ diff.13: 1.68 min. length of s8rf_pshort_W1p68_L0p15_2F_cell |
| COPY q4s8rf_pshort_W1p68_L0p15_2F_cell |
| } |
| q5s8rf_pshort_W1p68_L0p15_2F_cell = s8rf_pshort_W1p68_L0p15_2F_cell WITH EDGE (LENGTH s8rf_pshort_W1p68_L0p15_2F_cell > 1.68) |
| "r_689_diff.13" { |
| @ diff.13: 1.68 max. length of s8rf_pshort_W1p68_L0p15_2F_cell |
| COPY q5s8rf_pshort_W1p68_L0p15_2F_cell |
| } |
| q0s8rf_pshort_W1p68_L0p15_4F_cell = NOT RECTANGLE s8rf_pshort_W1p68_L0p15_4F_cell ORTHOGONAL ONLY |
| "r_690_diff.13" { |
| @ diff.13: s8rf_pshort_W1p68_L0p15_4F_cell should be rectangular |
| COPY q0s8rf_pshort_W1p68_L0p15_4F_cell |
| } |
| q1s8rf_pshort_W1p68_L0p15_4F_cell = INTERNAL s8rf_pshort_W1p68_L0p15_4F_cell < 1.68 REGION |
| "r_691_diff.13" { |
| @ diff.13: 1.68 min. width of s8rf_pshort_W1p68_L0p15_4F_cell |
| COPY q1s8rf_pshort_W1p68_L0p15_4F_cell |
| } |
| q2s8rf_pshort_W1p68_L0p15_4F_cell = INTERNAL s8rf_pshort_W1p68_L0p15_4F_cell <= 1.68 REGION |
| q3s8rf_pshort_W1p68_L0p15_4F_cell = s8rf_pshort_W1p68_L0p15_4F_cell NOT q2s8rf_pshort_W1p68_L0p15_4F_cell |
| "r_692_diff.13" { |
| @ diff.13: 1.68 max. width of s8rf_pshort_W1p68_L0p15_4F_cell |
| COPY q3s8rf_pshort_W1p68_L0p15_4F_cell |
| } |
| q4s8rf_pshort_W1p68_L0p15_4F_cell = INTERNAL s8rf_pshort_W1p68_L0p15_4F_cell < 1.97 PROJECTING < 1.97 REGION |
| "r_693_diff.13" { |
| @ diff.13: 1.97 min. length of s8rf_pshort_W1p68_L0p15_4F_cell |
| COPY q4s8rf_pshort_W1p68_L0p15_4F_cell |
| } |
| q5s8rf_pshort_W1p68_L0p15_4F_cell = s8rf_pshort_W1p68_L0p15_4F_cell WITH EDGE (LENGTH s8rf_pshort_W1p68_L0p15_4F_cell > 1.97) |
| "r_694_diff.13" { |
| @ diff.13: 1.97 max. length of s8rf_pshort_W1p68_L0p15_4F_cell |
| COPY q5s8rf_pshort_W1p68_L0p15_4F_cell |
| } |
| q0s8rf_pshort_W3p0_L0p15_2F_cell = NOT RECTANGLE s8rf_pshort_W3p0_L0p15_2F_cell ORTHOGONAL ONLY |
| "r_695_diff.13" { |
| @ diff.13: s8rf_pshort_W3p0_L0p15_2F_cell should be rectangular |
| COPY q0s8rf_pshort_W3p0_L0p15_2F_cell |
| } |
| q1s8rf_pshort_W3p0_L0p15_2F_cell = INTERNAL s8rf_pshort_W3p0_L0p15_2F_cell < 1.11 REGION |
| "r_696_diff.13" { |
| @ diff.13: 1.11 min. width of s8rf_pshort_W3p0_L0p15_2F_cell |
| COPY q1s8rf_pshort_W3p0_L0p15_2F_cell |
| } |
| q2s8rf_pshort_W3p0_L0p15_2F_cell = INTERNAL s8rf_pshort_W3p0_L0p15_2F_cell <= 1.11 REGION |
| q3s8rf_pshort_W3p0_L0p15_2F_cell = s8rf_pshort_W3p0_L0p15_2F_cell NOT q2s8rf_pshort_W3p0_L0p15_2F_cell |
| "r_697_diff.13" { |
| @ diff.13: 1.11 max. width of s8rf_pshort_W3p0_L0p15_2F_cell |
| COPY q3s8rf_pshort_W3p0_L0p15_2F_cell |
| } |
| q4s8rf_pshort_W3p0_L0p15_2F_cell = INTERNAL s8rf_pshort_W3p0_L0p15_2F_cell < 3.0 PROJECTING < 3.0 REGION |
| "r_698_diff.13" { |
| @ diff.13: 3 min. length of s8rf_pshort_W3p0_L0p15_2F_cell |
| COPY q4s8rf_pshort_W3p0_L0p15_2F_cell |
| } |
| q5s8rf_pshort_W3p0_L0p15_2F_cell = s8rf_pshort_W3p0_L0p15_2F_cell WITH EDGE (LENGTH s8rf_pshort_W3p0_L0p15_2F_cell > 3.0) |
| "r_699_diff.13" { |
| @ diff.13: 3 max. length of s8rf_pshort_W3p0_L0p15_2F_cell |
| COPY q5s8rf_pshort_W3p0_L0p15_2F_cell |
| } |
| q0s8rf_pshort_W5p0_L0p15_2F_cell = NOT RECTANGLE s8rf_pshort_W5p0_L0p15_2F_cell ORTHOGONAL ONLY |
| "r_700_diff.13" { |
| @ diff.13: s8rf_pshort_W5p0_L0p15_2F_cell should be rectangular |
| COPY q0s8rf_pshort_W5p0_L0p15_2F_cell |
| } |
| q1s8rf_pshort_W5p0_L0p15_2F_cell = INTERNAL s8rf_pshort_W5p0_L0p15_2F_cell < 1.11 REGION |
| "r_701_diff.13" { |
| @ diff.13: 1.11 min. width of s8rf_pshort_W5p0_L0p15_2F_cell |
| COPY q1s8rf_pshort_W5p0_L0p15_2F_cell |
| } |
| q2s8rf_pshort_W5p0_L0p15_2F_cell = INTERNAL s8rf_pshort_W5p0_L0p15_2F_cell <= 1.11 REGION |
| q3s8rf_pshort_W5p0_L0p15_2F_cell = s8rf_pshort_W5p0_L0p15_2F_cell NOT q2s8rf_pshort_W5p0_L0p15_2F_cell |
| "r_702_diff.13" { |
| @ diff.13: 1.11 max. width of s8rf_pshort_W5p0_L0p15_2F_cell |
| COPY q3s8rf_pshort_W5p0_L0p15_2F_cell |
| } |
| q4s8rf_pshort_W5p0_L0p15_2F_cell = INTERNAL s8rf_pshort_W5p0_L0p15_2F_cell < 5.0 PROJECTING < 5.0 REGION |
| "r_703_diff.13" { |
| @ diff.13: 5 min. length of s8rf_pshort_W5p0_L0p15_2F_cell |
| COPY q4s8rf_pshort_W5p0_L0p15_2F_cell |
| } |
| q5s8rf_pshort_W5p0_L0p15_2F_cell = s8rf_pshort_W5p0_L0p15_2F_cell WITH EDGE (LENGTH s8rf_pshort_W5p0_L0p15_2F_cell > 5.0) |
| "r_704_diff.13" { |
| @ diff.13: 5 max. length of s8rf_pshort_W5p0_L0p15_2F_cell |
| COPY q5s8rf_pshort_W5p0_L0p15_2F_cell |
| } |
| s8rf_nlowvt_poly = INSIDE CELL poly s8rf_nlowvt_W0p42_L0p15_2F s8rf_nlowvt_W0p84_L0p15_2F s8rf_nlowvt_W0p84_L0p15_4F s8rf_nlowvt_W0p84_L0p15_8F s8rf_nlowvt_W3p0_L0p15_2F s8rf_nlowvt_W3p0_L0p15_4F s8rf_nlowvt_W3p0_L0p15_8F |
| s8rf_nlowvt_diff = INSIDE CELL diff s8rf_nlowvt_W0p42_L0p15_2F s8rf_nlowvt_W0p84_L0p15_2F s8rf_nlowvt_W0p84_L0p15_4F s8rf_nlowvt_W0p84_L0p15_8F s8rf_nlowvt_W3p0_L0p15_2F s8rf_nlowvt_W3p0_L0p15_4F s8rf_nlowvt_W3p0_L0p15_8F |
| s8rf_pshort_poly = INSIDE CELL poly s8rf_pshort_W0p84_L0p15_2F s8rf_pshort_W1p68_L0p15_2F s8rf_pshort_W1p68_L0p15_4F s8rf_pshort_W3p0_L0p15_2F s8rf_pshort_W5p0_L0p15_2F |
| s8rf_pshort_diff = INSIDE CELL diff s8rf_pshort_W0p84_L0p15_2F s8rf_pshort_W1p68_L0p15_2F s8rf_pshort_W1p68_L0p15_4F s8rf_pshort_W3p0_L0p15_2F s8rf_pshort_W5p0_L0p15_2F |
| s8rf_H5_err = INTERACT s8rf_nlowvt_poly s8rf_pshort_poly |
| s8rf_nlowvt_err = INTERACT s8rf_nlowvt_poly s8rf_nlowvt_diff > 1 |
| s8rf_pshort_err = INTERACT s8rf_pshort_poly s8rf_pshort_diff > 1 |
| s8rf_H5_err_all = s8rf_H5_err OR |
| (s8rf_nlowvt_err OR s8rf_pshort_err) |
| "r_705_poly.16" { |
| @ poly.16: Poly of the RF FETs defined in Table H5 cannot overlap |
| COPY s8rf_H5_err_all |
| } |
| "r_706_npc.1" { |
| @ npc.1: 0.27 min. width of npc |
| INTERNAL npc < 0.27 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_707_npc.2" { |
| @ npc.2: 0.27 min. spacing/notch of npc |
| EXTERNAL npc < 0.27 ABUT < 90 SINGULAR REGION |
| } |
| /// npc.3 is handled by design |
| "r_708_npc.4" { |
| @ npc.4: 0.09 min. spacing of npc & gate |
| EXTERNAL npc GATE < 0.09 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_709_npc.4" { |
| @ npc.4: npc must not overlap gate |
| npc AND GATE |
| } |
| LCON1AndRpm = rectLCON1 AND (rpm OR urpm) |
| slotted_licon = (WITH WIDTH LCON1AndRpm == 0.19) WITH EDGE (LENGTH LCON1AndRpm == 2.0) |
| poly_with_slotlicon = poly ENCLOSE slotted_licon |
| npc_no_hrpoly = NOT INTERACT npc poly_with_slotlicon |
| poly_edges_horiz = ANGLE poly_with_slotlicon == 0 |
| poly_edges_vert = ANGLE poly_with_slotlicon == 90 |
| hrpoly_horiz = DFM PROPERTY poly_with_slotlicon poly_edges_horiz poly_edges_vert OVERLAP |
| ["-" = length( poly_edges_horiz ) - length( poly_edges_vert )] > 0 |
| hrpoly_vert = poly_with_slotlicon NOT hrpoly_horiz |
| valid_npc = SIZE poly_with_slotlicon BY 0.095 |
| npc_merge = EXTERNAL valid_npc < 0.27 ABUT < 90 SINGULAR REGION PARALLEL OPPOSITE |
| valid_npc_final = (valid_npc OR npc_merge) OR npc_no_hrpoly |
| hrpoly_horiz_edges = EXPAND EDGE (ANGLE hrpoly_horiz == 0) OUTSIDE BY 0.1 |
| hrpoly_vert_edges = EXPAND EDGE (ANGLE hrpoly_vert == 90) OUTSIDE BY 0.1 |
| npc_no_slot = ((hrpoly_horiz_edges OR hrpoly_vert_edges) AND npc) NOT valid_npc_final |
| "r_710_npc.5" { |
| @ npc.5: 0.095 max enclosure of poly overlapping slotted_licon by npcm |
| COPY npc_no_slot |
| } |
| ringLCON1 = DONUT licon1 |
| rectLCON1 = licon1 NOT ringLCON1 |
| badLCON1 = licon1 OUTSIDE (li1 AND (poly OR diffTap)) |
| ButtTap = tap WITH EDGE (tap COINCIDENT OUTSIDE EDGE diff) |
| noButtTap = tap NOT ButtTap |
| tapLicon_PERI = licon1_PERI AND tap |
| varactorLicon1 = licon1 AND lvNtap |
| varLiconPer = (licon1 AND lvNtap) NOT COREID |
| phighvt15 = WITH WIDTH phighvt == 0.15 |
| gateSC = GATE AND STDCID |
| gateSCPhighvt = gateSC AND phighvt15 |
| gateSCnoPhighvt = gateSC NOT phighvt15 |
| licon11cGateCell = INSIDE CELL poly s8fs_gwdlvx4 s8fs_gwdlvx8 s8fs_hvrsw_x4 s8fs_hvrsw8 s8fs_hvrsw264 s8fs_hvrsw520 |
| licon11dGateCell = INSIDE CELL poly s8fs_rdecdrv s8fs_rdec8 s8fs_rdec32 s8fs_rdec264 s8fs_rdec520 |
| licon11cGate = INTERACT licon11cGateCell (EXPAND EDGE (LENGTH (phv COINCIDENT INSIDE EDGE diff) == 0.5) INSIDE BY 0.005) |
| licon11dGate = licon11dGateCell AND (WITH WIDTH nshort == 0.15) |
| gateNoSC = GATE NOT (STDCID OR |
| (licon11cGate OR licon11dGate)) |
| liconInSource = licon1 INSIDE source_diffusion_PERI |
| invalid_src_diff = (source_diffusion_PERI OUTSIDE liconInSource) NOT UHVI |
| npcon_tap = tap_PERI OR (CUT tap COREID) |
| liconInTap = licon1 INSIDE npcon_tap |
| invalid_tap = npcon_tap OUTSIDE liconInTap |
| invalid_tap_outuhvi = invalid_tap NOT uhvi |
| liconOverPoly = INTERACT licon1 (licon1 AND poly) |
| npcOutsidePolyLicon = npc NOT ENCLOSE polyLicon1 |
| badLiconInFGR = licon1 AND PolyInFGR |
| "r_711_licon.2" { |
| @ licon.2: 0.17 min. spacing/notch of "licon1" in periphery |
| EXTERNAL licon1_PERI < 0.17 ABUT < 90 SINGULAR REGION |
| } |
| "r_712_licon.2" { |
| @ licon.2: 0.17 min. spacing of licon1 across COREID boundary |
| EXTERNAL licon1_CORE licon1_PERI > 0 < 0.17 ABUT > 0 < 90 SINGULAR REGION |
| } |
| "r_713_licon.3" { |
| @ licon.3: 0.17 min. width of ring licon1 |
| INTERNAL ringLCON1 < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_714_licon.3" { |
| @ licon.3: 0.175 max. width of ring licon1 |
| q0ringLCON1 = SIZE ringLCON1 BY -0.087 |
| SIZE q0ringLCON1 BY 0.087 |
| } |
| "r_715_licon.3" { |
| @ licon.3: ring licon1 must be enclosed by SEALID |
| ringLCON1 NOT SEALID |
| } |
| "r_716_licon.4" { |
| @ licon.4: licon1 must overlap li1 and (poly or diff or tap) |
| COPY badLCON1 |
| } |
| "r_717_licon.5a" { |
| @ licon.5a: 0.04 min. enclosure of "licon1" in periphery by diff |
| q0licon1_PERIand = licon1_PERI AND diff |
| ENCLOSURE q0licon1_PERIand diff < 0.04 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_718_licon.5b" { |
| @ licon.5b: 0.06 min. spacing of tapLicon_PERI & diffTap butting edge |
| EXTERNAL tapLicon_PERI diffTapButtEdge < 0.06 ABUT < 90 REGION EXCLUDE FALSE |
| } |
| "r_719_licon.5c" { |
| @ licon.5c: 0.06 min. enclosure of adj. sides of "licon1" in periphery by diff |
| q14diffenc = ENCLOSURE [licon1_PERI] diff < 0.06 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q14diffenc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_720_licon.6" { |
| @ licon.6: "licon1" in periphery must not straddle tap |
| CUT licon1_PERI tap |
| } |
| "r_721_licon.7" { |
| @ licon.7: 0.12 min. enclosure of adj. sides of "licon1" in periphery by noButtTap |
| q0noButtTapenc = ENCLOSURE [licon1_PERI] noButtTap < 0.12 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q0noButtTapenc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_722_licon.8" { |
| @ licon.8: 0.05 min. enclosure of "poly_licon1" in periphery by poly |
| q0polyLicon1_PERIand = polyLicon1_PERI AND poly |
| ENCLOSURE q0polyLicon1_PERIand poly < 0.05 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_723_licon.8a" { |
| @ licon.8a: 0.08 min. enclosure of adj. sides of "poly_licon1" in periphery by poly |
| q9polyenc = ENCLOSURE [polyLicon1_PERI] poly < 0.08 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q9polyenc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_724_licon.10" { |
| @ licon.10: 0.25 min. spacing of varLiconPer & varChannel |
| EXTERNAL varLiconPer varChannel_drc < 0.25 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_725_licon.11" { |
| @ licon.11: 0.055 min. spacing of "licon1 on diffTap" in periphery & gateNoSC |
| EXTERNAL licon1ToXfom_PERI gateNoSC < 0.055 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_726_licon.11" { |
| @ licon.11: "licon1 on diffTap" in periphery must not overlap gateNoSC |
| licon1ToXfom_PERI AND gateNoSC |
| } |
| "r_727_licon.11a" { |
| @ licon.11a: 0.05 min. spacing of "licon1 on diffTap" in periphery & (gate and areaid.sc) except 0.15 phighvt |
| EXTERNAL licon1ToXfom_PERI gateSCnoPhighvt < 0.05 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_728_licon.11a" { |
| @ licon.11a: "licon1 on diffTap" in periphery must not overlap (gate and areaid.sc) except 0.15 phighvt |
| licon1ToXfom_PERI AND gateSCnoPhighvt |
| } |
| "r_729_licon.11b" { |
| @ licon.11b: 0.05 min. spacing of "licon1 on diffTap" in periphery & gateSCPhighvt |
| EXTERNAL licon1ToXfom_PERI gateSCPhighvt < 0.05 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_730_licon.11b" { |
| @ licon.11b: "licon1 on diffTap" in periphery must not overlap gateSCPhighvt |
| licon1ToXfom_PERI AND gateSCPhighvt |
| } |
| "r_731_licon.11c" { |
| @ licon.11c: 0.04 min. spacing of "licon1 on diffTap" in periphery & licon11cGate |
| EXTERNAL licon1ToXfom_PERI licon11cGate < 0.04 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_732_licon.11c" { |
| @ licon.11c: "licon1 on diffTap" in periphery must not overlap licon11cGate |
| licon1ToXfom_PERI AND licon11cGate |
| } |
| "r_733_licon.11d" { |
| @ licon.11d: 0.045 min. spacing of "licon1 on diffTap" in periphery & licon11dGate |
| EXTERNAL licon1ToXfom_PERI licon11dGate < 0.045 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_734_licon.11d" { |
| @ licon.11d: "licon1 on diffTap" in periphery must not overlap licon11dGate |
| licon1ToXfom_PERI AND licon11dGate |
| } |
| /// licon.12 is not checked |
| polyLicon1OutRpm = polyLicon1_PERI NOT (rpm OR urpm) |
| rectLCON1OutRpm = rectLCON1 NOT (rpm OR urpm) |
| rectLCON1AndRpm = rectLCON1 AND (rpm OR urpm) |
| precResLateral = EXTERNAL rectLCON1AndRpm < 0.51 ABUT < 90 SINGULAR REGION |
| precResLCON_2 = LENGTH rectLCON1AndRpm == 2.0 |
| precResLCON_2edge = precResLateral COINCIDENT EDGE precResLCON_2 |
| Invalid_licon_2c = precResLateral WITH EDGE precResLCON_2edge |
| q0rectLCON1OutRpm = NOT RECTANGLE rectLCON1OutRpm ORTHOGONAL ONLY |
| "r_735_licon.1" { |
| @ licon.1: rectLCON1OutRpm should be rectangular |
| COPY q0rectLCON1OutRpm |
| } |
| q1rectLCON1OutRpm = INTERNAL rectLCON1OutRpm < 0.17 REGION |
| "r_736_licon.1" { |
| @ licon.1: 0.17 min. width of rectLCON1OutRpm |
| COPY q1rectLCON1OutRpm |
| } |
| q2rectLCON1OutRpm = rectLCON1OutRpm WITH EDGE (LENGTH rectLCON1OutRpm > 0.17) |
| "r_737_licon.1" { |
| @ licon.1: 0.17 max. length of rectLCON1OutRpm |
| COPY q2rectLCON1OutRpm |
| } |
| q0rectLCON1AndRpm = NOT RECTANGLE rectLCON1AndRpm ORTHOGONAL ONLY |
| "r_738_licon.1b/c" { |
| @ licon.1b/c: rectLCON1AndRpm should be rectangular |
| COPY q0rectLCON1AndRpm |
| } |
| q1rectLCON1AndRpm = INTERNAL rectLCON1AndRpm < 0.19 REGION |
| "r_739_licon.1b/c" { |
| @ licon.1b/c: 0.19 min. width of rectLCON1AndRpm |
| COPY q1rectLCON1AndRpm |
| } |
| q2rectLCON1AndRpm = INTERNAL rectLCON1AndRpm <= 0.19 REGION |
| q3rectLCON1AndRpm = rectLCON1AndRpm NOT q2rectLCON1AndRpm |
| "r_740_licon.1b/c" { |
| @ licon.1b/c: 0.19 max. width of rectLCON1AndRpm |
| COPY q3rectLCON1AndRpm |
| } |
| q4rectLCON1AndRpm = INTERNAL rectLCON1AndRpm < 2.0 PROJECTING < 2.0 REGION |
| "r_741_licon.1b/c" { |
| @ licon.1b/c: 2 min. length of rectLCON1AndRpm |
| COPY q4rectLCON1AndRpm |
| } |
| q5rectLCON1AndRpm = rectLCON1AndRpm WITH EDGE (LENGTH rectLCON1AndRpm > 2.0) |
| "r_742_licon.1b/c" { |
| @ licon.1b/c: 2 max. length of rectLCON1AndRpm |
| COPY q5rectLCON1AndRpm |
| } |
| "r_743_licon.2b" { |
| @ licon.2b: 0.35 min. spacing/notch of rectLCON1AndRpm |
| EXTERNAL rectLCON1AndRpm < 0.35 ABUT < 90 SINGULAR REGION |
| } |
| "r_744_licon.2c" { |
| @ licon.2c: min spacing between slotted licon in lateral dir is 0.510 |
| COPY Invalid_licon_2c |
| } |
| "r_745_licon.2d" { |
| @ licon.2d: 0.51 min. spacing of rectLCON1AndRpm & rectLCON1OutRpm |
| EXTERNAL rectLCON1AndRpm rectLCON1OutRpm < 0.51 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_746_licon.9" { |
| @ licon.9: 0.11 min. spacing of polyLicon1OutRpm & psdm |
| EXTERNAL polyLicon1OutRpm psdm < 0.11 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_747_licon.9" { |
| @ licon.9: polyLicon1OutRpm must not overlap psdm |
| polyLicon1OutRpm AND psdm |
| } |
| "r_748_licon.13" { |
| @ licon.13: 0.09 min. spacing of "licon1 on diffTap" in periphery & npc |
| EXTERNAL licon1ToXfom_PERI npc < 0.09 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_749_licon.13" { |
| @ licon.13: "licon1 on diffTap" in periphery must not overlap npc |
| licon1ToXfom_PERI AND npc |
| } |
| "r_750_licon.14" { |
| @ licon.14: 0.19 min. spacing of poly_licon1 & "diffTap" in periphery |
| EXTERNAL polyLicon1 diffTap_PERI < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_751_licon.15" { |
| @ licon.15: 0.1 min. enclosure of "poly_licon1" in periphery by npc |
| q1polyLicon1_PERIand = polyLicon1_PERI AND npc |
| ENCLOSURE q1polyLicon1_PERIand npc < 0.1 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_752_licon.15" { |
| @ licon.15: "poly_licon1" in periphery must be enclosed by npc |
| polyLicon1_PERI NOT npc |
| } |
| "r_753_npcon.c6" { |
| @ npcon.c6: 0.045 min. enclosure of "poly_licon1" in core by npc |
| q0polyLicon1_COREand = polyLicon1_CORE AND npc |
| ENCLOSURE q0polyLicon1_COREand npc < 0.045 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_754_npcon.c6" { |
| @ npcon.c6: "poly_licon1" in core must be enclosed by npc |
| polyLicon1_CORE NOT npc |
| } |
| "r_755_licon.16" { |
| @ licon.16: source must enclose at least one licon in peri |
| COPY invalid_src_diff |
| } |
| "r_756_licon.16" { |
| @ licon.16: tap must enclose at least one licon in peri |
| COPY invalid_tap_outuhvi |
| } |
| "r_757_licon.17" { |
| @ licon.17: licon1 overlapping poly must not overlap diffTap |
| liconOverPoly AND diffTap |
| } |
| "r_758_licon.18" { |
| @ licon.18: npc must enclose poly_licon |
| COPY npcOutsidePolyLicon |
| } |
| "r_759_licon.19" { |
| @ licon.19: poly on HV varactor must not interact with licon |
| COPY badLiconInFGR |
| } |
| "r_760_licon.c1" { |
| @ licon.c1: 0.13 min. spacing of poly_licon1 & "diffTap" in core |
| EXTERNAL polyLicon1 diffTap_CORE < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_761_licon.c3" { |
| @ licon.c3: 0.165 min. spacing/notch of "licon1" in core |
| EXTERNAL licon1_CORE < 0.165 ABUT < 90 SINGULAR REGION |
| } |
| "r_762_licon.c4" { |
| @ licon.c4: "poly_licon1" in core must not overlap psdm |
| polyLicon1_CORE AND psdm |
| } |
| vpp_hd5 = EXTENT CELL "s8rf2_xcmvpp_hd5_*" |
| liVppCaps = li1 AND vpp_hd5 |
| liNoVppCaps = li1 NOT liVppCaps |
| li1_3_PERI = liNoVppCaps NOT COREID |
| li1_3a_PERI = liVppCaps NOT COREID |
| q0liNoVppCaps = INTERNAL liNoVppCaps < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q3liNoVppCaps = q0liNoVppCaps OUTSIDE COREID |
| q7liNoVppCaps = liNoVppCaps NOT COREID |
| q6liNoVppCaps = INTERNAL q7liNoVppCaps < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q1liNoVppCaps = q6liNoVppCaps INSIDE (CUT q0liNoVppCaps COREID) |
| q2liNoVppCaps = SIZE q1liNoVppCaps BY 0.005 INSIDE OF q0liNoVppCaps STEP 0.17 |
| "r_763_li.1" { |
| @ li.1: 0.17 min. width of liNoVppCaps across areaid:ce |
| COPY q2liNoVppCaps |
| } |
| "r_764_li.1" { |
| @ li.1: 0.17 min. width of liNoVppCaps in PERI |
| COPY q3liNoVppCaps |
| } |
| q4liNoVppCaps = INTERNAL liNoVppCaps < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| q5liNoVppCaps = q4liNoVppCaps INSIDE COREID |
| "r_765_li.c1" { |
| @ li.c1: 0.14 min. width of liNoVppCaps in COREID |
| COPY q5liNoVppCaps |
| } |
| "r_766_li.1a" { |
| @ li.1a: 0.14 min. width of liVppCaps |
| INTERNAL liVppCaps < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| /// li.2 is not checked |
| "r_767_li.3" { |
| @ li.3: 0.17 min. spacing/notch of li1_3_PERI |
| EXTERNAL li1_3_PERI < 0.17 ABUT < 90 SINGULAR REGION |
| } |
| "r_768_li.3" { |
| @ li.3: 0.17 min. spacing of li1 across COREID boundary |
| EXTERNAL li1_CORE li1_PERI > 0 < 0.17 ABUT > 0 < 90 SINGULAR REGION |
| } |
| "r_769_li.3a" { |
| @ li.3a: 0.14 min. spacing/notch of li1_3a_PERI |
| EXTERNAL li1_3a_PERI < 0.14 ABUT < 90 SINGULAR REGION |
| } |
| "r_770_li.4" { |
| @ li.4: "licon1" in periphery must be enclosed by li1 |
| licon1_PERI NOT li1 |
| } |
| "r_771_li.5" { |
| @ li.5: 0.08 min. enclosure of adj. sides of "licon1" in periphery by li1 |
| q2li1enc = ENCLOSURE [licon1_PERI] li1 < 0.08 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q2li1enc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| q2li1 = AREA li1 < 0.0561 |
| q4li1 = q2li1 OUTSIDE COREID |
| q3li1 = CUT q2li1 COREID |
| "r_772_li.6" { |
| @ li.6: 0.0561 min. area of li1 across areaid:ce |
| COPY q3li1 |
| } |
| "r_773_li.6" { |
| @ li.6: 0.0561 min. area of li1 |
| COPY q4li1 |
| } |
| li1AndRes = li1res AND li1 |
| li1NoRes = li1 NOT li1AndRes |
| li1AndResNoESD = li1AndRes NOT ESDID |
| "r_774_li.7" { |
| @ li.7: 0.29 min. width of li1AndResNoESD |
| INTERNAL li1AndResNoESD < 0.29 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_775_li.c1" { |
| @ li.c1: 0.14 min. width of "li1" in core |
| INTERNAL li1_CORE < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_776_li.c2" { |
| @ li.c2: 0.14 min. spacing/notch of "li1" in core |
| EXTERNAL li1_CORE < 0.14 ABUT < 90 SINGULAR REGION |
| } |
| ringMCON = DONUT mcon |
| rectMCON = mcon NOT ringMCON |
| q0rectMCON = NOT RECTANGLE rectMCON ORTHOGONAL ONLY |
| "r_777_ct.1" { |
| @ ct.1: non-ring mcon should be rectangular |
| COPY q0rectMCON |
| } |
| q1rectMCON = INTERNAL rectMCON < 0.17 REGION |
| "r_778_ct.1" { |
| @ ct.1: 0.17 min. width of non-ring mcon |
| COPY q1rectMCON |
| } |
| q2rectMCON = rectMCON WITH EDGE (LENGTH rectMCON > 0.17) |
| "r_779_ct.1" { |
| @ ct.1: 0.17 max. length of non-ring mcon |
| COPY q2rectMCON |
| } |
| "r_780_ct.2" { |
| @ ct.2: 0.19 min. spacing/notch of mcon |
| EXTERNAL mcon < 0.19 ABUT < 90 SINGULAR REGION |
| } |
| "r_781_ct.3" { |
| @ ct.3: 0.17 min. width of ring-shaped mcon |
| INTERNAL ringMCON < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_782_ct.3" { |
| @ ct.3: 0.175 max. width of ring-shaped mcon |
| q0ringMCON = SIZE ringMCON BY -0.087 |
| SIZE q0ringMCON BY 0.087 |
| } |
| "r_783_ct.3" { |
| @ ct.3: ring-shaped mcon must be enclosed by SEALID |
| ringMCON NOT SEALID |
| } |
| "r_784_ct.4" { |
| @ ct.4: "mcon" in periphery must be enclosed by li1 |
| mcon_PERI NOT li1 |
| } |
| "r_785_ct.c1" { |
| @ ct.c1: "mcon" in core must overlap li1 |
| mcon_CORE OUTSIDE li1 |
| } |
| "r_786_ct.c2" { |
| @ ct.c2: 0.19 min. spacing/notch of "mcon" in core |
| EXTERNAL mcon_CORE < 0.19 ABUT < 90 SINGULAR REGION |
| } |
| "r_787_m1.1" { |
| @ m1.1: 0.14 min. width of met1 |
| INTERNAL met1 < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_788_m1.2" { |
| @ m1.2: 0.14 min. spacing/notch of met1 |
| EXTERNAL met1 < 0.14 ABUT < 90 SINGULAR REGION |
| } |
| q0Hugemet1 = WITH WIDTH met1 > 3.0 |
| q1Hugemet1 = SIZE q0Hugemet1 BY 0.28 INSIDE OF met1 STEP 0.28 |
| q2Hugemet1 = q1Hugemet1 NOT q0Hugemet1 |
| q3Hugemet1 = q2Hugemet1 WITH EDGE (q2Hugemet1 COINCIDENT OUTSIDE EDGE q0Hugemet1) |
| q4Hugemet1 = q3Hugemet1 OR q0Hugemet1 |
| q5Hugemet1 = SNAP q4Hugemet1 1 |
| q6Hugemet1 = met1 NOT q5Hugemet1 |
| q7Hugemet1 = EXTERNAL q0Hugemet1 q6Hugemet1 <= 0.275 REGION |
| q8Hugemet1 = q7Hugemet1 NOT (q7Hugemet1 INSIDE met1) |
| q9Hugemet1 = EXTERNAL q5Hugemet1 < 0.28 ABUT < 90 REGION |
| q10Hugemet1 = q9Hugemet1 NOT (INTERACT q9Hugemet1 (q9Hugemet1 AND met1)) |
| "r_789_m1.3b" { |
| @ m1.3b: 0.28 min. spacing between huge met1 and normal met1 |
| COPY q8Hugemet1 |
| } |
| "r_790_m1.3a" { |
| @ m1.3a: 0.28 min. spacing/notch of huge met1+nearby met1 |
| COPY q10Hugemet1 |
| } |
| s8spf_cells_m1_4 = EXTENT CELL "s8fs_cmux4_fm" ORIGINAL |
| mcon_PERI_4a = mcon_PERI AND s8spf_cells_m1_4 |
| mcon_PERI_4 = mcon_PERI NOT mcon_PERI_4a |
| "r_791_m1.4" { |
| @ m1.4: 0.03 min. enclosure of mcon_PERI_4 by met1 |
| q0mcon_PERI_4and = mcon_PERI_4 AND met1 |
| ENCLOSURE q0mcon_PERI_4and met1 < 0.03 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_792_m1.4" { |
| @ m1.4: mcon_PERI_4 must be enclosed by met1 |
| mcon_PERI_4 NOT met1 |
| } |
| "r_793_m1.4a" { |
| @ m1.4a: 0.005 min. enclosure of mcon_PERI_4a by met1 |
| q0mcon_PERI_4aand = mcon_PERI_4a AND met1 |
| ENCLOSURE q0mcon_PERI_4aand met1 < 0.005 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_794_m1.4a" { |
| @ m1.4a: mcon_PERI_4a must be enclosed by met1 |
| mcon_PERI_4a NOT met1 |
| } |
| "r_795_m1.5" { |
| @ m1.5: 0.06 min. enclosure of adj. sides of "mcon" in periphery by met1 |
| q0met1enc = ENCLOSURE [mcon_PERI] met1 < 0.06 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q0met1enc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_796_m1.6" { |
| @ m1.6: 0.083 min. area of met1 |
| AREA met1 < 0.083 |
| } |
| met1Hole = HOLES met1 |
| met1HoleEmpty = HOLES met1 INNER |
| "r_797_m1.7" { |
| @ m1.7: 0.14 min. area of met1Hole |
| AREA met1Hole < 0.14 |
| } |
| "r_798_m1.7" { |
| @ m1.7: 0.14 min. area of met1HoleEmpty |
| AREA met1HoleEmpty < 0.14 |
| } |
| "r_799_m1.c1" { |
| @ m1.c1: "mcon" in core must be enclosed by met1 |
| mcon_CORE NOT met1 |
| } |
| ringVIA = DONUT via |
| rectVIA = via NOT ringVIA |
| rectVIAnoMT = rectVIA NOT moduleCutAREA |
| rectVIAMT = rectVIA AND moduleCutAREA |
| rectVIAMTA = RECTANGLE rectVIAMT == 0.15 BY == 0.15 ORTHOGONAL ONLY |
| rectVIAMTB = RECTANGLE rectVIAMT == 0.23 BY == 0.23 ORTHOGONAL ONLY |
| rectVIAMTC = RECTANGLE rectVIAMT == 0.28 BY == 0.28 ORTHOGONAL ONLY |
| rectVIAMTbad = rectVIAMT NOT (rectVIAMTA OR (rectVIAMTB OR rectVIAMTC)) |
| rectVIAa = RECTANGLE rectVIA == 0.15 BY == 0.15 ORTHOGONAL ONLY |
| q0rectVIAnoMT = NOT RECTANGLE rectVIAnoMT ORTHOGONAL ONLY |
| "r_800_via.1a" { |
| @ via.1a: via outside of moduleCut should be rectangular |
| COPY q0rectVIAnoMT |
| } |
| q1rectVIAnoMT = INTERNAL rectVIAnoMT < 0.15 REGION |
| "r_801_via.1a" { |
| @ via.1a: 0.15 min. width of via outside of moduleCut |
| COPY q1rectVIAnoMT |
| } |
| q2rectVIAnoMT = rectVIAnoMT WITH EDGE (LENGTH rectVIAnoMT > 0.15) |
| "r_802_via.1a" { |
| @ via.1a: 0.15 max. length of via outside of moduleCut |
| COPY q2rectVIAnoMT |
| } |
| "r_803_via.1b" { |
| @ via.1b: via size inside module cut must be 0.150 or 0.230 or 0.280 |
| COPY rectVIAMTbad |
| } |
| "r_804_via.2" { |
| @ via.2: 0.17 min. spacing/notch of via |
| EXTERNAL via < 0.17 ABUT < 90 SINGULAR REGION |
| } |
| "r_805_via.3" { |
| @ via.3: 0.2 min. width of ring-shaped via |
| INTERNAL ringVIA < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_806_via.3" { |
| @ via.3: 0.205 max. width of ring-shaped via |
| q0ringVIA = SIZE ringVIA BY -0.102 |
| SIZE q0ringVIA BY 0.102 |
| } |
| "r_807_via.3" { |
| @ via.3: ring-shaped via must be enclosed by SEALID |
| ringVIA NOT SEALID |
| } |
| "r_808_via.4a" { |
| @ via.4a: 0.055 min. enclosure of 0.15um via by met1 |
| q0rectVIAaand = rectVIAa AND met1 |
| ENCLOSURE q0rectVIAaand met1 < 0.055 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_809_via.4a" { |
| @ via.4a: 0.15um via must be enclosed by met1 |
| rectVIAa NOT met1 |
| } |
| "r_810_via.4b" { |
| @ via.4b: 0.03 min. enclosure of 0.23 via within modulecut by met1 |
| q0rectVIAMTBand = rectVIAMTB AND met1 |
| ENCLOSURE q0rectVIAMTBand met1 < 0.03 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_811_via.4b" { |
| @ via.4b: 0.23 via within modulecut must be enclosed by met1 |
| rectVIAMTB NOT met1 |
| } |
| "r_812_via.4c" { |
| @ via.4c: 0 min. enclosure of 0.28 via within modulecut by met1 |
| q0rectVIAMTCand = rectVIAMTC AND met1 |
| rectVIAMTC NOT met1 |
| } |
| "r_813_via.4c" { |
| @ via.4c: 0.28 via within modulecut must be enclosed by met1 |
| rectVIAMTC NOT met1 |
| } |
| "r_814_via.5a" { |
| @ via.5a: 0.085 min. enclosure of adj. sides of 0.15um via by met1 |
| q1met1enc = ENCLOSURE [rectVIAa] met1 < 0.085 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q1met1enc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_815_via.5b" { |
| @ via.5b: 0.06 min. enclosure of adj. sides of 0.23 via within modulecut by met1 |
| q2met1enc = ENCLOSURE [rectVIAMTB] met1 < 0.06 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q2met1enc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_816_via.5c" { |
| @ via.5c: 0 min. enclosure of adj. sides of 0.28 via within modulecut by met1 |
| q3met1enc = rectVIAMTC NOT met1 |
| NOT RECTANGLE q3met1enc ORTHOGONAL ONLY |
| } |
| CONNECT SRCDRN li1 BY licon1 |
| CONNECT PTAP li1 BY licon1 |
| met2Conntap = NET AREA RATIO met2 tap > 0 |
| met2Conndiff = NET AREA RATIO met2 SRCDRN > 0 |
| met2ConnPtap = NET AREA RATIO met2 PTAP > 0 |
| met2Conndifftap = met2Conntap OR met2Conndiff |
| met2NotConndifftap = met2 NOT met2Conndifftap |
| met2NotConnVia = INTERACT met2NotConndifftap via2 > 2 |
| met2GroundOrFloat = met2ConnPtap OR met2NotConndifftap |
| met2GroundOrFloatVia = INTERACT met2GroundOrFloat via2 > 2 |
| met3_via2 = INTERACT met3 via2 |
| met3_over_floatingm2 = met3_via2 AND met2GroundOrFloat |
| CONNECT met2NotConnVia met3_over_floatingm2 by via2 |
| CONNECT met2GroundOrFloatVia met3_over_floatingm2 by via2 |
| crater = (EXTERNAL AR_MM2_more05 AR_MM2_less03 == 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE) NOT STDCID |
| AR_MM2_more05 = NET AREA RATIO met2NotConnVia via2 >= 0.05 [(AREA(via2))/(2*AREA(met2NotConnVia) +PERIMETER(met2NotConnVia) *0.35)] |
| AR_MM2_less03 = NET AREA RATIO met2GroundOrFloatVia via2 <= 0.032 [(AREA(via2))/(2*AREA(met2GroundOrFloatVia)+PERIMETER(met2GroundOrFloatVia)*0.35)] |
| "s_8_m2.3c" { |
| @ m2.3c: Crater: spacing matches between met2 areas with via2-to-SurfaceArea ratio >=0.05 and =< 0.032 |
| COPY crater |
| } |
| "r_817_m2.1" { |
| @ m2.1: 0.14 min. width of met2 |
| INTERNAL met2 < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_818_m2.2" { |
| @ m2.2: 0.14 min. spacing/notch of met2 |
| EXTERNAL met2 < 0.14 ABUT < 90 SINGULAR REGION |
| } |
| q0Hugemet2 = WITH WIDTH met2 > 3.0 |
| q1Hugemet2 = SIZE q0Hugemet2 BY 0.28 INSIDE OF met2 STEP 0.28 |
| q2Hugemet2 = q1Hugemet2 NOT q0Hugemet2 |
| q3Hugemet2 = q2Hugemet2 WITH EDGE (q2Hugemet2 COINCIDENT OUTSIDE EDGE q0Hugemet2) |
| q4Hugemet2 = q3Hugemet2 OR q0Hugemet2 |
| q5Hugemet2 = SNAP q4Hugemet2 1 |
| q6Hugemet2 = met2 NOT q5Hugemet2 |
| q7Hugemet2 = EXTERNAL q0Hugemet2 q6Hugemet2 <= 0.275 REGION |
| q8Hugemet2 = q7Hugemet2 NOT (q7Hugemet2 INSIDE met2) |
| q9Hugemet2 = EXTERNAL q5Hugemet2 < 0.28 ABUT < 90 REGION |
| q10Hugemet2 = q9Hugemet2 NOT (INTERACT q9Hugemet2 (q9Hugemet2 AND met2)) |
| "r_819_m2.3b" { |
| @ m2.3b: 0.28 min. spacing between huge met2 and normal met2 |
| COPY q8Hugemet2 |
| } |
| "r_820_m2.3a" { |
| @ m2.3a: 0.28 min. spacing/notch of huge met2+nearby met2 |
| COPY q10Hugemet2 |
| } |
| "r_821_m2.4" { |
| @ m2.4: 0.055 min. enclosure of "via" in periphery by met2 |
| q0via_PERIand = via_PERI AND met2 |
| ENCLOSURE q0via_PERIand met2 < 0.055 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_822_m2.4" { |
| @ m2.4: "via" in periphery must be enclosed by met2 |
| via_PERI NOT met2 |
| } |
| "r_823_m2.5" { |
| @ m2.5: 0.085 min. enclosure of adj. sides of via by met2 |
| q0met2enc = ENCLOSURE [via] met2 < 0.085 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q0met2enc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_824_m2.6" { |
| @ m2.6: 0.0676 min. area of met2 |
| AREA met2 < 0.0676 |
| } |
| met2Hole = HOLES met2 |
| met2HoleEmpty = HOLES met2 INNER |
| "r_825_m2.7" { |
| @ m2.7: 0.14 min. area of met2Hole |
| AREA met2Hole < 0.14 |
| } |
| "r_826_m2.7" { |
| @ m2.7: 0.14 min. area of met2HoleEmpty |
| AREA met2HoleEmpty < 0.14 |
| } |
| "r_827_m2.c4" { |
| @ m2.c4: 0.04 min. enclosure of "via" in core by met2 |
| q0via_COREand = via_CORE AND met2 |
| ENCLOSURE q0via_COREand met2 < 0.04 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_828_m2.c4" { |
| @ m2.c4: "via" in core must be enclosed by met2 |
| via_CORE NOT met2 |
| } |
| liconOnTap = licon1 AND tap |
| polyonVarChannel = INTERACT poly (poly AND varChannel_drc) |
| taponVarChannel = INTERACT tap (tap AND varChannel_drc) |
| varLength = varChannel_drc NOT COINCIDENT EDGE polyonVarChannel |
| varWidth = varChannel_drc COINCIDENT EDGE polyonVarChannel |
| varLengthError = LENGTH varLength < 0.18 |
| varWidthError = LENGTH varWidth < 1.0 |
| difftapNotVarChannel = difftap NOT taponVarChannel |
| pdiffVaracNwell = (INTERACT nwell (nwell AND varChannel_drc)) AND (INTERACT nwell (nwell AND PDIFF)) |
| "r_829_varac.1" { |
| @ varac.1: Min channel length of varactor channel is 0.180 |
| COPY varLengthError |
| } |
| "r_830_varac.2" { |
| @ varac.2: Min channel width of varactor channel is 1.000 |
| COPY varWidthError |
| } |
| "r_831_varac.3" { |
| @ varac.3: 0.18 min. spacing of varChannel & hvtp |
| EXTERNAL varChannel_drc hvtp < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_832_varac.4" { |
| @ varac.4: 0.25 min. spacing of varChannel & liconOnTap |
| EXTERNAL varChannel_drc liconOnTap < 0.25 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_833_varac.5" { |
| @ varac.5: 0.15 min. enclosure of polyonVarChannel by nwell |
| q0polyonVarChanneland = polyonVarChannel AND nwell |
| ENCLOSURE q0polyonVarChanneland nwell < 0.15 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_834_varac.6" { |
| @ varac.6: 0.27 min. spacing of taponVarChannel & difftapNotVarChannel |
| EXTERNAL taponVarChannel difftapNotVarChannel < 0.27 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_835_varac.7" { |
| @ varac.7: nwell overlapping varacChannel must not overlap p+ diff |
| COPY pdiffVaracNwell |
| } |
| "r_836_varac.8" { |
| @ varac.8: 0.255 min. enclosure of varChannel by hvtp |
| q0varChannel_drcand = varChannel_drc AND hvtp |
| ENCLOSURE q0varChannel_drcand hvtp < 0.255 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| photoDiodeSizeError = NOT LENGTH photoDiode == 3.0 |
| photoDiodeEdgeError = photoDiode NOT COINCIDENT INSIDE EDGE photoID |
| innerDnwellHoles = HOLES dnwell INNER |
| ptapHoles = HOLES PTAP INNER |
| photoDiodeNwell = photoDiode AND nwell |
| photoDbeyondNwell = photoDiode NOT nwell |
| photoEncNwellError = photoDbeyondNwell NOT (INTERNAL photoDbeyondNwell == 1.08 OPPOSITE EXTENDED 1.08 PARALLEL ONLY REGION) |
| photoNwellSizeError = NOT LENGTH photoDiodeNwell == 0.84 |
| photoDiodeTap = photoDiode AND tap |
| photoNwellBeyondTap = photoDiodeNwell NOT tap |
| photoNwellEncTapErr = photoNwellBeyondTap NOT (INTERNAL photoNwellBeyondTap == 0.215 OPPOSITE EXTENDED 0.215 PARALLEL ONLY REGION) |
| photoTapSizeError = NOT LENGTH photoDiodeTap == 0.41 |
| "r_837_photo.2" { |
| @ photo.2: 3.000 min/max width of photoDiode |
| COPY photoDiodeSizeError |
| } |
| "r_838_photo.3" { |
| @ photo.3: 5 min. spacing/notch of photoDiode |
| EXTERNAL photoDiode < 5.0 ABUT < 90 SINGULAR REGION |
| } |
| "r_839_photo.4" { |
| @ photo.4: 5.3 min. spacing of photoDiode & dnwellNotPhoto |
| EXTERNAL photoDiode dnwellNotPhoto < 5.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_840_photo.5" { |
| @ photo.5: edges of photoDiode (dnwell overlapping areaid.po) must be coincident with areaid.po |
| COPY photoDiodeEdgeError |
| } |
| "r_841_photo.6" { |
| @ photo.6: photoDiode must be enclosed by dnwell ring |
| photoDiode NOT innerDnwellHoles |
| } |
| "r_842_photo.7" { |
| @ photo.7: photoDiode must be enclosed by p+tap ring |
| photoDiode NOT ptapHoles |
| } |
| "r_843_photo.8" { |
| @ photo.8: 0.840 min/max width of nwell inside photoDiode |
| COPY photoNwellSizeError |
| } |
| "r_844_photo.9" { |
| @ photo.9: 1.080 min/max enclosure of nwell inside photoDiode by photoDiode |
| COPY photoEncNwellError |
| } |
| "r_845_photo.10" { |
| @ photo.10: 0.410 min/max width of tap inside photoDiode |
| COPY photoTapSizeError |
| } |
| "r_846_photo.11" { |
| @ photo.11: 0.215 min/max enclosure of tap by nwell inside photoDiode |
| COPY photoNwellEncTapErr |
| } |
| ringVIA2 = DONUT via2 |
| rectVIA2 = via2 NOT ringVIA2 |
| rectVIA2MT = rectVIA2 AND moduleCutAREA |
| rectVIA2noMT = rectVIA2 NOT moduleCutAREA |
| rectVIA2Vsmall = RECTANGLE rectVIA2MT == 0.2 BY == 0.2 ORTHOGONAL ONLY |
| rectVIA2Small = RECTANGLE rectVIA2MT == 0.28 BY == 0.28 ORTHOGONAL ONLY |
| rectVIA2Med = RECTANGLE rectVIA2MT == 1.2 BY == 1.2 ORTHOGONAL ONLY |
| rectVIA2Big = RECTANGLE rectVIA2MT == 1.5 BY == 1.5 ORTHOGONAL ONLY |
| rectVIA2Bad = rectVIA2MT NOT (rectVIA2Big OR |
| (rectVIA2Med OR |
| (rectVIA2Small OR rectVIA2Vsmall))) |
| "r_847_via2.1d" { |
| @ via2.1d: via size inside module cut must be 0.200, 0.280, 1.200, OR 1.500 |
| COPY rectVIA2Bad |
| } |
| q0rectVIA2noMT = NOT RECTANGLE rectVIA2noMT ORTHOGONAL ONLY |
| "r_848_via2.1a" { |
| @ via2.1a: rectVIA2noMT should be rectangular |
| COPY q0rectVIA2noMT |
| } |
| q1rectVIA2noMT = INTERNAL rectVIA2noMT < 0.2 REGION |
| "r_849_via2.1a" { |
| @ via2.1a: 0.2 min. width of rectVIA2noMT |
| COPY q1rectVIA2noMT |
| } |
| q2rectVIA2noMT = rectVIA2noMT WITH EDGE (LENGTH rectVIA2noMT > 0.2) |
| "r_850_via2.1a" { |
| @ via2.1a: 0.2 max. length of rectVIA2noMT |
| COPY q2rectVIA2noMT |
| } |
| "r_851_via2.2" { |
| @ via2.2: 0.2 min. spacing/notch of via2 |
| EXTERNAL via2 < 0.2 ABUT < 90 SINGULAR REGION |
| } |
| "r_852_via2.3" { |
| @ via2.3: 0.2 min. width of ring-shaped via2 |
| INTERNAL ringVIA2 < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_853_via2.3" { |
| @ via2.3: 0.205 max. width of ring-shaped via2 |
| q0ringVIA2 = SIZE ringVIA2 BY -0.102 |
| SIZE q0ringVIA2 BY 0.102 |
| } |
| "r_854_via2.3" { |
| @ via2.3: ring-shaped via2 must be enclosed by SEALID |
| ringVIA2 NOT SEALID |
| } |
| "r_855_via2.4" { |
| @ via2.4: 0.04 min. enclosure of via2 by met2 |
| q0via2and = via2 AND met2 |
| ENCLOSURE q0via2and met2 < 0.04 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_856_via2.4" { |
| @ via2.4: via2 must be enclosed by met2 |
| via2 NOT met2 |
| } |
| "r_857_via2.4a" { |
| @ via2.4a: 0.14 min. enclosure of rectVIA2Big by met2 |
| q0rectVIA2Bigand = rectVIA2Big AND met2 |
| ENCLOSURE q0rectVIA2Bigand met2 < 0.14 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_858_via2.4a" { |
| @ via2.4a: rectVIA2Big must be enclosed by met2 |
| rectVIA2Big NOT met2 |
| } |
| "r_859_via2.5" { |
| @ via2.5: 0.085 min. enclosure of adj. sides of via2 by met2 |
| q1met2enc = ENCLOSURE [via2] met2 < 0.085 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q1met2enc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_860_m3.1" { |
| @ m3.1: 0.3 min. width of met3 |
| INTERNAL met3 < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_861_m3.2" { |
| @ m3.2: 0.3 min. spacing/notch of met3 |
| EXTERNAL met3 < 0.3 ABUT < 90 SINGULAR REGION |
| } |
| "r_862_m3.4" { |
| @ m3.4: 0.065 min. enclosure of via2 by met3 |
| q1via2and = via2 AND met3 |
| ENCLOSURE q1via2and met3 < 0.065 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_863_m3.4" { |
| @ m3.4: via2 must be enclosed by met3 |
| via2 NOT met3 |
| } |
| "r_864_m3.6" { |
| @ m3.6: 0.24 min. area of met3 |
| AREA met3 < 0.24 |
| } |
| q0Hugemet3 = WITH WIDTH met3 > 3.0 |
| q1Hugemet3 = SIZE q0Hugemet3 BY 0.4 INSIDE OF met3 STEP 0.4 |
| q2Hugemet3 = q1Hugemet3 NOT q0Hugemet3 |
| q3Hugemet3 = q2Hugemet3 WITH EDGE (q2Hugemet3 COINCIDENT OUTSIDE EDGE q0Hugemet3) |
| q4Hugemet3 = q3Hugemet3 OR q0Hugemet3 |
| q5Hugemet3 = SNAP q4Hugemet3 1 |
| q6Hugemet3 = met3 NOT q5Hugemet3 |
| q7Hugemet3 = EXTERNAL q0Hugemet3 q6Hugemet3 <= 0.395 REGION |
| q8Hugemet3 = q7Hugemet3 NOT (q7Hugemet3 INSIDE met3) |
| q9Hugemet3 = EXTERNAL q5Hugemet3 < 0.4 ABUT < 90 REGION |
| q10Hugemet3 = q9Hugemet3 NOT (INTERACT q9Hugemet3 (q9Hugemet3 AND met3)) |
| "r_865_m3.3d" { |
| @ m3.3d: 0.4 min. spacing between huge met3 and normal met3 |
| COPY q8Hugemet3 |
| } |
| "r_866_m3.3c" { |
| @ m3.3c: 0.4 min. spacing/notch of huge met3+nearby met3 |
| COPY q10Hugemet3 |
| } |
| ringVIA3 = DONUT via3 |
| rectVIA3 = via3 NOT ringVIA3 |
| rectVIA3noMT = rectVIA3 NOT moduleCutAREA |
| rectVIA3MT = rectVIA3 AND moduleCutAREA |
| m4Exempt = met4 NOT (RECTANGLE met4 == 1.42 ASPECT == 1) |
| via3_sz1 = RECTANGLE rectVIA3MT == 0.2 ASPECT == 1 |
| via3_sz2 = RECTANGLE rectVIA3MT == 0.8 ASPECT == 1 |
| via3_1a_err = rectVIA3MT NOT (via3_sz1 OR via3_sz2) |
| q0rectVIA3noMT = NOT RECTANGLE rectVIA3noMT ORTHOGONAL ONLY |
| "r_867_via3.1" { |
| @ via3.1: rectVIA3noMT should be rectangular |
| COPY q0rectVIA3noMT |
| } |
| q1rectVIA3noMT = INTERNAL rectVIA3noMT < 0.2 REGION |
| "r_868_via3.1" { |
| @ via3.1: 0.2 min. width of rectVIA3noMT |
| COPY q1rectVIA3noMT |
| } |
| q2rectVIA3noMT = rectVIA3noMT WITH EDGE (LENGTH rectVIA3noMT > 0.2) |
| "r_869_via3.1" { |
| @ via3.1: 0.2 max. length of rectVIA3noMT |
| COPY q2rectVIA3noMT |
| } |
| "r_870_via3.1a" { |
| @ via3.1a: via size inside module cut must be 0.200 OR 0.800 |
| COPY via3_1a_err |
| } |
| "r_871_via3.2" { |
| @ via3.2: 0.2 min. spacing/notch of via3 |
| EXTERNAL via3 < 0.2 ABUT < 90 SINGULAR REGION |
| } |
| "r_872_via3.3" { |
| @ via3.3: 0.2 min. width of ring-shaped via3 |
| INTERNAL ringVIA3 < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_873_via3.3" { |
| @ via3.3: 0.205 max. width of ring-shaped via3 |
| q0ringVIA3 = SIZE ringVIA3 BY -0.102 |
| SIZE q0ringVIA3 BY 0.102 |
| } |
| "r_874_via3.3" { |
| @ via3.3: ring-shaped via3 must be enclosed by SEALID |
| ringVIA3 NOT SEALID |
| } |
| "r_875_via3.4" { |
| @ via3.4: 0.06 min. enclosure of non-ring via3 by met3 |
| q0rectVIA3and = rectVIA3 AND met3 |
| ENCLOSURE q0rectVIA3and met3 < 0.06 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_876_via3.4" { |
| @ via3.4: non-ring via3 must be enclosed by met3 |
| rectVIA3 NOT met3 |
| } |
| "r_877_via3.5" { |
| @ via3.5: 0.09 min. enclosure of adj. sides of via3 by met3 |
| q0met3enc = ENCLOSURE [via3] met3 < 0.09 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0 |
| NOT RECTANGLE (EXPAND EDGE q0met3enc INSIDE BY 0.005) ORTHOGONAL ONLY |
| } |
| "r_878_m4.1" { |
| @ m4.1: 0.3 min. width of met4 |
| INTERNAL met4 < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_879_m4.2" { |
| @ m4.2: 0.3 min. spacing/notch of met4 |
| EXTERNAL met4 < 0.3 ABUT < 90 SINGULAR REGION |
| } |
| "r_880_m4.3" { |
| @ m4.3: 0.065 min. enclosure of via3 by met4 |
| q0via3and = via3 AND met4 |
| ENCLOSURE q0via3and met4 < 0.065 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_881_m4.3" { |
| @ m4.3: via3 must be enclosed by met4 |
| via3 NOT met4 |
| } |
| "r_882_m4.4a" { |
| @ m4.4a: 0.24 min. area of met4 |
| AREA met4 < 0.24 |
| } |
| q0Hugemet4 = WITH WIDTH met4 > 3.0 |
| q1Hugemet4 = SIZE q0Hugemet4 BY 0.4 INSIDE OF met4 STEP 0.4 |
| q2Hugemet4 = q1Hugemet4 NOT q0Hugemet4 |
| q3Hugemet4 = q2Hugemet4 WITH EDGE (q2Hugemet4 COINCIDENT OUTSIDE EDGE q0Hugemet4) |
| q4Hugemet4 = q3Hugemet4 OR q0Hugemet4 |
| q5Hugemet4 = SNAP q4Hugemet4 1 |
| q6Hugemet4 = met4 NOT q5Hugemet4 |
| q7Hugemet4 = EXTERNAL q0Hugemet4 q6Hugemet4 <= 0.395 REGION |
| q8Hugemet4 = q7Hugemet4 NOT (q7Hugemet4 INSIDE met4) |
| q9Hugemet4 = EXTERNAL q5Hugemet4 < 0.4 ABUT < 90 REGION |
| q10Hugemet4 = q9Hugemet4 NOT (INTERACT q9Hugemet4 (q9Hugemet4 AND met4)) |
| "r_883_m4.5b" { |
| @ m4.5b: 0.4 min. spacing between huge met4 and normal met4 |
| COPY q8Hugemet4 |
| } |
| "r_884_m4.5a" { |
| @ m4.5a: 0.4 min. spacing/notch of huge met4+nearby met4 |
| COPY q10Hugemet4 |
| } |
| ringVIA4 = DONUT via4 |
| rectVIA4 = via4 NOT ringVIA4 |
| m5Exempt = met5 NOT (RECTANGLE met5 == 1.42 ASPECT == 1) |
| q0rectVIA4 = NOT RECTANGLE rectVIA4 ORTHOGONAL ONLY |
| "r_885_via4.1" { |
| @ via4.1: non-ring via4 should be rectangular |
| COPY q0rectVIA4 |
| } |
| q1rectVIA4 = INTERNAL rectVIA4 < 0.8 REGION |
| "r_886_via4.1" { |
| @ via4.1: 0.8 min. width of non-ring via4 |
| COPY q1rectVIA4 |
| } |
| q2rectVIA4 = rectVIA4 WITH EDGE (LENGTH rectVIA4 > 0.8) |
| "r_887_via4.1" { |
| @ via4.1: 0.8 max. length of non-ring via4 |
| COPY q2rectVIA4 |
| } |
| "r_888_via4.2" { |
| @ via4.2: 0.8 min. spacing/notch of via4 |
| EXTERNAL via4 < 0.8 ABUT < 90 SINGULAR REGION |
| } |
| "r_889_via4.3" { |
| @ via4.3: 0.8 min. width of ring-shaped via4 |
| INTERNAL ringVIA4 < 0.8 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_890_via4.3" { |
| @ via4.3: 0.805 max. width of ring-shaped via4 |
| q0ringVIA4 = SIZE ringVIA4 BY -0.402 |
| SIZE q0ringVIA4 BY 0.402 |
| } |
| "r_891_via4.3" { |
| @ via4.3: ring-shaped via4 must be enclosed by SEALID |
| ringVIA4 NOT SEALID |
| } |
| "r_892_via4.4" { |
| @ via4.4: 0.19 min. enclosure of non-ring via4 by met4 |
| q0rectVIA4and = rectVIA4 AND met4 |
| ENCLOSURE q0rectVIA4and met4 < 0.19 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_893_via4.4" { |
| @ via4.4: non-ring via4 must be enclosed by met4 |
| rectVIA4 NOT met4 |
| } |
| "r_894_m5.1" { |
| @ m5.1: 1.6 min. width of met5 |
| INTERNAL met5 < 1.6 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_895_m5.2" { |
| @ m5.2: 1.6 min. spacing/notch of met5 |
| EXTERNAL met5 < 1.6 ABUT < 90 SINGULAR REGION |
| } |
| "r_896_m5.3" { |
| @ m5.3: 0.31 min. enclosure of via4 by met5 |
| q0via4and = via4 AND met5 |
| ENCLOSURE q0via4and met5 < 0.31 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_897_m5.3" { |
| @ m5.3: via4 must be enclosed by met5 |
| via4 NOT met5 |
| } |
| "r_898_m5.4" { |
| @ m5.4: 4 min. area of met5 |
| AREA met5 < 4.0 |
| } |
| "r_899_pad.2" { |
| @ pad.2: 1.27 min. spacing/notch of pad |
| EXTERNAL pad < 1.27 ABUT < 90 SINGULAR REGION |
| } |
| topmet = met5 OR MM5mk |
| HugePDMmkW = WITH WIDTH PDMmk > 100.0 |
| HugePDMmkWsz = SIZE HugePDMmkW BY 0.005 INSIDE OF PDMmk STEP 0.005 |
| HugePDMmkA = HugePDMmkWsz NOT HugePDMmkW |
| HugePDMmkB = HugePDMmkA WITH EDGE (HugePDMmkA COINCIDENT OUTSIDE EDGE HugePDMmkW) |
| HugePDMmkC = HugePDMmkB OR HugePDMmkW |
| HugePDMmkD = SNAP HugePDMmkC 5 |
| padNotMet3 = HugePDMmkD NOT topmet |
| pad3_err = AREA padNotMet3 > 30000.0 |
| "r_900_pad.3" { |
| @ pad.3: hugepad with area less than 30000.0 not allowed |
| COPY pad3_err |
| } |
| deFetPoly = INTERACT poly (poly AND ENID) |
| deFetGate = deFetPoly AND ENID |
| deFetDiff = diff AND ENID |
| deFetNdiff = deFetDiff NOT dnwell |
| deFetPdiff = deFetDiff AND dnwell |
| nonIsolatedTap = tap WITH EDGE (tap COINCIDENT OUTSIDE EDGE diff) |
| isolatedTap = tap NOT nonIsolatedTap |
| deFetTap = isolatedTap AND ENID |
| deNFetGate = INTERACT deFetGate (deFetGate AND deFetNdiff) |
| deNFetSource = INTERACT deFetNdiff (deFetNdiff AND deNFetGate) |
| deNFetSourceAndPoly = deNFetSource AND deFetpoly |
| deNFetSourceNotPoly = deNFetSource NOT deFetpoly |
| deNFetDrain = deFetTap AND nwell |
| nwellOVRdeNFetDrain = INTERACT nwell (nwell AND deNFetDrain) |
| deNFetSourceOverlapNwell = nwell AND deNFetSource |
| deNFetSourceGood = INTERNAL deNFetSourceOverlapNwell == 0.225 REGION |
| deNFetSourceBad = deNFetSourceOverlapNwell NOT deNFetSourceGood |
| denmos_6_1 = (EXPAND EDGE deNFetSource OUTSIDE BY 1.585) AND ENID |
| denmos_6_2 = deNFetSource OR denmos_6_1 |
| denmos_6_good = TOUCH denmos_6_2 deNFetDrain |
| denmos_6_bad_tmp = denmos_6_2 NOT denmos_6_good |
| denmos_6_bad = denmos_6_bad_tmp NOT deNFetSource |
| deNFetChannelEgde = deNFetGate INSIDE EDGE deNFetSource |
| deNFetChannelBadEgde = LENGTH deNFetChannelEgde < 5.0 |
| nwellOverlapEnid = INTERACT nwell (nwell AND deFetGate) |
| nwellRightAngEdg = CONVEX EDGE nwellOverlapEnid ANGLE1 == 90 ANGLE2 > 0 |
| nwellRightAngEdgExp = EXPAND EDGE nwellRightAngEdg OUTSIDE BY 0.005 |
| nwellRightAngEdgExpPoly = INTERACT nwellRightAngEdgExp (nwellRightAngEdgExp AND poly) |
| invalidNwellEdges = TOUCH EDGE nwellOverlapEnid nwellRightAngEdgExpPoly |
| nwellOverENID = INTERACT nwell (nwell AND ENID) |
| "r_901_denmos.1" { |
| @ denmos.1: 1.055 min. width of gate of Drain Extended nFET |
| INTERNAL deNFetGate < 1.055 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_902_denmos.2" { |
| @ denmos.2: 0.28 min. width of deNFetSource not overlapping poly |
| INTERNAL deNFetSourceNotPoly < 0.28 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_903_denmos.3" { |
| @ denmos.3: 0.925 min. width of deNFetSource overlapping poly |
| INTERNAL deNFetSourceAndPoly < 0.925 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_904_denmos.4" { |
| @ denmos.4: 0.17 min. width of drain of Drain Extended nFET |
| INTERNAL deNFetDrain < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_905_denmos.5" { |
| @ denmos.5: min/max extension between de_nFET_source over nwell 0.225 |
| COPY deNFetSourceBad |
| } |
| "r_906_denmos.6" { |
| @ denmos.6: min/max spacing between de_nFET_source and de_nFET_drain 1.585 |
| COPY denmos_6_bad |
| } |
| "r_907_denmos.7" { |
| @ denmos.7: min channel width 5.000 |
| COPY deNFetChannelBadEgde |
| } |
| "r_908_denmos.8" { |
| @ denmos.8: 90 degree angles are not permitted for nwell over poly |
| COPY invalidNwellEdges |
| } |
| "r_909_denmos.10" { |
| @ denmos.10: 0.66 min. enclosure of drain of Drain Extended nFET by nwell |
| q0deNFetDrainand = deNFetDrain AND nwell |
| ENCLOSURE q0deNFetDrainand nwell < 0.66 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_910_denmos.11" { |
| @ denmos.11: 0.86 min. spacing of ptap & nwellOVRdeNFetDrain |
| EXTERNAL PTAP nwellOVRdeNFetDrain < 0.86 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_911_denmos.12" { |
| @ denmos.12: 2.4 min. spacing of nwellOVRdeNFetDrain |
| EXTERNAL nwellOVRdeNFetDrain < 2.4 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE |
| } |
| "r_912_denmos.13" { |
| @ denmos.13: 0.13 min. enclosure of source of Drain Extended nFET by nsdm |
| q0deNFetSourceand = deNFetSource AND nsdm |
| ENCLOSURE q0deNFetSourceand nsdm < 0.13 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_913_denmos.13" { |
| @ denmos.13: source of Drain Extended nFET must be enclosed by nsdm |
| deNFetSource NOT nsdm |
| } |
| //"r_914_denmos.14" { |
| // @ denmos.14: nvhv must be enclosed by moduleCutAREA |
| // nvhv NOT moduleCutAREA |
| // } |
| nwellhole = HOLES nwell |
| dePFetGate = INTERACT deFetGate (deFetGate AND deFetPdiff) |
| dePFetSource = INTERACT deFetPdiff (deFetPdiff AND dePFetGate) |
| dePFetSourceAndPoly = dePFetSource AND deFetpoly |
| dePFETSourceNotPoly = dePFetSource NOT deFetpoly |
| dePFetDrain = deFetTap NOT nwell |
| dePFetSourceExtendNwell = dePFetSource NOT nwell |
| dePFetSourceGood = INTERNAL dePFetSourceExtendNwell == 0.26 REGION |
| dePFETSourceBad = dePFetSourceExtendNwell NOT dePFetSourceGood |
| depmos_6_1 = (EXPAND EDGE dePFetSource OUTSIDE BY 1.19) AND ENID |
| depmos_6_2 = dePFetSource OR depmos_6_1 |
| depmos_6_good = TOUCH depmos_6_2 dePFetDrain |
| depmos_6_bad_tmp = depmos_6_2 NOT depmos_6_good |
| depmos_6_bad = depmos_6_bad_tmp NOT dePFetSource |
| dePFetChannelEgde = dePFetGate INSIDE EDGE dePFetSource |
| dePFetChannelBadEgde = LENGTH dePFetChannelEgde < 5.0 |
| nwellholeOverlapEnid = INTERACT nwellhole (nwellhole AND deFetGate) |
| nwellholeRightAngEdg = CONVEX EDGE nwellholeOverlapEnid ANGLE1 == 90 ANGLE2 > 0 |
| nwellholeRightAngEdgExp = EXPAND EDGE nwellholeRightAngEdg OUTSIDE BY 0.005 |
| nwellholeRightAngEdgExpPoly = INTERACT nwellholeRightAngEdgExp (nwellholeRightAngEdgExp AND poly) |
| invalidNwellholeEdges = TOUCH EDGE nwellholeOverlapEnid nwellholeRightAngEdgExpPoly |
| dePFetDrainNwellhole = nwellhole ENCLOSE dePFetDrain |
| pvhvW5 = EXPAND EDGE (LENGTH (pvhv NOT COINCIDENT EDGE diff) == 5.0) INSIDE BY 0.005 |
| pvhvL0_66 = EXPAND EDGE (LENGTH (pvhv COINCIDENT EDGE diff) == 0.66) INSIDE BY 0.005 |
| pvhvW5L0_66 = INTERACT (INTERACT pvhv pvhvW5) pvhvL0_66 |
| pvhv_depmos13 = pvhv NOT pvhvW5L0_66 |
| "r_915_depmos.1" { |
| @ depmos.1: 1.05 min. width of gate of Drain Extended pFET |
| INTERNAL dePFetGate < 1.05 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_916_depmos.2" { |
| @ depmos.2: 0.28 min. width of dePFetSourceNotpoly |
| INTERNAL dePFetSourceNotpoly < 0.28 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_917_depmos.3" { |
| @ depmos.3: 0.92 min. width of dePFetSource overlapping poly |
| INTERNAL dePFetSourceAndPoly < 0.92 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_918_depmos.4" { |
| @ depmos.4: 0.17 min. width of drain of Drain Extended pFET |
| INTERNAL dePFetDrain < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_919_depmos.5" { |
| @ depmos.5: min/max extension between de_pFET_source beyond nwell 0.260 |
| COPY dePFetSourceBad |
| } |
| "r_920_depmos.6" { |
| @ depmos.6: min/max spacing between de_pFET_source and de_pFET_drain 1.190 |
| COPY depmos_6_bad |
| } |
| "r_921_depmos.7" { |
| @ depmos.7: min channel width 5.000 |
| COPY dePFetChannelBadEgde |
| } |
| "r_922_depmos.8" { |
| @ depmos.8: 90 degree angles are not permitted for nwellhole over poly |
| COPY invalidNwellholeEdges |
| } |
| "r_923_depmos.10" { |
| @ depmos.10: 0.86 min. enclosure of drain of Drain Extended pFET by nwellhole |
| q0dePFetDrainand = dePFetDrain AND nwellhole |
| ENCLOSURE q0dePFetDrainand nwellhole < 0.86 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_924_depmos.11" { |
| @ depmos.11: 0.66 min. spacing of ntap & dePFetDrainNwellhole |
| EXTERNAL NTAP dePFetDrainNwellhole < 0.66 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_925_depmos.12" { |
| @ depmos.12: 0.13 min. enclosure of source of Drain Extended pFET by psdm |
| q0dePFetSourceand = dePFetSource AND psdm |
| ENCLOSURE q0dePFetSourceand psdm < 0.13 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_926_depmos.12" { |
| @ depmos.12: source of Drain Extended pFET must be enclosed by psdm |
| dePFetSource NOT psdm |
| } |
| "r_927_depmos.13" { |
| @ depmos.13: pvhv_depmos13 must be enclosed by moduleCutAREA |
| pvhv_depmos13 NOT moduleCutAREA |
| } |
| difftapInsideEnid = difftap INSIDE ENID |
| difftapEndidEdg = difftapInsideEnid COINCIDENT INSIDE EDGE ENID |
| difftapEndidEdgExp = EXPAND EDGE difftapEndidEdg OUTSIDE BY 0.005 |
| goodHvdifftap = TOUCH difftapInsideEnid difftapEndidEdgExp >= 2 <= 3 |
| badHvdifftap = difftapInsideEnid NOT goodHvdifftap |
| polyGap = deFetGate NOT difftapInsideEnid |
| "r_928_extd.1" { |
| @ extd.1: difftap must not straddle ENID |
| CUT difftap ENID |
| } |
| "r_929_extd.2" { |
| @ extd.2: diff tap must have two or three coincident edges with areaid.en if enclosed by areaid.en |
| COPY badHvdifftap |
| } |
| "r_930_extd.3" { |
| @ extd.3: deFetPoly must overlap polyGap |
| deFetPoly OUTSIDE polyGap |
| } |
| DnwNoRing = dnwell NOT nwellring |
| PwresDnw = pwres AND DnwNoRing |
| PwresNwell = PwresDnw COINCIDENT OUTSIDE EDGE nwell |
| GoodPwresNwell = PwresDnw WITH EDGE PwresNwell == 2 |
| BadPwresNwell = PwresDnw NOT GoodPwresNwell |
| PwresTap = TOUCH EDGE PwresDnw tap |
| GoodPwresTap = PwresDnw WITH EDGE PwresTap == 2 |
| BadPwresTap = PwresDnw NOT GoodPwresTap |
| PwresTerm = tap WITH EDGE (tap COINCIDENT OUTSIDE EDGE GoodPwresTap) |
| GoodPwTap = EXTERNAL PwresTerm nwell == 0.22 ABUT < 90 SINGULAR REGION |
| PwresTermOutEdge = PwresTerm NOT COINCIDENT EDGE PwresDnw |
| BadPwTap = PwresTermOutEdge NOT COINCIDENT EDGE GoodPwTap |
| BadTapW = SIZE (SIZE PwresTerm BY -0.265) BY (0.53 / 2) |
| GoodTapLicon = INTERACT PwresTerm (PwresTerm AND Licon1) == 12 |
| GoodTapMcon = INTERACT PwresTerm (PwresTerm AND Mcon) == 12 |
| BadTapLicon = PwresTerm NOT GoodTapLicon |
| BadTapMcon_tmp = PwresTerm NOT GoodTapMcon |
| BadTapMcon = BadTapMcon_tmp AND met1 |
| nwellEnclosePwres = TOUCH nwell PwresDnw |
| tapRing = (DONUT tap) AND nwellEnclosePwres |
| tapRingLicon = licon1 AND tapRing |
| tapRingLi1 = INTERACT li1 tapRingLicon |
| tapRingMcon = mcon AND tapRingLi1 |
| tapRingMet1 = INTERACT met1 tapRingMcon |
| tapRingMetStrap = INTERACT tapRing tapRingMet1 |
| nonTapwell = nwellEnclosePwres NOT (INTERACT nwell tapRingMetStrap) |
| "r_931_pwres.1" { |
| @ pwres.1: pwres must be enclosed by DnwNoRing |
| pwres NOT DnwNoRing |
| } |
| q0PwresDnw = NOT RECTANGLE PwresDnw ORTHOGONAL ONLY |
| "r_932_pwres.2" { |
| @ pwres.2: PwresDnw should be rectangular |
| COPY q0PwresDnw |
| } |
| q1PwresDnw = INTERNAL PwresDnw < 2.65 REGION |
| "r_933_pwres.2" { |
| @ pwres.2: 2.65 min. width of PwresDnw |
| COPY q1PwresDnw |
| } |
| q2PwresDnw = INTERNAL PwresDnw <= 2.65 REGION |
| q3PwresDnw = PwresDnw NOT q2PwresDnw |
| "r_934_pwres.2" { |
| @ pwres.2: 2.65 max. width of PwresDnw |
| COPY q3PwresDnw |
| } |
| q4PwresDnw = INTERNAL PwresDnw < 26.5 PROJECTING < 26.5 REGION |
| "r_935_pwres.2" { |
| @ pwres.2: 26.5 min. length of PwresDnw |
| COPY q4PwresDnw |
| } |
| q5PwresDnw = PwresDnw WITH EDGE (LENGTH PwresDnw > 265.0) |
| "r_936_pwres.2" { |
| @ pwres.2: 265 max. length of PwresDnw |
| COPY q5PwresDnw |
| } |
| /// pwres.2 is handled by pwres.3 |
| /// pwres.2 is handled by pwres.4 |
| "r_937_pwres.5" { |
| @ pwres.5: pwres Tap to nwell spacing must be 0.220 |
| COPY BadPwTap |
| } |
| "r_938_pwres.6" { |
| @ pwres.6: 0.53 min. width of PwresTerm |
| INTERNAL PwresTerm < 0.53 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_939_pwres.6" { |
| @ pwres.6: Exceeds allowed width of pwell res tap |
| COPY BadTapW |
| } |
| "r_940_pwres.7a" { |
| @ pwres.7a: Tap in pwell must enclose 12 licon1 |
| COPY BadTapLicon |
| } |
| "r_941_pwres.7b" { |
| @ pwres.7b: Tap in pwell must enclose 12 mcon |
| COPY BadTapMcon |
| } |
| "r_942_pwres.8a" { |
| @ pwres.8a: poly must not overlap PwresDnw |
| poly AND PwresDnw |
| } |
| "r_943_pwres.8b" { |
| @ pwres.8b: diff must not overlap PwresDnw |
| diff AND PwresDnw |
| } |
| "r_944_pwres.9" { |
| @ pwres.9: Nwell around pwell res must have strapped tap with metal |
| COPY nonTapwell |
| } |
| "r_945_pwres.11" { |
| @ pwres.11: Pwell res must abut nwell edges on opposite sides |
| COPY BadPwresNwell |
| } |
| "r_946_pwres.10" { |
| @ pwres.10: Pwell res must abut 2 pwres_terminal on opposite sides |
| COPY BadPwresTap |
| } |
| invalid_rfdiode_2 = RFDIODEID NOT COINCIDENT EDGE nwell |
| nwellAndDnwellDRC = dnwell AND nwell |
| nwellDnwellHolesDRC = HOLES nwellAndDnwellDRC INNER |
| inner_nwell_ring_edge = nwellRing COINCIDENT EDGE nwellDnwellHolesDRC |
| invalid_rfdiode_3 = (INTERACT RFDIODEID nwellHoles) NOT COINCIDENT EDGE inner_nwell_ring_edge |
| "r_947_rfdiode.1" { |
| @ rfdiode.1: non-manhattan RFDIODEID edge |
| ANGLE RFDIODEID > 0 < 90 |
| } |
| "r_948_rfdiode.2" { |
| @ rfdiode.2: areaid.re must be coincident with nwell for the rf nwell diode |
| COPY invalid_rfdiode_2 |
| } |
| "r_949_rfdiode.3" { |
| @ rfdiode.3: areaid.re must be coincident with inner nwell ring edge for rf pwell-deep nwell diode |
| COPY invalid_rfdiode_3 |
| } |
| NSM_keepout_DRC = nsm OR NSMmk |
| exempt_NSM3_Cells = (SEALID AND |
| (DONUT diff) |
| ) OR (EXTENT CELL "nikon*") |
| exempt_NSM3a_Cells = (EXTENT CELL "s8Fab_crntic*") OR dieCut |
| "r_950_nsm.1" { |
| @ nsm.1: 3 min. width of nsm |
| INTERNAL nsm < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_951_nsm.2" { |
| @ nsm.2: 4 min. spacing/notch of nsm |
| EXTERNAL nsm < 4.0 ABUT < 90 SINGULAR REGION |
| } |
| diff_not_NSM3_exempt = diff NOT exempt_NSM3_Cells |
| "r_952_nsm.3" { |
| @ nsm.3: 1 min. spacing of diff_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL diff_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_953_nsm.3" { |
| @ nsm.3: diff_not_NSM3_exempt must not overlap nsm OR NSMmk |
| diff_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| tap_not_NSM3_exempt = tap NOT exempt_NSM3_Cells |
| "r_954_nsm.3" { |
| @ nsm.3: 1 min. spacing of tap_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL tap_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_955_nsm.3" { |
| @ nsm.3: tap_not_NSM3_exempt must not overlap nsm OR NSMmk |
| tap_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| fomDummyDRC_not_NSM3_exempt = fomDummyDRC NOT exempt_NSM3_Cells |
| "r_956_nsm.3" { |
| @ nsm.3: 1 min. spacing of fomDummyDRC_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL fomDummyDRC_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_957_nsm.3" { |
| @ nsm.3: fomDummyDRC_not_NSM3_exempt must not overlap nsm OR NSMmk |
| fomDummyDRC_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| FOMmk_not_NSM3_exempt = FOMmk NOT exempt_NSM3_Cells |
| "r_958_nsm.3" { |
| @ nsm.3: 1 min. spacing of FOMmk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL FOMmk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_959_nsm.3" { |
| @ nsm.3: FOMmk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| FOMmk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| poly_not_NSM3_exempt = poly NOT exempt_NSM3_Cells |
| "r_960_nsm.3" { |
| @ nsm.3: 1 min. spacing of poly_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL poly_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_961_nsm.3" { |
| @ nsm.3: poly_not_NSM3_exempt must not overlap nsm OR NSMmk |
| poly_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| P1Mmk_not_NSM3_exempt = P1Mmk NOT exempt_NSM3_Cells |
| "r_962_nsm.3" { |
| @ nsm.3: 1 min. spacing of P1Mmk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL P1Mmk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_963_nsm.3" { |
| @ nsm.3: P1Mmk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| P1Mmk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| li1_not_NSM3_exempt = li1 NOT exempt_NSM3_Cells |
| "r_964_nsm.3" { |
| @ nsm.3: 1 min. spacing of li1_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL li1_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_965_nsm.3" { |
| @ nsm.3: li1_not_NSM3_exempt must not overlap nsm OR NSMmk |
| li1_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| LI1Mmk_not_NSM3_exempt = LI1Mmk NOT exempt_NSM3_Cells |
| "r_966_nsm.3" { |
| @ nsm.3: 1 min. spacing of LI1Mmk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL LI1Mmk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_967_nsm.3" { |
| @ nsm.3: LI1Mmk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| LI1Mmk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| met1_not_NSM3_exempt = met1 NOT exempt_NSM3_Cells |
| "r_968_nsm.3" { |
| @ nsm.3: 1 min. spacing of met1_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL met1_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_969_nsm.3" { |
| @ nsm.3: met1_not_NSM3_exempt must not overlap nsm OR NSMmk |
| met1_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| MM1mk_not_NSM3_exempt = MM1mk NOT exempt_NSM3_Cells |
| "r_970_nsm.3" { |
| @ nsm.3: 1 min. spacing of MM1mk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL MM1mk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_971_nsm.3" { |
| @ nsm.3: MM1mk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| MM1mk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| met2_not_NSM3_exempt = met2 NOT exempt_NSM3_Cells |
| "r_972_nsm.3" { |
| @ nsm.3: 1 min. spacing of met2_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL met2_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_973_nsm.3" { |
| @ nsm.3: met2_not_NSM3_exempt must not overlap nsm OR NSMmk |
| met2_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| MM2Mk_not_NSM3_exempt = MM2Mk NOT exempt_NSM3_Cells |
| "r_974_nsm.3" { |
| @ nsm.3: 1 min. spacing of MM2Mk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL MM2Mk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_975_nsm.3" { |
| @ nsm.3: MM2Mk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| MM2Mk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| met3_not_NSM3_exempt = met3 NOT exempt_NSM3_Cells |
| "r_976_nsm.3" { |
| @ nsm.3: 1 min. spacing of met3_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL met3_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_977_nsm.3" { |
| @ nsm.3: met3_not_NSM3_exempt must not overlap nsm OR NSMmk |
| met3_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| MM3mk_not_NSM3_exempt = MM3mk NOT exempt_NSM3_Cells |
| "r_978_nsm.3" { |
| @ nsm.3: 1 min. spacing of MM3mk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL MM3mk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_979_nsm.3" { |
| @ nsm.3: MM3mk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| MM3mk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| met4_not_NSM3_exempt = met4 NOT exempt_NSM3_Cells |
| "r_980_nsm.3" { |
| @ nsm.3: 1 min. spacing of met4_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL met4_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_981_nsm.3" { |
| @ nsm.3: met4_not_NSM3_exempt must not overlap nsm OR NSMmk |
| met4_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| MM4mk_not_NSM3_exempt = MM4mk NOT exempt_NSM3_Cells |
| "r_982_nsm.3" { |
| @ nsm.3: 1 min. spacing of MM4mk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL MM4mk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_983_nsm.3" { |
| @ nsm.3: MM4mk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| MM4mk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| met5_not_NSM3_exempt = met5 NOT exempt_NSM3_Cells |
| "r_984_nsm.3" { |
| @ nsm.3: 1 min. spacing of met5_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL met5_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_985_nsm.3" { |
| @ nsm.3: met5_not_NSM3_exempt must not overlap nsm OR NSMmk |
| met5_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| MM5mk_not_NSM3_exempt = MM5mk NOT exempt_NSM3_Cells |
| "r_986_nsm.3" { |
| @ nsm.3: 1 min. spacing of MM5mk_not_NSM3_exempt & nsm OR NSMmk |
| EXTERNAL MM5mk_not_NSM3_exempt NSM_keepout_DRC < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_987_nsm.3" { |
| @ nsm.3: MM5mk_not_NSM3_exempt must not overlap nsm OR NSMmk |
| MM5mk_not_NSM3_exempt AND NSM_keepout_DRC |
| } |
| diff_not_NSM3a_exempt = diff NOT exempt_NSM3a_Cells |
| "r_988_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of diff_not_NSM3a_exempt by frameBndr |
| q0diff_not_NSM3a_exemptand = diff_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0diff_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| tap_not_NSM3a_exempt = tap NOT exempt_NSM3a_Cells |
| "r_989_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of tap_not_NSM3a_exempt by frameBndr |
| q0tap_not_NSM3a_exemptand = tap_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0tap_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| fomDummyDRC_not_NSM3a_exempt = fomDummyDRC NOT exempt_NSM3a_Cells |
| "r_990_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of fomDummyDRC_not_NSM3a_exempt by frameBndr |
| q0fomDummyDRC_not_NSM3a_exemptand = fomDummyDRC_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0fomDummyDRC_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| FOMmk_not_NSM3a_exempt = FOMmk NOT exempt_NSM3a_Cells |
| "r_991_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of FOMmk_not_NSM3a_exempt by frameBndr |
| q0FOMmk_not_NSM3a_exemptand = FOMmk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0FOMmk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| poly_not_NSM3a_exempt = poly NOT exempt_NSM3a_Cells |
| "r_992_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of poly_not_NSM3a_exempt by frameBndr |
| q0poly_not_NSM3a_exemptand = poly_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0poly_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| P1Mmk_not_NSM3a_exempt = P1Mmk NOT exempt_NSM3a_Cells |
| "r_993_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of P1Mmk_not_NSM3a_exempt by frameBndr |
| q0P1Mmk_not_NSM3a_exemptand = P1Mmk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0P1Mmk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| li1_not_NSM3a_exempt = li1 NOT exempt_NSM3a_Cells |
| "r_994_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of li1_not_NSM3a_exempt by frameBndr |
| q0li1_not_NSM3a_exemptand = li1_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0li1_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| LI1Mmk_not_NSM3a_exempt = LI1Mmk NOT exempt_NSM3a_Cells |
| "r_995_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of LI1Mmk_not_NSM3a_exempt by frameBndr |
| q0LI1Mmk_not_NSM3a_exemptand = LI1Mmk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0LI1Mmk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| met1_not_NSM3a_exempt = met1 NOT exempt_NSM3a_Cells |
| "r_996_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of met1_not_NSM3a_exempt by frameBndr |
| q0met1_not_NSM3a_exemptand = met1_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0met1_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| MM1mk_not_NSM3a_exempt = MM1mk NOT exempt_NSM3a_Cells |
| "r_997_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of MM1mk_not_NSM3a_exempt by frameBndr |
| q0MM1mk_not_NSM3a_exemptand = MM1mk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0MM1mk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| met2_not_NSM3a_exempt = met2 NOT exempt_NSM3a_Cells |
| "r_998_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of met2_not_NSM3a_exempt by frameBndr |
| q0met2_not_NSM3a_exemptand = met2_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0met2_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| MM2Mk_not_NSM3a_exempt = MM2Mk NOT exempt_NSM3a_Cells |
| "r_999_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of MM2Mk_not_NSM3a_exempt by frameBndr |
| q0MM2Mk_not_NSM3a_exemptand = MM2Mk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0MM2Mk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| met3_not_NSM3a_exempt = met3 NOT exempt_NSM3a_Cells |
| "r_1000_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of met3_not_NSM3a_exempt by frameBndr |
| q0met3_not_NSM3a_exemptand = met3_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0met3_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| MM3mk_not_NSM3a_exempt = MM3mk NOT exempt_NSM3a_Cells |
| "r_1001_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of MM3mk_not_NSM3a_exempt by frameBndr |
| q0MM3mk_not_NSM3a_exemptand = MM3mk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0MM3mk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| met4_not_NSM3a_exempt = met4 NOT exempt_NSM3a_Cells |
| "r_1002_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of met4_not_NSM3a_exempt by frameBndr |
| q0met4_not_NSM3a_exemptand = met4_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0met4_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| MM4mk_not_NSM3a_exempt = MM4mk NOT exempt_NSM3a_Cells |
| "r_1003_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of MM4mk_not_NSM3a_exempt by frameBndr |
| q0MM4mk_not_NSM3a_exemptand = MM4mk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0MM4mk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| met5_not_NSM3a_exempt = met5 NOT exempt_NSM3a_Cells |
| "r_1004_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of met5_not_NSM3a_exempt by frameBndr |
| q0met5_not_NSM3a_exemptand = met5_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0met5_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| MM5mk_not_NSM3a_exempt = MM5mk NOT exempt_NSM3a_Cells |
| "r_1005_nsm.3a" { |
| @ nsm.3a: 3 min. enclosure of MM5mk_not_NSM3a_exempt by frameBndr |
| q0MM5mk_not_NSM3a_exemptand = MM5mk_not_NSM3a_exempt AND frameBndr |
| ENCLOSURE q0MM5mk_not_NSM3a_exemptand frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| diff_not_NSM3b_exempt = diff NOT dieCut |
| "r_1006_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of diff_not_NSM3b_exempt & dieCut |
| EXTERNAL diff_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| tap_not_NSM3b_exempt = tap NOT dieCut |
| "r_1007_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of tap_not_NSM3b_exempt & dieCut |
| EXTERNAL tap_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| fomDummyDRC_not_NSM3b_exempt = fomDummyDRC NOT dieCut |
| "r_1008_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of fomDummyDRC_not_NSM3b_exempt & dieCut |
| EXTERNAL fomDummyDRC_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| FOMmk_not_NSM3b_exempt = FOMmk NOT dieCut |
| "r_1009_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of FOMmk_not_NSM3b_exempt & dieCut |
| EXTERNAL FOMmk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| poly_not_NSM3b_exempt = poly NOT dieCut |
| "r_1010_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of poly_not_NSM3b_exempt & dieCut |
| EXTERNAL poly_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| P1Mmk_not_NSM3b_exempt = P1Mmk NOT dieCut |
| "r_1011_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of P1Mmk_not_NSM3b_exempt & dieCut |
| EXTERNAL P1Mmk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| li1_not_NSM3b_exempt = li1 NOT dieCut |
| "r_1012_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of li1_not_NSM3b_exempt & dieCut |
| EXTERNAL li1_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| LI1Mmk_not_NSM3b_exempt = LI1Mmk NOT dieCut |
| "r_1013_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of LI1Mmk_not_NSM3b_exempt & dieCut |
| EXTERNAL LI1Mmk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met1_not_NSM3b_exempt = met1 NOT dieCut |
| "r_1014_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of met1_not_NSM3b_exempt & dieCut |
| EXTERNAL met1_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| MM1mk_not_NSM3b_exempt = MM1mk NOT dieCut |
| "r_1015_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of MM1mk_not_NSM3b_exempt & dieCut |
| EXTERNAL MM1mk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met2_not_NSM3b_exempt = met2 NOT dieCut |
| "r_1016_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of met2_not_NSM3b_exempt & dieCut |
| EXTERNAL met2_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| MM2Mk_not_NSM3b_exempt = MM2Mk NOT dieCut |
| "r_1017_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of MM2Mk_not_NSM3b_exempt & dieCut |
| EXTERNAL MM2Mk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met3_not_NSM3b_exempt = met3 NOT dieCut |
| "r_1018_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of met3_not_NSM3b_exempt & dieCut |
| EXTERNAL met3_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| MM3mk_not_NSM3b_exempt = MM3mk NOT dieCut |
| "r_1019_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of MM3mk_not_NSM3b_exempt & dieCut |
| EXTERNAL MM3mk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met4_not_NSM3b_exempt = met4 NOT dieCut |
| "r_1020_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of met4_not_NSM3b_exempt & dieCut |
| EXTERNAL met4_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| MM4mk_not_NSM3b_exempt = MM4mk NOT dieCut |
| "r_1021_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of MM4mk_not_NSM3b_exempt & dieCut |
| EXTERNAL MM4mk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met5_not_NSM3b_exempt = met5 NOT dieCut |
| "r_1022_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of met5_not_NSM3b_exempt & dieCut |
| EXTERNAL met5_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| MM5mk_not_NSM3b_exempt = MM5mk NOT dieCut |
| "r_1023_nsm.3b" { |
| @ nsm.3b: 3 min. spacing of MM5mk_not_NSM3b_exempt & dieCut |
| EXTERNAL MM5mk_not_NSM3b_exempt dieCut < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| ncmCore_drc = (ncm AND COREID) NOT exempt_tech_CD |
| ncmOverLapCore = INTERACT ncm (ncm AND COREID) |
| NdiffInNcm = NDIFF INSIDE ncmCore_drc |
| PdiffInNcm = PDIFF INSIDE ncmCore_drc |
| normPDiff = PDIFF_PERI NOT (ESDID OR DIODEID) |
| ncmPeri_drc = ncm NOT ncmCore_drc |
| PdiffNoAreadid = PDIFF_PERI INSIDE (ESDID NOT DIODEID) |
| LVTN_Gate = INTERACT Gate (Gate AND lvtn) |
| lvtnPDiff = (INTERACT diff (diff AND lvtn)) OR LVTN_Gate |
| ncmHoles = HOLES ncm |
| nwellOutCore = NOT TOUCH (nwell OUTSIDE COREID) COREID |
| "r_1024_ncm.X.3" { |
| @ ncm.X.3: ncm_CORE not tech_CD must not overlap "ndiff" in periphery |
| ncmCore_drc AND NDIFF_PERI |
| } |
| "r_1025_ncm.1" { |
| @ ncm.1: 0.38 min. width of ncmPeri |
| INTERNAL ncmPeri_drc < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1026_ncm.2a" { |
| @ ncm.2a: 0.38 min. spacing/notch of ncmPeri |
| EXTERNAL ncmPeri_drc < 0.38 ABUT < 90 SINGULAR REGION |
| } |
| "r_1027_ncm.7" { |
| @ ncm.7: 0.265 min. area of ncm |
| AREA ncm < 0.265 |
| } |
| "r_1028_ncm.8" { |
| @ ncm.8: 0.265 min. area of ncmHoles |
| AREA ncmHoles < 0.265 |
| } |
| "r_1029_ncm.c8" { |
| @ ncm.c8: 0.235 min. enclosure of PDIFF by ncm_CORE not tech_CD |
| q0PdiffInNcmand = PdiffInNcm AND ncmCore_drc |
| ENCLOSURE q0PdiffInNcmand ncmCore_drc < 0.235 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1030_ncm.c9" { |
| @ ncm.c9: 0.235 min. spacing of ncm_CORE not tech_CD & ndiff |
| EXTERNAL ncmCore_drc NDIFF < 0.235 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1031_ncm.c9" { |
| @ ncm.c9: ncm_CORE not tech_CD must not overlap ndiff |
| ncmCore_drc AND NDIFF |
| } |
| "r_1032_ncm.c10" { |
| @ ncm.c10: 0.38 min. spacing of nwellOutCore & ncm_CORE not tech_CD |
| EXTERNAL nwellOutCore ncmCore_drc < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| ldntmCore = ldntm AND COREID |
| ldntmCoreExempt = ldntmCore AND exempt_tech_CD |
| ndiffLdntmEnclose = ENCLOSURE [NDIFF] ldntmCore < 0.18 SINGULAR MEASURE ALL ABUT < 90 |
| nFet = Gate NOT nwell |
| ldntmNotCore = (ldntm NOT ldntmCore) NOT exempt_tech_CD |
| "r_1033_ldntm.c1" { |
| @ ldntm.c1: 0.7 min. width of ldntmCore |
| INTERNAL ldntmCore < 0.7 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1034_ldntm.c2" { |
| @ ldntm.c2: 0.7 min. spacing/notch of ldntmCore |
| EXTERNAL ldntmCore < 0.7 ABUT < 90 SINGULAR REGION |
| } |
| "r_1035_ldntm.c3" { |
| @ ldntm.c3: enclosure of ndiff by ldntm must be more than 0.180 |
| COPY ndiffLdntmEnclose |
| } |
| "r_1036_ldntm.c4" { |
| @ ldntm.c4: 0.125 min. enclosure of nFet by ldntmCore |
| q0nFetand = nFet AND ldntmCore |
| ENCLOSURE q0nFetand ldntmCore < 0.125 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1037_ldntm.c5" { |
| @ ldntm.c5: ldntm not allowed outside areaid.ce |
| COPY ldntmNotCore |
| } |
| "r_1038_ldntm.c6" { |
| @ ldntm.c6: 0.18 min. spacing of ldntmCoreExempt & pdiff |
| EXTERNAL ldntmCoreExempt PDIFF < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| precResistor = poly AND |
| (polyres AND |
| ((rpm OR urpm) AND psdm)) |
| precResistorTerm = (INTERACT poly precResistor) NOT polyres |
| precResistorWidthEdge = precResistor COINCIDENT EDGE poly |
| precResistor_0p35 = INTERNAL precResistorWidthEdge == 0.35 OPPOSITE PARALLEL REGION |
| precResistor_0p69 = INTERNAL precResistorWidthEdge == 0.69 OPPOSITE PARALLEL REGION |
| precResistor_1p41 = INTERNAL precResistorWidthEdge == 1.41 OPPOSITE PARALLEL REGION |
| precResistor_2p85 = INTERNAL precResistorWidthEdge == 2.85 OPPOSITE PARALLEL REGION |
| precResistor_5p73 = INTERNAL precResistorWidthEdge == 5.73 OPPOSITE PARALLEL REGION |
| precResErr = precResistor NOT (INTERACT precResistor (precResistor AND (precResistor_0p35 OR |
| (precResistor_0p69 OR |
| (precResistor_1p41 OR |
| (precResistor_2p85 OR precResistor_5p73)))))) |
| precResTerm_0p35 = precResistorTerm WITH EDGE (precResistorTerm COINCIDENT OUTSIDE EDGE precResistor_0p35) |
| precResTerm_0p69 = precResistorTerm WITH EDGE (precResistorTerm COINCIDENT OUTSIDE EDGE precResistor_0p69) |
| precResTerm_1p41 = precResistorTerm WITH EDGE (precResistorTerm COINCIDENT OUTSIDE EDGE precResistor_1p41) |
| precResTerm_2p85 = precResistorTerm WITH EDGE (precResistorTerm COINCIDENT OUTSIDE EDGE precResistor_2p85) |
| precResTerm_5p73 = precResistorTerm WITH EDGE (precResistorTerm COINCIDENT OUTSIDE EDGE precResistor_5p73) |
| precResCon_0p35 = INTERACT precResTerm_0p35 licon1 != 1 |
| precResCon_0p69 = INTERACT precResTerm_0p69 licon1 != 1 |
| precResCon_1p41 = INTERACT precResTerm_1p41 licon1 != 2 |
| precResCon_2p85 = INTERACT precResTerm_2p85 licon1 != 4 |
| precResCon_5p73 = INTERACT precResTerm_5p73 licon1 != 8 |
| |
| precResistorLengthEdge = precResistor INSIDE EDGE poly |
| precResistor_L0p5 = INTERNAL precResistorLengthEdge < 0.5 OPPOSITE PARALLEL REGION |
| |
| precResNotSupported = INTERACT precResistor (precResistor AND (precResistor_0p35 OR |
| (precResistor_0p69 OR |
| (precResistor_1p41 OR |
| (precResistor_2p85 OR precResistor_5p73))))) |
| "r_1000_rpmNotSupport" { |
| @ prec_res: precision poly resistors with length less than 0.500 um |
| COPY precResistor_L0p5 |
| } |
| rpmExempt = EXTENT CELL "s8usbpdv2_csa_top" "s8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit" "s8usbpdv2_20vconn_sw_300ma_ovp" "s8usbpdv2_20sbu_sw_300ma_ovp" ORIGINAL |
| rpmNotXmt = rpm NOT rpmExempt |
| "r_1039_rpm.1a" { |
| @ rpm.1a: 1.27 min. width of (rpm OR urpm) |
| INTERNAL (rpm OR urpm) < 1.27 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1040_rpm.1b/c/d/e/f" { |
| @ rpm.1b/c/d/e/f: 0.35 or 0.69 or 1.41 or 2.85 or 5.73: allowed width of prec. resistors |
| COPY precResErr |
| } |
| /// rpm.1c is handled by rpm.1b |
| /// rpm.1d is handled by rpm.1b |
| /// rpm.1e is handled by rpm.1b |
| /// rpm.1f is handled by rpm.1b |
| "r_1041_rpm.1g" { |
| @ rpm.1g: Only 1 licon allowed in xhrpoly_0p35 precResistor terminal |
| COPY precResCon_0p35 |
| } |
| "r_1042_rpm.1h" { |
| @ rpm.1h: Only 1 licon allowed in xhrpoly_0p69 precResistor terminal |
| COPY precResCon_0p69 |
| } |
| "r_1043_rpm.1i" { |
| @ rpm.1i: Only 2 licons allowed in xhrpoly_1p41 precResistor terminal |
| COPY precResCon_1p41 |
| } |
| "r_1044_rpm.1j" { |
| @ rpm.1j: Only 4 licons allowed in xhrpoly_2p85 precResistor terminal |
| COPY precResCon_2p85 |
| } |
| "r_1045_rpm.1k" { |
| @ rpm.1k: Only 8 licons allowed in xhrpoly_5p73 precResistor terminal |
| COPY precResCon_5p73 |
| } |
| "r_1046_rpm.2" { |
| @ rpm.2: 0.84 min. spacing/notch of rpm |
| EXTERNAL (rpm OR urpm) < 0.84 ABUT < 90 SINGULAR REGION |
| } |
| "r_1047_rpm.3" { |
| @ rpm.3: 0.2 min. enclosure of precResistor by rpm |
| q0precResistorand = precResistor AND (rpm OR urpm) |
| ENCLOSURE q0precResistorand (rpm OR urpm) < 0.2 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1048_rpm.3" { |
| @ rpm.3: precResistor must be enclosed by rpm |
| precResistor NOT (rpm OR urpm) |
| } |
| "r_1049_rpm.4" { |
| @ rpm.4: 0.11 min. enclosure of precResistor by psdm |
| q1precResistorand = precResistor AND psdm |
| ENCLOSURE q1precResistorand psdm < 0.11 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1050_rpm.4" { |
| @ rpm.4: precResistor must be enclosed by psdm |
| precResistor NOT psdm |
| } |
| "r_1051_rpm.5" { |
| @ rpm.5: 0.095 min. enclosure of precResistor by npc |
| q2precResistorand = precResistor AND npc |
| ENCLOSURE q2precResistorand npc < 0.095 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1052_rpm.5" { |
| @ rpm.5: precResistor must be enclosed by npc |
| precResistor NOT npc |
| } |
| "r_1053_rpm.6" { |
| @ rpm.6: 0.2 min. spacing of rpm & nsdm |
| EXTERNAL (rpm OR urpm) nsdm < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1054_rpm.6" { |
| @ rpm.6: rpm must not overlap nsdm |
| (rpm OR urpm) AND nsdm |
| } |
| "r_1055_rpm.7" { |
| @ rpm.7: 0.2 min. spacing of rpm & poly |
| EXTERNAL (rpm OR urpm) poly < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1056_rpm.8" { |
| @ rpm.8: poly must not straddle rpm |
| CUT poly (rpm OR urpm) |
| } |
| "r_1057_rpm.9" { |
| @ rpm.9: 0.185 min. spacing of precResistor & hvntm |
| EXTERNAL precResistor hvntm < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1058_rpm.9" { |
| @ rpm.9: precResistor must not overlap hvntm |
| precResistor AND hvntm |
| } |
| "r_1059_rpm.10" { |
| @ rpm.10: 2 min. spacing of rpmNotXmt & pwbm |
| EXTERNAL rpmNotXmt pwbm < 2.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1060_rpm.10" { |
| @ rpm.10: rpmNotXmt must not overlap pwbm |
| rpmNotXmt AND pwbm |
| } |
| hvntm_peri = hvntm NOT COREID |
| hvntmNotInHvi = hvntm NOT INSIDE hvi |
| ndiffInHvi = NDIFF AND hvi |
| ndiffInHviPeri = ndiffInHvi NOT (ndiffInHvi AND COREID) |
| ndiffOutsideHvi = NDIFF OUTSIDE hvi |
| PDIFF_notENID = PDIFF NOT ENID |
| PTAPnoButtDiff = PTAP OUTSIDE EDGE NDIFF |
| diffpTapButtEdge_sz = EXPAND EDGE (NDIFF COINCIDENT OUTSIDE EDGE PTAP) OUTSIDE BY 0.005 |
| ESD_nwell_tap_hvi = ESD_nwell_tap INSIDE hvi |
| "r_1061_hvntm.X.1" { |
| @ hvntm.X.1: hvntm must be drawn inside hvi |
| COPY hvntmNotInHvi |
| } |
| "r_1062_hvntm.1" { |
| @ hvntm.1: 0.7 min. width of hvntm_peri |
| INTERNAL hvntm_peri < 0.7 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1063_hvntm.2" { |
| @ hvntm.2: 0.7 min. spacing/notch of hvntm_peri |
| EXTERNAL hvntm_peri < 0.7 ABUT < 90 SINGULAR REGION |
| } |
| "r_1064_hvntm.3" { |
| @ hvntm.3: 0.185 min. enclosure of ndiffInHviPeri by hvntm_peri |
| q0ndiffInHviPeriand = ndiffInHviPeri AND hvntm_peri |
| ENCLOSURE q0ndiffInHviPeriand hvntm_peri < 0.185 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1065_hvntm.4" { |
| @ hvntm.4: 0.185 min. spacing of hvntm_peri & ndiffOutsideHvi |
| EXTERNAL hvntm_peri ndiffOutsideHvi < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1066_hvntm.4" { |
| @ hvntm.4: hvntm_peri must not overlap ndiffOutsideHvi |
| hvntm_peri AND ndiffOutsideHvi |
| } |
| "r_1067_hvntm.5" { |
| @ hvntm.5: 0.185 min. spacing of hvntm_peri & PDIFF_notENID |
| EXTERNAL hvntm_peri PDIFF_notENID < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1068_hvntm.5" { |
| @ hvntm.5: hvntm_peri must not overlap PDIFF_notENID |
| hvntm_peri AND PDIFF_notENID |
| } |
| "r_1069_hvntm.6a" { |
| @ hvntm.6a: 0.185 min. spacing of hvntm_peri & PTAPnoButtDiff |
| EXTERNAL hvntm_peri PTAPnoButtDiff < 0.185 ABUT < 90 REGION EXCLUDE FALSE |
| } |
| "r_1070_hvntm.6a" { |
| @ hvntm.6a: hvntm_peri must not overlap ptap |
| hvntm_peri AND PTAP |
| } |
| "r_1071_hvntm.6b" { |
| @ hvntm.6b: hvntm_peri must not overlap diffpTapButtEdge_sz |
| hvntm_peri AND diffpTapButtEdge_sz |
| } |
| "r_1072_hvntm.7" { |
| @ hvntm.7: 0 min. enclosure of ESD_nwell_tap_hvi by hvntm_peri |
| q0ESD_nwell_tap_hviand = ESD_nwell_tap_hvi AND hvntm_peri |
| ESD_nwell_tap_hvi NOT hvntm_peri |
| } |
| "r_1073_hvntm.7" { |
| @ hvntm.7: ESD_nwell_tap_hvi must be enclosed by hvntm_peri |
| ESD_nwell_tap_hvi NOT hvntm_peri |
| } |
| "r_1074_hvntm.9" { |
| @ hvntm.9: hvntm must not overlap COREID |
| hvntm AND COREID |
| } |
| "r_1075_hvntm.10" { |
| @ hvntm.10: hvntm must overlap hvi |
| hvntm OUTSIDE hvi |
| } |
| q1FOMmk = FOMmk AND SEALID |
| q2FOMmk = DONUT q1FOMmk |
| q3FOMmk = INTERACT SEALID FOMmk != 4 |
| "r_1076_cfom_nikon" { |
| @ cfom_nikon: FOMmk in the nikon cross has the wrong polarity |
| COPY q2FOMmk |
| } |
| "r_1077_cfom_nikon" { |
| @ cfom_nikon: FOMmk is missing from the nikon cross in the layout. |
| COPY q3FOMmk |
| } |
| q1DNMmk = DNMmk AND SEALID |
| q2DNMmk = q1DNMmk NOT (DONUT q1DNMmk) |
| q3DNMmk = INTERACT SEALID DNMmk != 4 |
| "r_1078_cdnm_nikon" { |
| @ cdnm_nikon: DNMmk in the nikon cross has the wrong polarity |
| COPY q2DNMmk |
| } |
| "r_1079_cdnm_nikon" { |
| @ cdnm_nikon: DNMmk is missing from the nikon cross in the layout. |
| COPY q3DNMmk |
| } |
| q1NWMmk = NWMmk AND SEALID |
| q2NWMmk = DONUT q1NWMmk |
| q3NWMmk = INTERACT SEALID NWMmk != 4 |
| "r_1080_cnwm_nikon" { |
| @ cnwm_nikon: NWMmk in the nikon cross has the wrong polarity |
| COPY q2NWMmk |
| } |
| "r_1081_cnwm_nikon" { |
| @ cnwm_nikon: NWMmk is missing from the nikon cross in the layout. |
| COPY q3NWMmk |
| } |
| q1HVTPMmk = HVTPMmk AND SEALID |
| q2HVTPMmk = DONUT q1HVTPMmk |
| q3HVTPMmk = INTERACT SEALID HVTPMmk != 4 |
| "r_1082_chvtpm_nikon" { |
| @ chvtpm_nikon: HVTPMmk in the nikon cross has the wrong polarity |
| COPY q2HVTPMmk |
| } |
| "r_1083_chvtpm_nikon" { |
| @ chvtpm_nikon: HVTPMmk is missing from the nikon cross in the layout. |
| COPY q3HVTPMmk |
| } |
| q1LVTNMmk = LVTNMmk AND SEALID |
| q2LVTNMmk = q1LVTNMmk NOT (DONUT q1LVTNMmk) |
| q3LVTNMmk = INTERACT SEALID LVTNMmk != 4 |
| "r_1084_clvtnm_nikon" { |
| @ clvtnm_nikon: LVTNMmk in the nikon cross has the wrong polarity |
| COPY q2LVTNMmk |
| } |
| "r_1085_clvtnm_nikon" { |
| @ clvtnm_nikon: LVTNMmk is missing from the nikon cross in the layout. |
| COPY q3LVTNMmk |
| } |
| q1LVOMmk = LVOMmk AND SEALID |
| q2LVOMmk = DONUT q1LVOMmk |
| q3LVOMmk = INTERACT SEALID LVOMmk != 4 |
| "r_1086_clvom_nikon" { |
| @ clvom_nikon: LVOMmk in the nikon cross has the wrong polarity |
| COPY q2LVOMmk |
| } |
| "r_1087_clvom_nikon" { |
| @ clvom_nikon: LVOMmk is missing from the nikon cross in the layout. |
| COPY q3LVOMmk |
| } |
| q1P1Mmk = P1Mmk AND SEALID |
| q2P1Mmk = DONUT q1P1Mmk |
| q3P1Mmk = INTERACT SEALID P1Mmk != 4 |
| "r_1088_cp1m_nikon" { |
| @ cp1m_nikon: P1Mmk in the nikon cross has the wrong polarity |
| COPY q2P1Mmk |
| } |
| "r_1089_cp1m_nikon" { |
| @ cp1m_nikon: P1Mmk is missing from the nikon cross in the layout. |
| COPY q3P1Mmk |
| } |
| q1NTMmk = NTMmk AND SEALID |
| q2NTMmk = DONUT q1NTMmk |
| q3NTMmk = INTERACT SEALID NTMmk != 4 |
| "r_1090_cntm_nikon" { |
| @ cntm_nikon: NTMmk in the nikon cross has the wrong polarity |
| COPY q2NTMmk |
| } |
| "r_1091_cntm_nikon" { |
| @ cntm_nikon: NTMmk is missing from the nikon cross in the layout. |
| COPY q3NTMmk |
| } |
| q1HVNTMmk = HVNTMmk AND SEALID |
| q2HVNTMmk = q1HVNTMmk NOT (DONUT q1HVNTMmk) |
| q3HVNTMmk = INTERACT SEALID HVNTMmk != 4 |
| "r_1092_chvntm_nikon" { |
| @ chvntm_nikon: HVNTMmk in the nikon cross has the wrong polarity |
| COPY q2HVNTMmk |
| } |
| "r_1093_chvntm_nikon" { |
| @ chvntm_nikon: HVNTMmk is missing from the nikon cross in the layout. |
| COPY q3HVNTMmk |
| } |
| q1LDNTMmk = LDNTMmk AND SEALID |
| q2LDNTMmk = q1LDNTMmk NOT (DONUT q1LDNTMmk) |
| q3LDNTMmk = INTERACT SEALID LDNTMmk != 4 |
| "r_1094_cldntm_nikon" { |
| @ cldntm_nikon: LDNTMmk in the nikon cross has the wrong polarity |
| COPY q2LDNTMmk |
| } |
| "r_1095_cldntm_nikon" { |
| @ cldntm_nikon: LDNTMmk is missing from the nikon cross in the layout. |
| COPY q3LDNTMmk |
| } |
| q1NPCMmk = NPCMmk AND SEALID |
| q2NPCMmk = q1NPCMmk NOT (DONUT q1NPCMmk) |
| q3NPCMmk = INTERACT SEALID NPCMmk != 4 |
| "r_1096_cnpc_nikon" { |
| @ cnpc_nikon: NPCMmk in the nikon cross has the wrong polarity |
| COPY q2NPCMmk |
| } |
| "r_1097_cnpc_nikon" { |
| @ cnpc_nikon: NPCMmk is missing from the nikon cross in the layout. |
| COPY q3NPCMmk |
| } |
| q1NSDMmk = NSDMmk AND SEALID |
| q2NSDMmk = DONUT q1NSDMmk |
| q3NSDMmk = INTERACT SEALID NSDMmk != 4 |
| "r_1098_cnsdm_nikon" { |
| @ cnsdm_nikon: NSDMmk in the nikon cross has the wrong polarity |
| COPY q2NSDMmk |
| } |
| "r_1099_cnsdm_nikon" { |
| @ cnsdm_nikon: NSDMmk is missing from the nikon cross in the layout. |
| COPY q3NSDMmk |
| } |
| q1PSDMmk = PSDMmk AND SEALID |
| q2PSDMmk = DONUT q1PSDMmk |
| q3PSDMmk = INTERACT SEALID PSDMmk != 4 |
| "r_1100_cpsdm_nikon" { |
| @ cpsdm_nikon: PSDMmk in the nikon cross has the wrong polarity |
| COPY q2PSDMmk |
| } |
| "r_1101_cpsdm_nikon" { |
| @ cpsdm_nikon: PSDMmk is missing from the nikon cross in the layout. |
| COPY q3PSDMmk |
| } |
| q1LICM1mk = LICM1mk AND SEALID |
| q2LICM1mk = DONUT q1LICM1mk |
| q3LICM1mk = INTERACT SEALID LICM1mk != 4 |
| "r_1102_clicm1_nikon" { |
| @ clicm1_nikon: LICM1mk in the nikon cross has the wrong polarity |
| COPY q2LICM1mk |
| } |
| "r_1103_clicm1_nikon" { |
| @ clicm1_nikon: LICM1mk is missing from the nikon cross in the layout. |
| COPY q3LICM1mk |
| } |
| q1LI1Mmk = LI1Mmk AND SEALID |
| q2LI1Mmk = DONUT q1LI1Mmk |
| q3LI1Mmk = INTERACT SEALID LI1Mmk != 4 |
| "r_1104_cli1m_nikon" { |
| @ cli1m_nikon: LI1Mmk in the nikon cross has the wrong polarity |
| COPY q2LI1Mmk |
| } |
| "r_1105_cli1m_nikon" { |
| @ cli1m_nikon: LI1Mmk is missing from the nikon cross in the layout. |
| COPY q3LI1Mmk |
| } |
| q1CTM1mk = CTM1mk AND SEALID |
| q2CTM1mk = DONUT q1CTM1mk |
| q3CTM1mk = INTERACT SEALID CTM1mk != 4 |
| "r_1106_cctm1_nikon" { |
| @ cctm1_nikon: CTM1mk in the nikon cross has the wrong polarity |
| COPY q2CTM1mk |
| } |
| "r_1107_cctm1_nikon" { |
| @ cctm1_nikon: CTM1mk is missing from the nikon cross in the layout. |
| COPY q3CTM1mk |
| } |
| q1MM1mk = MM1mk AND SEALID |
| q2MM1mk = DONUT q1MM1mk |
| q3MM1mk = INTERACT SEALID MM1mk != 4 |
| "r_1108_cmm1_nikon" { |
| @ cmm1_nikon: MM1mk in the nikon cross has the wrong polarity |
| COPY q2MM1mk |
| } |
| "r_1109_cmm1_nikon" { |
| @ cmm1_nikon: MM1mk is missing from the nikon cross in the layout. |
| COPY q3MM1mk |
| } |
| q1VIMmk = VIMmk AND SEALID |
| q2VIMmk = DONUT q1VIMmk |
| q3VIMmk = INTERACT SEALID VIMmk != 4 |
| "r_1110_cviam_nikon" { |
| @ cviam_nikon: VIMmk in the nikon cross has the wrong polarity |
| COPY q2VIMmk |
| } |
| "r_1111_cviam_nikon" { |
| @ cviam_nikon: VIMmk is missing from the nikon cross in the layout. |
| COPY q3VIMmk |
| } |
| q1MM2mk = MM2mk AND SEALID |
| q2MM2mk = DONUT q1MM2mk |
| q3MM2mk = INTERACT SEALID MM2mk != 4 |
| "r_1112_cmm2_nikon" { |
| @ cmm2_nikon: MM2mk in the nikon cross has the wrong polarity |
| COPY q2MM2mk |
| } |
| "r_1113_cmm2_nikon" { |
| @ cmm2_nikon: MM2mk is missing from the nikon cross in the layout. |
| COPY q3MM2mk |
| } |
| q1NSMmk = NSMmk AND SEALID |
| q2NSMmk = DONUT q1NSMmk |
| q3NSMmk = INTERACT SEALID NSMmk != 4 |
| "r_1114_cnsm_nikon" { |
| @ cnsm_nikon: NSMmk in the nikon cross has the wrong polarity |
| COPY q2NSMmk |
| } |
| "r_1115_cnsm_nikon" { |
| @ cnsm_nikon: NSMmk is missing from the nikon cross in the layout. |
| COPY q3NSMmk |
| } |
| q1PDMmk = PDMmk AND SEALID |
| q2PDMmk = q1PDMmk NOT (DONUT q1PDMmk) |
| q3PDMmk = INTERACT SEALID PDMmk != 4 |
| "r_1116_cpdm_nikon" { |
| @ cpdm_nikon: PDMmk in the nikon cross has the wrong polarity |
| COPY q2PDMmk |
| } |
| "r_1117_cpdm_nikon" { |
| @ cpdm_nikon: PDMmk is missing from the nikon cross in the layout. |
| COPY q3PDMmk |
| } |
| q1VIM2mk = VIM2mk AND SEALID |
| q2VIM2mk = DONUT q1VIM2mk |
| q3VIM2mk = INTERACT SEALID VIM2mk != 4 |
| "r_1118_cviam2_nikon" { |
| @ cviam2_nikon: VIM2mk in the nikon cross has the wrong polarity |
| COPY q2VIM2mk |
| } |
| "r_1119_cviam2_nikon" { |
| @ cviam2_nikon: VIM2mk is missing from the nikon cross in the layout. |
| COPY q3VIM2mk |
| } |
| q1MM3mk = MM3mk AND SEALID |
| q2MM3mk = DONUT q1MM3mk |
| q3MM3mk = INTERACT SEALID MM3mk != 4 |
| "r_1120_cmm3_nikon" { |
| @ cmm3_nikon: MM3mk in the nikon cross has the wrong polarity |
| COPY q2MM3mk |
| } |
| "r_1121_cmm3_nikon" { |
| @ cmm3_nikon: MM3mk is missing from the nikon cross in the layout. |
| COPY q3MM3mk |
| } |
| q1VIM3mk = VIM3mk AND SEALID |
| q2VIM3mk = DONUT q1VIM3mk |
| q3VIM3mk = INTERACT SEALID VIM3mk != 4 |
| "r_1122_cviam3_nikon" { |
| @ cviam3_nikon: VIM3mk in the nikon cross has the wrong polarity |
| COPY q2VIM3mk |
| } |
| "r_1123_cviam3_nikon" { |
| @ cviam3_nikon: VIM3mk is missing from the nikon cross in the layout. |
| COPY q3VIM3mk |
| } |
| q1MM4mk = MM4mk AND SEALID |
| q2MM4mk = DONUT q1MM4mk |
| q3MM4mk = INTERACT SEALID MM4mk != 4 |
| "r_1124_cmm4_nikon" { |
| @ cmm4_nikon: MM4mk in the nikon cross has the wrong polarity |
| COPY q2MM4mk |
| } |
| "r_1125_cmm4_nikon" { |
| @ cmm4_nikon: MM4mk is missing from the nikon cross in the layout. |
| COPY q3MM4mk |
| } |
| q1VIM4mk = VIM4mk AND SEALID |
| q2VIM4mk = DONUT q1VIM4mk |
| q3VIM4mk = INTERACT SEALID VIM4mk != 4 |
| "r_1126_cviam4_nikon" { |
| @ cviam4_nikon: VIM4mk in the nikon cross has the wrong polarity |
| COPY q2VIM4mk |
| } |
| "r_1127_cviam4_nikon" { |
| @ cviam4_nikon: VIM4mk is missing from the nikon cross in the layout. |
| COPY q3VIM4mk |
| } |
| q1MM5mk = MM5mk AND SEALID |
| q2MM5mk = DONUT q1MM5mk |
| q3MM5mk = INTERACT SEALID MM5mk != 4 |
| "r_1128_cmm5_nikon" { |
| @ cmm5_nikon: MM5mk in the nikon cross has the wrong polarity |
| COPY q2MM5mk |
| } |
| "r_1129_cmm5_nikon" { |
| @ cmm5_nikon: MM5mk is missing from the nikon cross in the layout. |
| COPY q3MM5mk |
| } |
| q1RPMmk = RPMmk AND SEALID |
| q2RPMmk = DONUT q1RPMmk |
| q3RPMmk = INTERACT SEALID RPMmk != 4 |
| "r_1130_crpm_nikon" { |
| @ crpm_nikon: RPMmk in the nikon cross has the wrong polarity |
| COPY q2RPMmk |
| } |
| "r_1131_crpm_nikon" { |
| @ crpm_nikon: RPMmk is missing from the nikon cross in the layout. |
| COPY q3RPMmk |
| } |
| validCoreID9 = INSIDE CELL COREID s8cell_ee_bseln s8cell_ee_cellcorn_n s8cell_ee_termcella s8cell_ee_bselp s8cell_ee_cellcorn_p s8cell_ee_termcella_int s8cell_ee_cell s8cell_ee_colend_lasta s8cell_ee_termcellb s8cell_ee_cell_int s8cell_ee_colend_lastb s8cell_ee_termcellb_int s8cell_ee_cell_last s8cell_ee_colenda s8cell_mcell4_last_int s8cell_ee_cell_last_int s8cell_ee_colendb s8sram_colenda s8sram_precharge_ce_3x s8sram_colend_cent s8sram_horstrap_opt1_blx_ce s8sram_rowend_hstrap_ce s8sram_colend s8sram_cell s8sram_hor_wlstrap_ce s8sram_cornera s8sram_precharge s8sram_precharge_ce s8sram_precharge_end_2x s8sram_corner s8sram_precharge_end s8sram_precharge_end_3x s8sram_wlstrap_ce s8sram_colenda_cent s8sram_precharge_2x s8sram_rowend_ce s8sram_horstrap_opt1_ce s8sram_precharge_3x s8sram_precharge_ce_2x s8sram_precharge_ce_via1 s8sram_precharge_ce_2x_via1 s8sram_precharge_ce_3x_via1 s8sram_precharge_end_via1 s8sram_precharge_end_2x_via1 s8sram_precharge_end_3x_via1 s8cell_col_precharge s8cell_sp_colend_opt1_ce s8cell_sp_horstrap_opt1_ce s8cell_col_precharge_ce s8cell_sp_colend_opt1a_ce s8cell_sp_horstrap_opt3_ce s8cell_col_precharge_end s8cell_sp_colend1_ce s8cell_sp_rowend_ce s8cell_sp_cell s8cell_sp_corner_ce s8cell_sp_rowend_hstrap_ce s8cell_sp_colend_ce s8cell_sp_hor_wlstrap_ce s8cell_sp_wlstrap_ce s8cell_sp_colend_cent_ce s8cell_sp_horstrap_opt1_blx_ce s8cell_tc_tech_CD_top s8cell_tc_tech_CD_lcross s8cell_tc_tech_CD_top_pcell s8nvlatch_cell1ux s8nvlatch_lvD s8nvlatch_s8cell_ee_cell s8nvlatch_cell s8nvlatch_lvC s8nvlatch_cellg s8nvlatch_cells s8nvlatch_s8cell_ee_cell_back s8cell_nvlfp_cell s8sram16x16_wlstrap_p_ce s8sram16x16_colend s8sram16x16_ctl_load_unit s8sram16x16_colend_p_cent s8sram16x16_colenda s8sram16x16_wlstrapa2x s8sram16x16_cornerb s8sram16x16_rowend_ce s8sram16x16_wlstrap2x s8sram16x16_cornera s8sram16x16_colenda_p_cent s8sram16x16_corner s8sram16x16_ctl_load s8cell_ee_colend_last s8cell_ee_colend s8cell_ee_cell s8cell_ee_corner_east s8cell_ee_cell_opt0 s8cell_ee_colend_lastb_opt0 s8cell_ee_cell_last s8cell_ee_termcellb_ref s8cell_ee_colendb s8cell_ee_cellcorn_p_ref_opt0 s8cell_ee_termcella_ref s8cell_ee_colenda s8cell_ee_colenda_opt0 s8cell_ee_rowend_west s8cell_ee_corner_east_opt0 s8cell_ee_rowend_east_opt0 s8cell_ee_cellcorn_n_ref_opt0 s8cell_ee_corner_west_opt0 s8cell_ee_colend_lasta_opt0 s8cell_ee_cell_last_opt0 s8cell_ee_cellcorn_p_ref s8cell_ee_rowend_west_opt0 s8cell_ee_termcellb_ref_opt0 s8cell_ee_corner_west s8cell_ee_colend_opt0 s8cell_ee_rowend_east s8cell_ee_cellcorn_n_ref s8cell_ee_colend_lastb s8cell_ee_termcella_ref_opt0 s8cell_ee_colenda_d s8cell_ee_colend_lasta s8cell_ee_colendb_opt0 s8cell_ee_colend_lasta_d s8cell_ee_bseln_enda_d s8cell_ee_bseln_enda_poly_d s8cell_ee_bselp_enda_d s8cell_ee_plus_1t_cell s8cell_ee_plus_rowtie_ref s8cell_ee_plus_sselptie_ref s8cell_ee_plus_sselp_ref s8cell_ee_plus_sselntie_ref s8cell_ee_plus_sseln_a s8cell_ee_plus_sseln_b s8cell_ee_plus_coltie_ref s8cell_ee_plus_corner_tie s8cell_ee_plus_sselp_a s8cell_ee_plus_sselp_b sr_blld sr_mcell_tie up_rom_tie sr_bltd_eq sr_tcell up_rom1 sr_mcell sr_tcell_tie up_romref sr_mcell_tie_L sr_mcell_tie_R sr_tcell_tie_L sr_tcell_tie_R s8tnvcell_mcell_tie_END_b_cell7 s8tnvcell_mcell_tie_END_t_cell7 s8tnvcell_tcell_END_t_cell7 s8tnvcell_tcell_END_b_cell7 s8tnvcell_mcell_tie_END_sub_t_cell7 s8tnvcell_mcell_tie_END_sub_b_cell7 s8tnvcell_tcell_tie_Rt_cell7 s8tnvcell_tcell_tie_Rb_cell7 s8tnvcell_mcell_tie_Rt_cell7 s8tnvcell_mcell_tie_Rb_cell7 s8tnvcell_mcell_Mt_cell7 s8tnvcell_mcell_Mb_cell7 s8tnvcell_mcell_t_cell7 s8tnvcell_mcell_b_cell7 s8tnvcell_tcell_t_cell7 s8tnvcell_tcell_b_cell7 s8tnvcell_mcell_tie_Lt_cell7 s8tnvcell_mcell_tie_Lb_cell7 s8tnvcell_tcell_tie_Lb_cell7 s8tnvcell_tcell_tie_Lt_cell7 s8tnvcell_tcell_tie_t_cell7 s8tnvcell_tcell_tie_b_cell7 s8tnvcell_mcell_tie_t_cell7 s8tnvcell_mcell_tie_b_cell7 s8tnvssr_bltd_eq s8tnvssr_bltd_tie s8tnvssr_blld_tie s8tnvssr_blld s8ovation_atc2_pd_12_6_BiCell |
| validCoreID1 = INSIDE CELL COREID ram8_buildspace s8diaet_md3235_a s8diaet_md7301_a s8diaet_md7302_a s8diaet_md7303_a s8diaet_md7304_a s8diaet_md7321_a s8diaet_md7322_a s8diaet_md7333_a s8diaet_md7334_a s8diaet_s7333_hvpmos_cap_a s8Fab_etch_a s8Fab_etch_b s8Fab_etch_c s8Fab_etch_d s8Fab_etch_e s8Fab_etch_f s8Fab_fab_fomc s8Fab_fab_li1mc s8Fab_fab_pimc s8Fab_fabCD_b s8Fab_fabCD_c s8Fab_fabCD_d s8Fab_fabCD_e s8Fab_plot_etch_a s8Fab_sem_CDcross s8Fab_tech_CD_drawn_a s8te2et_2t_cell_end01 s8te2et_2t_cell_end01_NoVia s8te2et_2t_cell_end01_sonos_Diff s8te2et_2t_cell_end01_sonos_Diff_b s8te2et_2t_cell_end01_sonos_Diff_R s8te2et_2t_cell_end02_opt1_L s8te2et_2t_cell_end02_opt1_L_b s8te2et_2t_cell_end02_opt1_R s8te2et_2t_cell_end02_opt1_R01 s8te2et_2t_cell_end02_opt2_L s8te2et_2t_cell_end02_opt2_L_b s8te2et_2t_cell_end02_opt2_L_c s8te2et_2t_cell_end02_opt2_R s8te2et_2t_cell_end02_opt2_R01 s8te2et_2t_cell_end02_opt3_L s8te2et_2t_cell_end02_opt3_L_b s8te2et_2t_cell_end02_opt3_L_c s8te2et_2t_cell_end02_opt3_R s8te2et_2t_cell_end02_opt3_R01 s8te2et_2t_cell_end02_opt4_L s8te2et_2t_cell_end02_opt4_L_c s8te2et_2t_cell_end02_opt4_R s8te2et_2t_cell_end02_opt4_R01 s8te2et_2t_cell_end02_sonos_Diff s8te2et_2t_cell_end02_sonos_Diff_b s8te2et_2t_cell_end02_sonos_Diff_L s8te2et_2t_cell_end02_sonos_Diff_L_b s8te2et_2t_cell_end02_sonos_Diff_R s8te2et_2t_cell_option1_swap s8te2et_2t_cell_option1_swap_b s8te2et_2t_cell_option1_swap_ncBot s8te2et_2t_cell_option1_swap_ncBot_b s8te2et_2t_cell_option1_swap_ncTop s8te2et_2t_cell_option1_swap_ncTop_b s8te2et_2t_cell_option2_swap s8te2et_2t_cell_option2_swap_b s8te2et_2t_cell_option2_swap_ncBot s8te2et_2t_cell_option2_swap_ncBot_b s8te2et_2t_cell_option2_swap_ncTop s8te2et_2t_cell_option2_swap_ncTop_b s8te2et_2t_cell_option3_swap s8te2et_2t_cell_option3_swap_b s8te2et_2t_cell_option3_swap_c s8te2et_2t_cell_option3_swap_ncTop s8te2et_2t_cell_option3_swap_ncTop_b s8te2et_2t_cell_option3_swap_ncTop_c s8te2et_2t_cell_option3_swap1_ncBot s8te2et_2t_cell_option3_swap1_ncBot_b s8te2et_2t_cell_option3_swap1_ncBot_c s8te2et_2t_cell_option4_swap s8te2et_2t_cell_option4_swap_c s8te2et_2t_cell_option4_swap_ncBot s8te2et_2t_cell_option4_swap_ncBot_c s8te2et_2t_cell_option4_swap_ncTop s8te2et_2t_cell_option4_swap_ncTop_c s8te2et_2t_cell_sonos_Diff_swap s8te2et_2t_cell_sonos_Diff_swap_b s8te2et_2t_cell_sonos_Diff_swap_ncTop s8te2et_2t_cell_sonos_Diff_swap_ncTop_b s8te2et_2t_cell_sonos_Diff_swap1_ncBot s8te2et_2t_cell_sonos_Diff_swap1_ncBot_b s8te2et_2t_cell_sonos_Diff_swapR s8te2et_2t_cell_sonos_Diff_swapR_b s8te2et_2t_cellcrnr_L s8te2et_2t_cellcrnr_R s8te2et_md1005_a s8te2et_md1092_a s8te2et_md1701_a |
| validCoreID2 = INSIDE CELL COREID s8te2et_md1702_a s8te2et_md1702_b s8te2et_md1703_a s8te2et_md1705_a s8te2et_md1773_a s8te2et_md3235_a s8te2et_md3242_b s8te2et_md3244_b s8te2et_md3248_d s8te2et_md3251_b s8te2et_md3277_b s8te2et_md3288_b s8te2et_md3288_c s8te2et_md7301_a s8te2et_md7302_a s8te2et_md7303_a s8te2et_md7304_a s8te2et_md8111_a s8te2et_md8113_a s8te2et_PassGate_sonos_Fet_novia s8te2et_s_hv_depmos_dieler_opt1 s8te2et_s_hv_depmos_dieler_opt2 s8te2et_s_hv_depmos_dieler_opt3 s8te2et_s0755_rowend_1 s8te2et_s0790_cell_1 s8te2et_s0790_cell_2 s8te2et_s0790_colend_1 s8te2et_s0791_cell_1 s8te2et_s0791_colend_1 s8te2et_s0791_rowend_1 s8te2et_s1700_hier0_basecell_a s8te2et_s1700_hier0_basecell_b s8te2et_s1700_hier0_bot_basecell_a s8te2et_s1700_hier0_corner_a s8te2et_s1700_hier0_elem_a s8te2et_s1700_hier0_elem_b s8te2et_s1700_hier0_left_a s8te2et_s1700_hier0_rcorner_a s8te2et_s1700_hier0_right_a s8te2et_s1700_hier0_top_basecell_a s8te2et_s1701_hier0_base_cell_a s8te2et_s1701_hier0_bot_con_a s8te2et_s1701_hier0_corner_a s8te2et_s1701_hier0_lft_con_a s8te2et_s1701_hier0_rht_con_a s8te2et_s1701_hier0_top_con_a s8te2et_s1702_hier0_base_cell_a s8te2et_s1702_hier0_base_cell_b s8te2et_s1702_hier0_bot_a s8te2et_s1702_hier0_corner_l_a s8te2et_s1702_hier0_corner_r_a s8te2et_s1702_hier0_left_a s8te2et_s1702_hier0_right_a s8te2et_s1702_hier0_top_a s8te2et_s1703_hier0_base_cell_a s8te2et_s1703_hier0_bot_con_a s8te2et_s1703_hier0_corner_a s8te2et_s1703_hier0_lft_con_a s8te2et_s1703_hier0_rht_con_a s8te2et_s1703_hier0_top_con_a s8te2et_s1705_hier0_base_cell_a s8te2et_s1709_hier0_base_cell_a s8te2et_s1709_hier0_lft_con_a s8te2et_s1709_hier0_rht_con_a s8te2et_s1709_hier0_top_con_a s8te2et_s1726_hier0_base_cell_a s8te2et_s1726_hier0_base_cell_b s8te2et_s1726_hier0_lft_con_a s8te2et_s1726_hier0_rht_con_b s8te2et_s1726_hier1_array_b s8te2et_s1726_hier1_array_c s8te2et_s1726_hier1_array_d s8te2et_s1726_hier2_array_a s8te2et_s1743_hier0_base_cell_a s8te2et_s1743_hier0_sl_a s8te2et_s1743_hier0_sr_a s8te2et_s1743_hier1_array_a s8te2et_s1743_hier1_array_b s8te2et_s1744_hstrap_term_a s8te2et_s1744_hstrap_term_n_a s8te2et_s1744_hstrap2_a s8te2et_s1744_npass_a s8te2et_s1744_npass_b s8te2et_s1744_npass_cent_a s8te2et_s1744_npass_horiz_term_cent_a s8te2et_s1744_npass_vert_a s8te2et_s1744_npd_a s8te2et_s1744_npd_b s8te2et_s1744_npd_cent_a s8te2et_s1744_npd_horiz_a s8te2et_s1744_npd_horiz_term_a s8te2et_s1744_npd_horiz_term_cent_a s8te2et_s1744_npd_horiz_term_wl_a s8te2et_s1744_npd_vert_a s8te2et_s1744_npd_vert_term_cent_a |
| validCoreID3 = INSIDE CELL COREID s8te2et_s1744_ppu_a s8te2et_s1744_ppu_b s8te2et_s1744_ppu_cent_c s8te2et_s1744_ppu_corn_a s8te2et_s1744_ppu_cornu_a s8te2et_s1744_ppu_vert_a s8te2et_s1744_ppu_vert_hstrap2_a s8te2et_s1744_ppu_vert_term_a s8te2et_s1744_ppu_vert_term_cent_a s8te2et_s1744_topbot_hstrap2_a s8te2et_s1756_hier0_base_cell_1_a s8te2et_s1756_hier0_base_cell_1_b s8te2et_s1756_hier0_base_cell_2_a s8te2et_s1756_hier0_bot_con_1_a s8te2et_s1756_hier0_bot_con_2_a s8te2et_s1756_hier0_top_con_1_a s8te2et_s1756_hier0_top_con_2_a s8te2et_s1756_hier1_array_2_a s8te2et_s1756_npass_bot_term_a s8te2et_s1756_npass_top_term_a s8te2et_s1756_npd_4x2_a s8te2et_s1756_npd_4x2_b s8te2et_s1756_npd_a s8te2et_s1756_npd_b s8te2et_s1756_npd_bot_term_a s8te2et_s1756_npd_top_term_a s8te2et_s1758_ppu_4x2_a s8te2et_s1758_ppu_4x2_c s8te2et_s1758_ppu_a s8te2et_s1758_ppu_bot_term_a s8te2et_s1758_ppu_c s8te2et_s1758_ppu_top_term_a s8te2et_s1760_hier1_array_a s8te2et_s1760_hier1_array_b s8te2et_s1761_hier1_array_a s8te2et_s1762_hier0_cell_1 s8te2et_s1762_hier0_colend_a s8te2et_s1762_hier0_rowend_2_a s8te2et_s1762_hier1_array_b s8te2et_s1773_hier0_base_cell_a s8te2et_s2t_cell_end02 s8te2et_s2t_cell_end02_NoVia s8te2et_s2t_cell_end03 s8te2et_s2t_cell_end03_NoVia s8te2et_s2t_cellcrnr_01_L s8te2et_s2t_cellcrnr_01_R s8te2et_s3243_sonos_0p42_0p18 s8te2et_s3243_sonos_0p42_0p18_c s8te2et_s3243_sonos_0p42_0p22 s8te2et_s3243_sonos_0p42_0p22_c s8te2et_s3243_sonos_0p42_0p26 s8te2et_s3243_sonos_0p42_0p26_c s8te2et_s3243_sonos_25_0p22 s8te2et_s3243_sonos_25_0p22_c s8te2et_s3243_sonos_25_25 s8te2et_s3243_sonos_25_25_c s8te2et_s3248_sonos_2p0_2p0 s8te2et_s3248_sonos_2p0_2p0_d s8te2et_s3255_MiniArray_b s8te2et_s3259_2t_cell_end02_opt2_L s8te2et_s3259_2t_cellcrnr_L s8te2et_s3262_2t_cell_a s8te2et_s3262_2t_cell_end02_L s8te2et_s3262_2t_cell_end02_R s8te2et_s3262_2t_cell_end02_R01 s8te2et_s3262_2t_cell_ncBot s8te2et_s3262_2t_cell_ncTop s8te2et_s3263_2t_cell_a s8te2et_s3263_2t_cell_end02_L s8te2et_s3263_2t_cell_end02_R s8te2et_s3263_2t_cell_end02_R01 s8te2et_s3263_2t_cell_ncBot s8te2et_s3263_2t_cell_ncTop s8te2et_s3264_2t_2x2_b s8te2et_s3264_2t_2x2_NoVia_b s8te2et_s3264_2t_cell_a s8te2et_s3264_2t_cell_c s8te2et_s3264_2t_cell_end02_L s8te2et_s3264_2t_cell_end02_L_b s8te2et_s3264_2t_cell_end02_L_c s8te2et_s3264_2t_cell_end02_R s8te2et_s3264_2t_cell_end02_R01 s8te2et_s3264_2t_cell_ncBot s8te2et_s3264_2t_cell_ncBot_c s8te2et_s3264_2t_cell_ncTop s8te2et_s3264_2t_cell_ncTop_c s8te2et_s3265_2t_cell_a s8te2et_s3265_2t_cell_b s8te2et_s3265_2t_cell_end01 s8te2et_s3265_2t_cell_end01_NoVia s8te2et_s3265_2t_cell_end02_L s8te2et_s3265_2t_cell_end02_L_b s8te2et_s3265_2t_cell_end02_R s8te2et_s3265_2t_cell_end02_R01 s8te2et_s3265_2t_cell_ncBot |
| validCoreID4 = INSIDE CELL COREID s8te2et_s3265_2t_cell_ncBot_b s8te2et_s3265_2t_cell_ncTop s8te2et_s3265_2t_cell_ncTop_b s8te2et_s3266_2t_cell_a s8te2et_s3266_2t_cell_b s8te2et_s3266_2t_cell_end02_L s8te2et_s3266_2t_cell_end02_L_b s8te2et_s3266_2t_cell_end02_R s8te2et_s3266_2t_cell_end02_R01 s8te2et_s3266_2t_cell_ncBot s8te2et_s3266_2t_cell_ncBot_b s8te2et_s3266_2t_cell_ncTop s8te2et_s3266_2t_cell_ncTop_b s8te2et_s3267_2t_2x2_a s8te2et_s3267_2t_2x2_b s8te2et_s3267_2t_2x2_c s8te2et_s3267_PassGate_sonos_2x2 s8te2et_s3267_PassGate_sonos_2x2_b s8te2et_s3267_PassGate_sonos_2x2_novia s8te2et_s3267_PassGate_sonos_2x2_novia_b s8te2et_s3267_PassGate_sonos_2x2_novia_c s8te2et_s3268_sonos_Fet_novia s8te2et_s3268_sonos_Fet_novia_b s8te2et_s3268_sonos_Fet_novia_c s8te2et_s3268_Sonos_soFet_2x2 s8te2et_s3268_Sonos_soFet_2x2_c s8te2et_s3269_2t_2x2_a s8te2et_s3269_2t_2x2_b s8te2et_s3269_2t_2x2_c s8te2et_s3269_PassGate_sonos_2x2 s8te2et_s3269_PassGate_sonos_2x2_b s8te2et_s3269_PassGate_sonos_2x2_c s8te2et_s3270_2t_2x2_opt3 s8te2et_s3270_2t_2x2_opt3_b s8te2et_s3270_2t_2x2_opt3_c s8te2et_s3270_2x2_NoVia s8te2et_s3270_2x2_NoVia_b s8te2et_s3270_2x2_NoVia_c s8te2et_s3270_Sonos_soFet_2x2 s8te2et_s3270_Sonos_soFet_2x2_b s8te2et_s3270_Sonos_soFet_2x2_c s8te2et_s3271_32x32_Array s8te2et_s3272_2t_2x2_a s8te2et_s3272_2t_2x2_NoVia s8te2et_s3272_2t_cell_end02_L s8te2et_s3272_2t_cell_end02_R s8te2et_s3272_32x32_Array s8te2et_s3273_2t_end02_L s8te2et_s3273_2t_end02_L_b s8te2et_s3273_2t_end02_R s8te2et_s3274_2x2_NoVia s8te2et_s3274_2x2_NoVia_b s8te2et_s3274_32x32_Array s8te2et_s3274_32x32_Array_b s8te2et_s3275_2t_cell s8te2et_s3275_2t_cell_a s8te2et_s3275_2t_cell_b s8te2et_s3275_2t_cell_end01 s8te2et_s3275_2t_cell_end01_NoVia s8te2et_s3275_2t_cell_ncBot s8te2et_s3275_2t_cell_ncTop s8te2et_s3275_2x2_NoVia s8te2et_s3275_2x2_NoVia_b s8te2et_s3275_32x32_Array s8te2et_s3275_32x32_Array_b s8te2et_s3275_cell s8te2et_s3275_cell_end01 s8te2et_s3275_cell_end01_NoVia s8te2et_s3276_W2_L2 s8te2et_s3277_W2_L2 s8te2et_s3278_clock_latch s8te2et_s3279_8T_latch s8te2et_s3280_6T_latch s8te2et_s3280_6T_latch_b s8te2et_s3282_2T_Spl_cell2x2 s8te2et_s3282_2T_Spl_cell2x2_b s8te2et_s3282_2T_Spl_cell2x2_nc s8te2et_s3282_2T_Spl_cell2x2_nosrc s8te2et_s3282_cellend s8te2et_s3282_cellend_cntr s8te2et_s3282_celltop s8te2et_s3282_celltop_nc s8te2et_s3283_3T_Dual_cell2x2_nc s8te2et_s3283_3T_Dual_cell2x2_nc_b s8te2et_s3283_3T_Dual_cell2x2_nosrc s8te2et_s3283_3T_Spl_Chanel_cell s8te2et_s3283_cellend s8te2et_s3283_cellend_cntr s8te2et_s3284_1T_SSL_cell2x2 s8te2et_s3284_1T_SSL_cell2x2_nc s8te2et_s3284_1T_SSL_cell2x2_nosrc s8te2et_s3284_cellend s8te2et_s3284_cellend_cntr s8te2et_s3284_celltop s8te2et_s3284_celltop_nc |
| validCoreID5 = INSIDE CELL COREID s8te2et_s3286_cell2x2 s8te2et_s3286_cell2x2_nc s8te2et_s3286_cell2x2_nosrc s8te2et_s3287_2t_cell_end02_opt3_L s8te2et_s3287_2x2 s8te2et_s3287_2x2_Bot s8te2et_s3287_2x2_NoVia s8te2et_s3287_2x2_NoViaB s8te2et_s3287_2x2_Top s8te2et_s3287_32x32_Array s8te2et_s3287_32x32_Array_b s8te2et_s3287_cell_end01 s8te2et_s3287_cell_end01_NoVia s8te2et_s3289_14T_latch s8te2et_s3t_cell_end s8te2et_s3t_cell_end_01 s8te2et_s3t_cell_end_01_NoVia s8te2et_s3t_cell_end_NoVia s8te2et_s3t_cellcrnr_01_L s8te2et_s3t_cellcrnr_01_R s8te2et_s3t_cellcrnr_L s8te2et_s3t_cellcrnr_R s8te2et_s4100_2t_cell_end02_opt3_L s8te2et_s4100_2t_cell_option3_NP1 s8te2et_s4100_2t_cell_option3_swap_ncTop s8te2et_s4100_2t_cell_option3_swap1_ncBot s8te2et_s4100_2t_cellcrnr_01_L s8te2et_s4100_2t_cellend_R s8te2et_s4100_2t_cellend_R01 s8te2et_s4101_2t_cell_option3_IP2 s8te2et_s4102_2t_cell_option3_swap_ncTop s8te2et_s4102_2t_cell_option3_swap1_ncBot s8te2et_s4102_2t_cell_STD s8te2et_s4102_2t_cellend_L s8te2et_s4102_2t_cellend_R s8te2et_s4102_2t_cellend_R01 s8te2et_s4103_2t_cell_Bot s8te2et_s4103_2t_cell_NoLvtn s8te2et_s4103_2t_cell_NP1 s8te2et_s4103_2t_cell_option3_swap_ncTop s8te2et_s4103_2t_cell_option3_swap1_ncBot s8te2et_s4103_2t_cell_Top s8te2et_s4103_2t_cellend_L s8te2et_s4103_2t_cellend_L_NoLvtn s8te2et_s4103_2t_cellend_R s8te2et_s4103_2t_cellend_R01 s8te2et_s4104_2t_cell_Bot s8te2et_s4104_2t_cell_NP2 s8te2et_s4104_2t_cell_Top s8te2et_s4104_2t_cellend_L s8te2et_s4105_2t_cell_Bot s8te2et_s4105_2t_cell_NP3 s8te2et_s4105_2t_cell_Top s8te2et_s4105_2t_cellend_L s8te2et_s4105_2t_cellend_R s8te2et_s4105_2t_cellend_R01 s8te2et_s4106_2t_cell_Bot s8te2et_s4106_2t_cell_NP4 s8te2et_s4106_2t_cell_Top s8te2et_s4106_2t_cellend_L s8te2et_s4106_2t_cellend_R s8te2et_s4106_2t_cellend_R01 s8te2et_s4107_2t_cell_Bot s8te2et_s4107_2t_cell_NP5 s8te2et_s4107_2t_cell_Top s8te2et_s4107_2t_cellend_L s8te2et_s4107_2t_cellend_R s8te2et_s4107_2t_cellend_R01 s8te2et_s4108_2t_cell_Bot s8te2et_s4108_2t_cell_STD s8te2et_s4108_2t_cell_Top s8te2et_s4108_2t_cellend_L s8te2et_s4108_2t_cellend_R s8te2et_s4108_2t_cellend_R01 s8te2et_s4109_2t_cell_Bot s8te2et_s4109_2t_cell_NP1 s8te2et_s4109_2t_cell_Top s8te2et_s4109_2t_cellend_L s8te2et_s4109_2t_cellend_R s8te2et_s4109_2t_cellend_R01 s8te2et_s4110_2t_cell_Bot s8te2et_s4110_2t_cell_NP2 s8te2et_s4110_2t_cell_Top s8te2et_s4110_2t_cellend_L s8te2et_s4111_2t_cell_Bot s8te2et_s4111_2t_cell_NP3 s8te2et_s4111_2t_cell_Top s8te2et_s4111_2t_cellend_L s8te2et_s4112_2t_cell_Bot s8te2et_s4112_2t_cell_NP4 s8te2et_s4112_2t_cell_Top s8te2et_s4112_2t_cellend_L s8te2et_s4112_2t_cellend_R s8te2et_s4112_2t_cellend_R01 s8te2et_s4113_2t_cell_Bot |
| validCoreID6 = INSIDE CELL COREID s8te2et_s4113_2t_cell_NP5 s8te2et_s4113_2t_cell_Top s8te2et_s4113_2t_cellend_L s8te2et_s4113_2t_cellend_R s8te2et_s4113_2t_cellend_R01 s8te2et_s4114_2t_cell_Bot s8te2et_s4114_2t_cell_STD s8te2et_s4114_2t_cell_Top s8te2et_s4114_2t_cellend_L s8te2et_s4114_2t_cellend_R s8te2et_s4114_2t_cellend_R01 s8te2et_s4115_2t_cell_Bot s8te2et_s4115_2t_cell_NP1 s8te2et_s4115_2t_cell_Top s8te2et_s4115_2t_cellend_L s8te2et_s4115_2t_cellend_R s8te2et_s4115_2t_cellend_R01 s8te2et_s4116_2t_cell_Bot s8te2et_s4116_2t_cell_NP2 s8te2et_s4116_2t_cell_Top s8te2et_s4116_2t_cellend_L s8te2et_s4117_2t_cell_Bot s8te2et_s4117_2t_cell_NP3 s8te2et_s4117_2t_cell_Top s8te2et_s4117_2t_cellend_L s8te2et_s4118_2t_cell_Bot s8te2et_s4118_2t_cell_NP4 s8te2et_s4118_2t_cell_Top s8te2et_s4118_2t_cellend_L s8te2et_s4118_2t_cellend_R s8te2et_s4118_2t_cellend_R01 s8te2et_s4119_2t_cell_Bot s8te2et_s4119_2t_cell_NP5 s8te2et_s4119_2t_cell_Top s8te2et_s4119_2t_cellend_L s8te2et_s4119_2t_cellend_R s8te2et_s4119_2t_cellend_R01 s8te2et_s4120_2t_cell_Bot s8te2et_s4120_2t_cell_STD s8te2et_s4120_2t_cell_Top s8te2et_s4120_2t_cellend_L s8te2et_s4120_2t_cellend_R s8te2et_s4120_2t_cellend_R01 s8te2et_s4121_2t_cell_Bot s8te2et_s4121_2t_cell_NP1 s8te2et_s4121_2t_cell_Top s8te2et_s4121_2t_cellend_L s8te2et_s4121_2t_cellend_R s8te2et_s4121_2t_cellend_R01 s8te2et_s4122_2t_cell_Bot s8te2et_s4122_2t_cell_NP2 s8te2et_s4122_2t_cell_Top s8te2et_s4122_2t_cellend_L s8te2et_s4123_2t_cell_Bot s8te2et_s4123_2t_cell_NP3 s8te2et_s4123_2t_cell_Top s8te2et_s4123_2t_cellend_L s8te2et_s4124_2t_cell_Bot s8te2et_s4124_2t_cell_NP4 s8te2et_s4124_2t_cell_Top s8te2et_s4124_2t_cellend_L s8te2et_s4124_2t_cellend_R s8te2et_s4124_2t_cellend_R01 s8te2et_s4125_2t_cell_Bot s8te2et_s4125_2t_cell_NP5 s8te2et_s4125_2t_cell_Top s8te2et_s4125_2t_cellend_L s8te2et_s4125_2t_cellend_R s8te2et_s4125_2t_cellend_R01 s8te2et_s4126_2t_cell_Bot s8te2et_s4126_2t_cell_STD s8te2et_s4126_2t_cell_Top s8te2et_s4126_2t_cellend_L s8te2et_s4126_2t_cellend_R s8te2et_s4126_2t_cellend_R01 s8te2et_s4127_2t_cell_Bot s8te2et_s4127_2t_cell_NP1 s8te2et_s4127_2t_cell_Top s8te2et_s4127_2t_cellend_L s8te2et_s4127_2t_cellend_R s8te2et_s4127_2t_cellend_R01 s8te2et_s4128_2t_cell_Bot s8te2et_s4128_2t_cell_NP2 s8te2et_s4128_2t_cell_Top s8te2et_s4128_2t_cellend_L s8te2et_s4128_2t_cellend_R s8te2et_s4128_2t_cellend_R01 s8te2et_s4129_2t_cell_Bot s8te2et_s4129_2t_cell_NP3 s8te2et_s4129_2t_cell_Top s8te2et_s4129_2t_cellend_L s8te2et_s4129_2t_cellend_R s8te2et_s4129_2t_cellend_R01 s8te2et_s4130_2t_cell_Bot s8te2et_s4130_2t_cell_NP4 |
| validCoreID7 = INSIDE CELL COREID s8te2et_s4130_2t_cell_Top s8te2et_s4130_2t_cellend_L s8te2et_s4130_2t_cellend_R s8te2et_s4130_2t_cellend_R01 s8te2et_s4131_2t_cell_Bot s8te2et_s4131_2t_cell_NP5 s8te2et_s4131_2t_cell_Top s8te2et_s4131_2t_cellend_L s8te2et_s4131_2t_cellend_R s8te2et_s4131_2t_cellend_R01 s8te2et_s4132_2t_cellend_L s8te2et_s4132_3t_cell_Bot s8te2et_s4132_3t_cell_STD s8te2et_s4132_3t_cell_Top s8te2et_s4132_3t_cellend_R s8te2et_s4132_3t_cellend_R01 s8te2et_s4133_2t_cellend_L s8te2et_s4133_3t_cell_Bot s8te2et_s4133_3t_cell_NP1 s8te2et_s4133_3t_cell_Top s8te2et_s4133_3t_cellend_R s8te2et_s4133_3t_cellend_R01 s8te2et_s4135_2t_cellend_L s8te2et_s4135_3t_cell_Bot s8te2et_s4135_3t_cell_NP3 s8te2et_s4135_3t_cell_Top s8te2et_s4135_3t_cellend_R s8te2et_s4135_3t_cellend_R01 s8te2et_s4150_2t_cell s8te2et_s4150_2t_cell_Bot s8te2et_s4150_2t_cell_Top s8te2et_s4150_2t_cellcrnr_L s8te2et_s4150_2t_cellcrnr_R s8te2et_s4150_2t_cellend_L s8te2et_s4150_2t_cellend_R s8te2et_s4150_32x32_Array s8te2et_s4151_2t_2x2_a s8te2et_s4151_2t_cell_end01 s8te2et_s4151_2t_cell_end01_no_mcon s8te2et_s4151_2t_cell_end02_L s8te2et_s4151_2t_cell_end02_R s8te2et_s4151_2t_cell_end02_R01 s8te2et_s4151_2t_cellcrnr_L s8te2et_s4151_2t_cellcrnr_R s8te2et_s4151_PassGate_sonos_2x2 s8te2et_s4151_PassGate_sonos_2x2_no_mcon s8te2et_s4152_2t_2x2_a s8te2et_s4152_PassGate_sonos_2x2 s8te2et_s4154_2t_cell_a s8te2et_s4154_2t_cell_end02_L s8te2et_s4154_2t_cell_end02_R s8te2et_s4154_2t_cell_end02_R01 s8te2et_s4154_2t_cell_ncBot s8te2et_s4154_2t_cell_ncTop s8te2et_s4155_2t_cell_a s8te2et_s4155_2t_cell_end02_L s8te2et_s4155_2t_cell_end02_R s8te2et_s4155_2t_cell_end02_R01 s8te2et_s4155_2t_cell_ncBot s8te2et_s4155_2t_cell_ncTop s8te2et_s4156_2t_cell s8te2et_s4156_2t_cell_end s8te2et_s4156_2t_cell_end_no_mcon s8te2et_s4156_2t_cell_ncBot s8te2et_s4156_2t_cell_ncTop s8te2et_s7300_DNW_Ring s8te2et_s7300_DNW_Ring_Big s8te2et_s7300_DNW_Ring_s s8te2et_s7306_cap_padNFPASS_a s8te2et_sonos_Diff_MiniArray_opt3 s8te2et_SONOS_L0p13_Wmin s8te2et_SONOS_L0p15_Wmin s8te2et_SONOS_L0p17_Wmin s8te2et_SONOS_L0p18_Wmin s8te2et_sonos_L0p22_W25 s8te2et_SONOS_L0p22_W25 s8te2et_SONOS_L0p22_Wmin s8te2et_SONOS_L0p26_Wmin s8te2et_sonos_L25_W25 s8te2et_SONOS_L25_W25 s8te2et_sonos_L25_W25_cntm_ldntm s8te2et_SONOS_L25_Wmin s8te2et_sonos_Lmin_W25 s8te2et_SONOS_Lmin_W25 s8te2et_sonos_Lmin_W25_cntm_ldntm s8te2et_SONOS_Lmin_Wmin s8te2et_sonos_Lp5_W25 s8te2et_sonos_Lp5_Wp8 s8te2et_Sonos_soFet_2x2 s8te2et_sonos_W1_L1 s8te2et_sonos_W1_L1_NoDnw s8te2et_sonos_W1_L25 s8te2et_sonos_W1_L25_NoDnw s8tnvet_md5216_a s8tnvet_s9xxx_cyp_cap_padNHLV40 |
| validCoreID8 = INSIDE CELL COREID s8tnvet_s9xxx_cyp_cap_padNPD40 s8tnvet_s9xxx_cyp_cap_padPPU40 s8tnvet_s9xxx_cyp_cap_padS40 s8tnvet_s9xxx_pcm_iso_ppu_14_15 s8tnvet_s9xxx_pcm_iso_ppu_21_15 s8tnvet_s9xxx_pcm_iso_ppu_30_15 s8tnvet_s9xxx_pcm_multi_nhlv s8tnvet_s9xxx_pcm_multi_npass s8tnvet_s9xxx_pcm_multi_npd s8tnvet_s9xxx_pcm_multi_ppu s8tnvet_s9xxx_sr_mcell s8tnvet_s9xxx_sr_mcell_nTfr_1x s8tnvet_s9xxx_sr_mcell_pLoad_1x s8tnvet_s9xxx_sr_mcell_pLoad_1x_2 s8tnvet_s9xxx_sr_mcell_rcl s8tnvet_s9xxx_sr_mcell_rcl_2 s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b_2 s8tnvet_s9xxx_sr_mcell_tie s8tnvet_s9xxx_sr_mcell_tie_special_L s8tnvet_s9xxx_sr_mcell_tie_special_R s8tnvet_s9xxx_sr_tcell s8cell_ee_vcctrk_cell s8cell_ee_vcctrk_cellcorn_p s8cell_ee_vcctrk_termcella s8cell_ee_vcctrk_cellcorn_n s8cell_ee_vcctrk_colend s8cell_ee_vcctrk_termcellb s8cell_ee_colenda_d s8cell_ee_colend_lasta_d "s8sram_tech_CD_top*" s8sram_tech_CD_lcross s8sram_tech_CD_top_pcell "s8cell_ee_tech_CD_top*" s8cell_ee_tech_CD_lcross s8cell_ee_tech_CD_top_pcell |
| validCoreID10 = INSIDE CELL COREID "s8q_tech_CD_top*" s8q_tech_CD_lcross s8q_tech_CD_top_pcell |
| validCoreIDAW = INSIDE CELL COREID sr_mcell_b_cell7 sr_mcell_tie_Mt_cell7 sr_tcell_tie_b_cell7 sr_mcell_t_cell7 sr_mcell_tie_Rb_cell7 sr_tcell_tie_t_cell7 sr_mcell_tie_END_b_cell7 sr_mcell_tie_Rt_cell7 sr_tcell_END_b_cell7 sr_mcell_tie_END_t_cell7 sr_tcell_b_cell7 sr_tcell_END_t_cell7 sr_mcell_tie_Lb_cell7 sr_tcell_t_cell7 sr_tcell_tie_Rb_cell7 sr_mcell_tie_Lt_cell7 sr_tcell_tie_Lt_cell7 sr_tcell_tie_Rt_cell7 sr_mcell_tie_Mb_cell7 sr_tcell_tie_Lb_cell7 sr_blld_tie "s8sram_s8p_tech_CD_top*" |
| validCoreID_TDRrevCA = INSIDE CELL COREID s8tnvpsr_bltd_eq s8tnvpsr_bltd_tie s8tnvpsr_blld_tie s8tnvpsr_blld s8tnvpsr_mcell_tie_END_sub_t_cell7 s8tnvpsr_mcell_tie_Mt_cell7 s8tnvpsr_mcell_tie_Lt_cell7 s8tnvpsr_mcell_tie_Rt_cell7 s8tnv64kssr_bltd_eq s8tnv64kssr_bltd_tie s8tnv64kssr_blld_tie s8tnv64kssr_blld |
| validCoreID_TDRrevCL = INSIDE CELL COREID s8fmlt64k_cell_cell s8fmlt64k_cell_cell_last s8fmlt64k_cell_cellcorn_n s8fmlt64k_cell_cellcorn_p s8fmlt64k_cell_colend_lasta_d s8fmlt64k_cell_colend_lastb s8fmlt64k_cell_colenda_d s8fmlt64k_cell_colendb s8fmlt64k_cell_strapn s8fmlt64k_cell_strapp |
| validCoreID_TDRrevCW = INSIDE CELL COREID s8rom_rom_wlvnb2 s8rom_romb0 s8rom_romb1 |
| validCoreID_s8fmlt_cell = INSIDE CELL COREID s8fmlt_cell_cell s8fmlt_cell_cellcorn_p s8fmlt_cell_colenda_d s8fmlt_cell_strapp s8fmlt_cell_cell_last s8fmlt_cell_colend_lasta_d s8fmlt_cell_colendb s8fmlt_cell_cellcorn_n s8fmlt_cell_colend_lastb s8fmlt_cell_strapn |
| validCoreID_product_srom = INSIDE CELL COREID "*_srom*_rom*" |
| validCoreID_s8fs = INSIDE CELL COREID s8fs_cell_vcctrk_cell s8fs_cell_bseln_endb s8fs_cell_strapn s8fs_cell_vcctrk_cellcorn_n s8fs_cell_bselp_enda_d s8fs_cell_strapn_colendb_d s8fs_cell_vcctrk_cellcorn_p s8fs_cell_cellcorn_n s8fs_cell_strapp s8fs_cell_vcctrk_colend s8fs_cell_cellcorn_p s8fs_cell_strapp_colenda_d s8fs_cell_vcctrk_termcella s8fs_cell_cellcorn_poly s8fs_cell_termcella s8fs_cell_vcctrk_termcellb s8fs_cell_colenda_d s8fs_cell_termcellb s8fs_cell_cell s8fs_cell_colendb |
| validCoreID = (((validCoreID1 OR validCoreID2) OR (validCoreID3 OR validCoreID4)) OR ((validCoreID5 OR validCoreID6) OR (validCoreID7 OR (validCoreID8 OR validCoreID10)))) OR (validCoreID9 OR |
| (validCoreIDAW OR |
| (validCoreID_TDRrevCA OR |
| (validCoreID_TDRrevCL OR |
| (validCoreID_TDRrevCW OR |
| (validCoreID_s8fmlt_cell OR |
| (validCoreID_product_srom OR validCoreID_s8fs))))))) |
| inValidCoreID = COREID NOT validCoreID |
| "r_1132_areaid.1" { |
| @ areaid.1: Unapproved cells contain areaid.ce layer |
| COPY inValidCoreID |
| } |
| met5_vpp = COPY met5 |
| via4_vpp = COPY via4 |
| met4_vpp = COPY met4 |
| via3_vpp = COPY via3 |
| CONNECT met3 met4_vpp BY via3_vpp |
| CONNECT met4 met5_vpp BY via4_vpp |
| nhvnativeW10 = EXPAND EDGE (LENGTH (nhvnative NOT COINCIDENT EDGE diff) == 10.0) INSIDE BY 0.005 |
| nhvnativeL4 = EXPAND EDGE (LENGTH (nhvnative COINCIDENT EDGE diff) == 4.0) INSIDE BY 0.005 |
| nhvnative10x4 = INTERACT (INTERACT nhvnative nhvnativeW10) nhvnativeL4 |
| xcmvpp2_nhvnative = INTERACT (EXTENT CELL "s8rf_xcmvpp2" ORIGINAL) ((EXTENT CELL "s8rf_xcmvpp2" ORIGINAL) AND nhvnative10x4) |
| pfet_moscap = phv OR |
| (pshort OR |
| (phighvt OR plowvt)) |
| phvW5 = EXPAND EDGE (LENGTH (pfet_moscap NOT COINCIDENT EDGE diff) == 5.0) INSIDE BY 0.005 |
| phvL4 = EXPAND EDGE (LENGTH (pfet_moscap COINCIDENT EDGE diff) == 4.0) INSIDE BY 0.005 |
| phv5x4 = INTERACT (INTERACT pfet_moscap phvW5) phvL4 |
| xcmvpp2_phv = INTERACT (EXTENT CELL "s8rf_xcmvpp2_nwell" ORIGINAL) ((EXTENT CELL "s8rf_xcmvpp2_nwell" ORIGINAL) AND phv5x4) |
| vpp_over_MOSCAP = xcmvpp2_nhvnative OR (xcmvpp2_phv AND capacitor) |
| vppM3ShieldA = EXTENT CELL "s8rf_xcmvpp1p8x1p8_m3shield" ORIGINAL |
| vppM3ShieldB = EXTENT CELL "s8rf_xcmvpp4p4x4p6_m3shield" ORIGINAL |
| vppM3ShieldC = EXTENT CELL "s8rf_xcmvpp8p6x7p9_m3shield" ORIGINAL |
| vppM3ShieldD = EXTENT CELL "s8rf_xcmvpp11p5x11p7_m3shield" ORIGINAL |
| cap100fF_liShield = EXTENT CELL "s8rf_xcmvpp11p5x11p7_m3_lishield" ORIGINAL |
| cap50fF_liShield = EXTENT CELL "s8rf_xcmvpp8p6x7p9_m3_lishield" ORIGINAL |
| cap12fF_liShield = EXTENT CELL "s8rf_xcmvpp4p4x4p6_m3_lishield" ORIGINAL |
| cap1fF_liShield = EXTENT CELL "s8rf_xcmvpp1p8x1p8_lishield" ORIGINAL |
| vppM5ShieldA = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m5shield" ORIGINAL |
| vppM5ShieldB = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_polym5shield" ORIGINAL |
| vppM5ShieldC = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_lim5shield" ORIGINAL |
| vppM5ShieldD = EXTENT CELL "s8rf2_xcmvpp8p6x7p9_m3_lim5shield" ORIGINAL |
| vppM5ShieldE = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m4shield" ORIGINAL |
| vppM5ShieldF = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_polym4shield" ORIGINAL |
| vppM5ShieldG = EXTENT CELL "s8rf2_xcmvpp6p8x6p1_polym4shield" ORIGINAL |
| vppM5ShieldH = EXTENT CELL "s8rf2_xcmvpp6p8x6p1_lim4shield" ORIGINAL |
| vppM5ShieldI = EXTENT CELL "s8rf2_xcmvppx4_2xnhvnative10x4" ORIGINAL |
| vppM5ShieldJ = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m3_lim5shield" ORIGINAL |
| vppM5ShieldK = EXTENT CELL "s8rf2_xcmvpp4p4x4p6_m3_lim5shield" ORIGINAL |
| vppM5ShieldL = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m1m4m5shield" ORIGINAL |
| vppM5ShieldM = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m1m4" ORIGINAL |
| vppM5ShieldN = EXTENT CELL "s8rf2_xcmvpp11p5x11p7_polym50p4shield" ORIGINAL |
| vppLIShield = EXTENT CELL "s8rf*_li*shield" |
| vppM3Shield = vppM3ShieldA OR |
| (vppM3ShieldB OR |
| (vppM3ShieldC OR vppM3ShieldD)) |
| vpp_w_met5 = vpp_hd5 OR |
| (vppM5ShieldA OR |
| (vppM5shieldB OR |
| (vppM5ShieldC OR |
| (vppM5ShieldD OR |
| (vppM5ShieldE OR |
| (vppM5shieldF OR |
| (vppM5ShieldG OR |
| (vppM5ShieldH OR |
| (vppM5ShieldI OR |
| (vppM5ShieldJ OR |
| (vppM5ShieldK OR |
| (vppM5ShieldL OR vppM5ShieldN)))))))))))) |
| vpp_hd5_atlas = EXTENT CELL "s8rf2_xcmvpp_hd5_atlas*" ORIGINAL |
| vpp_w_met5_noatlas = vpp_w_met5 NOT vpp_hd5_atlas |
| vpp_w_met5polyShield = vpp_hd5 OR |
| (vppM5ShieldF OR |
| (vppM5ShieldG OR |
| (vppM5ShieldI OR |
| (vppM5ShieldB OR vppM5ShieldN)))) |
| vppShield = vppM3Shield OR |
| (vppLIShield OR vpp_w_met5) |
| vpp5c_unexempt = vppM5ShieldM OR vpp_hd5_atlas |
| vpp_w_noLi = (EXTENT CELL "s8rf2_xcmvpp3" ORIGINAL) OR |
| ((EXTENT CELL "s8rf2_xcmvpp4" ORIGINAL) OR |
| ((EXTENT CELL "s8rf2_xcmvpp5" ORIGINAL) OR |
| ((EXTENT CELL "s8rf2_xcmvpp4p4x4p6_m1m2" ORIGINAL) OR |
| ((EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m1m2" ORIGINAL) OR |
| ((EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m1m4" ORIGINAL) OR (EXTENT CELL "s8rf2_xcmvpp11p5x11p7_m1m4m5shield" ORIGINAL)))))) |
| vpp_err_li_exempt = vpp_w_noLi NOT vpp5c_unexempt |
| cap_in_noLi = capacitor AND vpp_w_noLi |
| cap_Li = capacitor NOT cap_in_noLi |
| capNotShield = capacitor NOT (vppM3Shield OR |
| (vppLIShield OR |
| (vpp_w_met5 OR vpp_w_noLi))) |
| capRing = (capacitor NOT (SIZE capacitor BY -0.005)) NOT vpp_over_MOSCAP |
| capRingLI = li1 AND capRing |
| capRingPY = poly AND capRing |
| capRingM1 = met1 AND capRing |
| capRingM2 = met2 AND capRing |
| capRingM3 = met3 AND capRing |
| capRingM4 = met4_vpp AND capRing |
| pyNOTcap = poly NOT capacitor |
| liNOTcap = li1 NOT capacitor |
| m1NOTcap = met1 NOT capacitor |
| m2NOTcap = met2 NOT capacitor |
| m3NOTcap = met3 NOT capacitor |
| m4NOTcap = met4_vpp NOT capacitor |
| m5NOTcap = met5_vpp NOT capacitor |
| vpp_5_flag_li = (INTERACT (EXTERNAL liNOTcap capRingLI < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL liNOTcap capRingPY < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL liNOTcap capRingM1 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR (INTERACT (EXTERNAL liNOTcap capRingM2 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield))) |
| vpp_5_flag_py = (INTERACT (EXTERNAL pyNOTcap capRingLI < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL pyNOTcap capRingPY < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL pyNOTcap capRingM1 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR (INTERACT (EXTERNAL pyNOTcap capRingM2 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield))) |
| vpp_5_flag_m1 = (INTERACT (EXTERNAL m1NOTcap capRingLI < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL m1NOTcap capRingPY < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL m1NOTcap capRingM1 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR (INTERACT (EXTERNAL m1NOTcap capRingM2 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield))) |
| vpp_5_flag_m2 = (INTERACT (EXTERNAL m2NOTcap capRingLI < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL m2NOTcap capRingPY < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR |
| ((INTERACT (EXTERNAL m2NOTcap capRingM1 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield) OR (INTERACT (EXTERNAL m2NOTcap capRingM2 < 1.5 ABUT < 90 NOT CONNECTED SINGULAR REGION) capNotShield))) |
| vpp_5_err_li = vpp_5_flag_li NOT (WITH WIDTH (AREA vpp_5_flag_li < 2.25) < 2.0) |
| vpp_5_err_py = vpp_5_flag_py NOT (WITH WIDTH (AREA vpp_5_flag_py < 2.25) < 2.0) |
| vpp_5_err_m1 = vpp_5_flag_m1 NOT (WITH WIDTH (AREA vpp_5_flag_m1 < 2.25) < 2.0) |
| vpp_5_err_m2 = vpp_5_flag_m2 NOT (WITH WIDTH (AREA vpp_5_flag_m2 < 2.25) < 2.0) |
| vpp_5a = DENSITY met3 > 0.25 INSIDE OF LAYER capacitor |
| vpp_5b = DENSITY met4 > 0.3 INSIDE OF LAYER capacitor |
| vpp_5c = DENSITY met5 > 0.4 INSIDE OF LAYER capacitor |
| vpp_5a_err = vpp_5a NOT (vpp_over_MOSCAP OR |
| (vppShield OR vppM5ShieldM)) |
| vpp_5b_err = vpp_5b NOT (vppM3Shield OR |
| (vpp_w_met5 OR |
| (vpp_over_MOSCAP OR vppM5ShieldM))) |
| vpp_5c_err = vpp_5c NOT (vppM3Shield OR |
| (vpp_w_met5_noatlas OR |
| (vpp_over_MOSCAP OR vpp_err_li_exempt))) |
| vpp3_xmt1 = vppLIshield OR |
| (vpp_over_MOSCAP OR (INTERACT poly (poly AND (vppM3Shield OR vpp_w_met5polyShield)))) |
| vpp3_xmt2 = (diff OR tap) AND vpp_w_met5polyShield |
| vpp3NotXmt = capacitor NOT (vpp3_xmt1 OR vpp3_xmt2) |
| xcmvppCell = INSIDE CELL pwell_pin "s8rf_xcmvpp*" PRIMARY ONLY |
| capErr = INTERACT capacitor xcmvppCell > 1 |
| vpp9NotXmt = capacitor NOT vpp_over_MOSCAP |
| vppMosDens1 = DENSITY nhvnative10x4 < 0.87 INSIDE OF LAYER xcmvpp2_nhvnative |
| vppMosDens2 = DENSITY phv5x4 < 0.87 INSIDE OF LAYER (xcmvpp2_phv AND capacitor) |
| vpp_11_err = vppMosDens1 OR vppMosDens2 |
| vpp_12_good = RECTANGLE met4 == 2.01 ASPECT == 1 |
| vpp_12c_good = RECTANGLE met4 == 1.5 ASPECT == 1 |
| vpp_12a_err1 = INTERACT (capacitor AND vppM5shieldD) (met4 NOT vpp_12_good) |
| vpp_12a_err2 = INTERACT (capacitor AND vppM5shieldD) met4 != 9.0 |
| vpp_12b_err1 = INTERACT (capacitor AND vppM5shieldJ) (met4 NOT vpp_12_good) |
| vpp_12b_err2 = INTERACT (capacitor AND vppM5shieldJ) met4 != 16.0 |
| vpp_12c_err1 = INTERACT (capacitor AND vppM5shieldK) (met4 NOT vpp_12c_good) |
| vpp_12c_err2 = INTERACT (capacitor AND vppM5shieldK) met4 != 4.0 |
| vpp_12a_err = vpp_12a_err1 OR vpp_12a_err2 |
| vpp_12b_err = vpp_12b_err1 OR vpp_12b_err2 |
| vpp_12c_err = vpp_12c_err1 OR vpp_12c_err2 |
| vpp_1b_err = capacitor NOT (vpp_w_met5 OR |
| (vppM3Shield OR |
| (vpp_over_MOSCAP OR |
| (vppLIShield OR vpp_w_noLi)))) |
| "r_1133_vpp.5" { |
| @ vpp.5: 1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other li1 |
| COPY vpp_5_err_li |
| } |
| "r_1134_vpp.5" { |
| @ vpp.5: 1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other poly |
| COPY vpp_5_err_py |
| } |
| "r_1135_vpp.5" { |
| @ vpp.5: 1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other met1 |
| COPY vpp_5_err_m1 |
| } |
| "r_1136_vpp.5" { |
| @ vpp.5: 1.5 min spacing of (li1, poly, or met1/2) overlapping cap.dg to other met2 |
| COPY vpp_5_err_m2 |
| } |
| "r_1137_vpp.5a" { |
| @ vpp.5a: 0.25 max PD ratio of met3.dg to capacitor.dg |
| COPY vpp_5a_err |
| } |
| "r_1138_vpp.5b" { |
| @ vpp.5b: 0.3 max PD ratio of met4.dg to capacitor.dg |
| COPY vpp_5b_err |
| } |
| "r_1139_vpp.5c" { |
| @ vpp.5c: 0.4 max PD ratio of met5.dg to capacitor.dg |
| COPY vpp_5c_err |
| } |
| "r_1140_vpp.10" { |
| @ vpp.10: capacitors are not allow to overlap |
| COPY capErr |
| } |
| "r_1141_vpp.11" { |
| @ vpp.11: 0.87 Minimum vpp_over_MOSCAP density over related gate |
| COPY vpp_11_err |
| } |
| "r_1142_vpp.12a" { |
| @ vpp.12a: capacitor in s8rf2_xcmvpp8p6x7p9_m3_lim5shield must overlap only 9.0 met4 2.01x2.01 polygons |
| COPY vpp_12a_err |
| } |
| "r_1143_vpp.12b" { |
| @ vpp.12b: capacitor in s8rf2_xcmvpp11p5x11p7_m3_lim5shield must overlap only 16.0 met4 2.01x2.01 polygons |
| COPY vpp_12b_err |
| } |
| "r_1144_vpp.12c" { |
| @ vpp.12c: capacitor in s8rf2_xcmvpp4p4x4p6_m3_lim5shield must overlap only 4.0 met4 1.5x1.5 polygons |
| COPY vpp_12c_err |
| } |
| "r_1145_vpp.1" { |
| @ vpp.1: 1.43 min. width of capacitor |
| INTERNAL capacitor < 1.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1146_vpp.1b" { |
| @ vpp.1b: 11.35 max. width of vpp_1b_err |
| q0vpp_1b_err = SIZE vpp_1b_err BY -5.675 |
| SIZE q0vpp_1b_err BY 5.675 |
| } |
| q0vppM3shieldA = NOT RECTANGLE vppM3shieldA ORTHOGONAL ONLY |
| "r_1147_vpp.1c" { |
| @ vpp.1c: vppM3shieldA should be rectangular |
| COPY q0vppM3shieldA |
| } |
| q1vppM3shieldA = INTERNAL vppM3shieldA < 3.88 REGION |
| "r_1148_vpp.1c" { |
| @ vpp.1c: 3.88 min. width of vppM3shieldA |
| COPY q1vppM3shieldA |
| } |
| q2vppM3shieldA = vppM3shieldA WITH EDGE (LENGTH vppM3shieldA > 3.88) |
| "r_1149_vpp.1c" { |
| @ vpp.1c: 3.88 max. length of vppM3shieldA |
| COPY q2vppM3shieldA |
| } |
| "r_1150_vpp.3" { |
| @ vpp.3: vpp3NotXmt must not overlap poly |
| @ vpp.3: vpp3NotXmt must not overlap diff |
| @ vpp.3: vpp3NotXmt must not overlap tap |
| vpp3NotXmt AND poly |
| vpp3NotXmt AND diff |
| vpp3NotXmt AND tap |
| } |
| "r_1151_vpp.4" { |
| @ vpp.4: capacitor must not straddle nwell |
| CUT capacitor nwell |
| } |
| "r_1152_vpp.4" { |
| @ vpp.4: capacitor must not straddle dnwell |
| CUT capacitor dnwell |
| } |
| "r_1153_vpp.8" { |
| @ vpp.8: 1.5 min. enclosure of capacitor by nwell |
| q2capacitorand = capacitor AND nwell |
| ENCLOSURE q2capacitorand nwell < 1.5 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1154_vpp.9" { |
| @ vpp.9: 1.5 min. spacing of capacitor & nwell |
| EXTERNAL vpp9NotXmt nwell < 1.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| VHVDiff = diff AND vhvi |
| VHVdiffResblock = WITH TEXT diffres "vhv_block" |
| VHVpolyResblock = WITH TEXT polyres "vhv_block" |
| VHVpwmResblock = WITH TEXT pwres "vhv_block" |
| PwellRes = INTERACT DnwNoRing (DnwNoRing AND pwres) |
| pwellNoBlockRes = PwellRes NOT (INTERACT PwellRes (PwellRes AND VHVpwmResblock)) |
| Polyconn = licon1 AND npc |
| diffNoBlockRes = diff NOT VHVdiffResblock |
| diffResTerminal = (TOUCH diffNoBlockRes diffres) INSIDE licon1 |
| polyNoBlockRes = poly NOT VHVpolyResblock |
| polyResTerminal = (TOUCH polyNoBlockRes polyres) INSIDE Polyconn |
| VHVSrcDrnProp = diffTap NOT (poly OR |
| (VHVdiffResblock OR |
| (diffResTerminal OR ESDID))) |
| VHVSrcDrn = INTERACT VHVSrcDrnProp (VHVSrcDrnProp AND vhvi) |
| VHVPolyProp = poly NOT (VHVpolyResblock OR polyResTerminal) |
| VHVPoly = INTERACT VHVPolyProp (VHVPolyProp AND vhvi) |
| VHVGate = VHVPoly AND diff |
| LiconTpNwell = licon1 AND (tap AND nwell) |
| DISCONNECT |
| CONNECT dnwell nwell |
| CONNECT nwell li1 BY LiconTpNwell |
| CONNECT li1 met1 BY mcon |
| CONNECT met1 met2 BY via |
| CONNECT VHVSrcDrnProp li1 BY licon1 |
| CONNECT VHVPolyProp li1 BY Polyconn |
| CONNECT VHVSrcDrn VHVSrcDrnProp BY vhvi |
| CONNECT VHVPoly VHVPolyProp BY vhvi |
| CONNECT pwellNoBlockRes li1 BY GoodTapLicon |
| CONNECT met3 met2 BY via2 |
| CONNECT met3 met4 BY via3 |
| CONNECT met4 met5 BY via4 |
| CONNECT met5 pad |
| CONNECT rdl pad |
| DiffConnVHVSrcDrn = NET AREA RATIO VHVSrcDrnProp VHVSrcDrn > 0 |
| DiffConnVHVSrcDrnErr = DiffConnVHVSrcDrn NOT (ESDID OR |
| (ENID OR VHVSrcDrn)) |
| VHVoverCE = INTERACT vhvi (vhvi AND COREID) |
| PolyVHVSrcDrnConn = NET AREA RATIO VHVPolyProp VHVSrcDrn > 0 |
| VHVPolyVHVSrcDrnConn = INTERACT PolyVHVSrcDrnConn (PolyVHVSrcDrnConn AND vhvi) |
| VHVNoPolyVHVSrcDrnConn = PolyVHVSrcDrnConn NOT VHVPolyVHVSrcDrnConn |
| VHVvhvSrcDrn = INTERACT vhvi (vhvi AND VHVSrcDrn) |
| VHVvhvSrcDrnoverPoly = INTERACT VHVvhvSrcDrn (VHVvhvSrcDrn AND poly) |
| VHVnwell = INTERACT nwell (nwell AND vhvi) |
| NSrcDrnProp = VHVSrcDrnProp NOT ((INTERACT diff (diff AND VHVnwell)) OR nwell) |
| VHVnwellDnConn = NET AREA RATIO dnwell VHVnwell > 0 |
| VHVnwellNwConn = NET AREA RATIO nwell VHVnwell > 0 |
| VHVnwellNdiffConn = NET AREA RATIO NSrcDrnProp VHVnwell > 0 |
| VHVnwellDnNoConn = dnwell NOT VHVnwellDnConn |
| VHVnwellNwNoConn = nwell NOT VHVnwellNwConn |
| VHVnwellNdiffNoConn = NSrcDrnProp NOT VHVnwellNdiffConn |
| VHVnwellNoConn = VHVnwellDnNoConn OR |
| (VHVnwellNwNoConn OR VHVnwellNdiffNoConn) |
| "r_1155_vhvi.vhv.5" { |
| @ vhvi.vhv.5: diffusion not in drain-extended devices must not be connected to VHVSrcDrn |
| COPY DiffConnVHVSrcDrnErr |
| } |
| "r_1156_vhvi.1" { |
| @ vhvi.1: 0.02 min. width of vhvi |
| INTERNAL vhvi < 0.02 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1157_vhvi.2" { |
| @ vhvi.2: vhvi must not overlap areaid.ce |
| COPY VHVoverCE |
| } |
| "r_1158_vhvi.3" { |
| @ vhvi.3: VHVGate must overlap hvi |
| VHVGate OUTSIDE hvi |
| } |
| "r_1159_vhvi.4" { |
| @ vhvi.4: poly connected to same net as VHVsourcedrain must be tagged by vhvi |
| COPY VHVNoPolyVHVSrcDrnConn |
| } |
| "r_1160_vhvi.5" { |
| @ vhvi.5: vhvi must not straddle VHVSrcDrn |
| CUT vhvi VHVSrcDrn |
| } |
| "r_1161_vhvi.6" { |
| @ vhvi.6: vhvi overlapping VHVSrcDrn must not overlap poly |
| COPY VHVvhvSrcDrnoverPoly |
| } |
| "r_1162_vhvi.7" { |
| @ vhvi.7: vhvi must not straddle VHVPoly |
| CUT vhvi VHVPoly |
| } |
| "r_1163_vhvi.8" { |
| @ vhvi.8: 11.24 min. spacing of VHVnwell & VHVnwellNoConn |
| EXTERNAL VHVnwell VHVnwellNoConn < 11.24 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| HVSrcDrnProp = diff NOT (diffres OR poly) |
| HVSrcDrn = INTERACT HVSrcDrnProp (HVSrcDrnProp AND diffhvp) |
| HVnSrcDrn = HVSrcDrn NOT nwell |
| HVpolyNotRes = poly NOT polyres |
| lcTapnw = INTERACT licon1 (licon1 AND (tap AND nwell)) |
| DISCONNECT |
| CONNECT dnwell nwell |
| CONNECT nwell li1 BY lcTapnw |
| CONNECT li1 met1 BY mcon |
| CONNECT met1 met2 BY via |
| CONNECT HVSrcDrnProp li1 BY licon1 |
| CONNECT HVpolyNotRes li1 BY npccon |
| CONNECT HVSrcDrn HVSrcDrnProp BY diffhvp |
| CONNECT met3 met2 BY via2 |
| CONNECT met3 met4 BY via3 |
| CONNECT met4 met5 BY via4 |
| CONNECT met5 pad |
| CONNECT rdl pad |
| diffTapEdge1 = diff COINCIDENT OUTSIDE EDGE tap |
| diffHVminSpc = EXTERNAL [HVSrcDrn] diff < 0.3 ABUT < 90 SINGULAR |
| hvSrcDrnnoTap = diffHVminSpc NOT COINCIDENT EDGE diffTapEdge1 |
| diffConnHVSrcDrn = NET AREA RATIO HVSrcDrnProp HVSrcDrn > 0 |
| nwellConHVdiff = NET AREA RATIO nwell HVSrcDrn > 0 |
| diffResButtHV = diffres WITH EDGE (diffres COINCIDENT OUTSIDE EDGE diffConnHVSrcDrn) |
| diffDiodeHV = DIODEID AND diffConnHVSrcDrn |
| ndiffResButtHV = diffResButtHV NOT nwell |
| ndiffDiodeHV = diffDiodeHV NOT nwell |
| hvPoly = NET AREA RATIO HVpolyNotRes HVSrcDrn > 0 |
| hvPd_0 = hvPoly OUTSIDE diff |
| hvPd_1 = INTERACT hvPoly diff == 1 |
| badHvPolytmp = hvPoly OUTSIDE (hvPd_0 OR hvPd_1) |
| hvPolyTexted = WITH TEXT hvPoly "hv_bb" |
| badHvPoly = badHvPolytmp NOT hvPolyTexted |
| hvPolyField = hvPoly NOT (ENID OR GATE) |
| hvPolyExmpt = hvPolyField NOT hvPolyTexted |
| deFetStradNW = CUT deFetPoly nwell |
| hvPolyExmpt2 = hvPolyExmpt NOT deFetStradNW |
| nwellHoleEdge = nwellring COINCIDENT EDGE nwellHoles |
| BadhvpolyEdge = nwell INSIDE EDGE hvPolyExmpt |
| badHvPoly2 = BadhvpolyEdge NOT COINCIDENT EDGE nwellHoleEdge |
| DiffButthvPolyExmpt = diff WITH EDGE (diff COINCIDENT OUTSIDE EDGE hvPolyExmpt) |
| hvPolyExmptDiff = hvPolyExmpt OR DiffButthvPolyExmpt |
| unrelDiff = diff NOT hvPolyExmptDiff |
| normSRCDRN = SRCDRN NOT HVSrcDrn |
| hvGate = GATE WITH EDGE (GATE COINCIDENT OUTSIDE EDGE HVSrcDrn) |
| hvGateButtSRCDRN = hvGate WITH EDGE (hvGate COINCIDENT OUTSIDE EDGE normSRCDRN) |
| hvGateButtSRCDRNtexted = WITH TEXT hvGateButtSRCDRN "hv_lv" |
| hvGateExmpt = hvGate NOT hvGateButtSRCDRNtexted |
| hvGateEdge = hvGateExmpt COINCIDENT INSIDE EDGE diff |
| hvGateEdgeBad = ENCLOSURE [hvGateEdge] poly < 0.16 MEASURE COINCIDENT ABUT < 90 |
| hvGateEdgeBadSz = EXPAND EDGE hvGateEdgeBad OUTSIDE BY 0.005 |
| hvGateExt = hvGateEdgeBadSz NOT ENID |
| GateExmpt = GATE NOT hvGateButtSRCDRNtexted |
| GateEdge = GateExmpt COINCIDENT INSIDE EDGE diff |
| p6bGateEdgeBad = ENCLOSURE [GateEdge] hvpoly < 0.16 MEASURE COINCIDENT ABUT < 90 |
| p6bGateEdgeBadSz = EXPAND EDGE p6bGateEdgeBad OUTSIDE BY 0.005 |
| p6bGateExt = p6bGateEdgeBadSz NOT ENID |
| "r_1164_hv.diff.1a" { |
| @ hv.diff.1a: Min space between hv_srcdrn and hv_srcdrn/diff for edges not butting tap is 0.3 |
| COPY hvSrcDrnnoTap |
| } |
| "r_1165_hv.diff.1b" { |
| @ hv.diff.1b: 0.3 min. spacing of diffResButtHV & diff |
| EXTERNAL diffResButtHV diff < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1166_hv.diff.1b" { |
| @ hv.diff.1b: 0.3 min. spacing of diffDiodeHV & diff |
| EXTERNAL diffDiodeHV diff < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1167_hv.diff.2" { |
| @ hv.diff.2: 0.43 min. spacing of nwellConHVdiff & ndiff (not for source of drain extended device) |
| EXTERNAL nwellConHVdiff ENIDNsource < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1168_hv.diff.3a" { |
| @ hv.diff.3a: 0.55 min. spacing of HVnSrcDrn & nwell |
| EXTERNAL HVnSrcDrn nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1169_hv.diff.3b" { |
| @ hv.diff.3b: 0.55 min. spacing of diffResButtHV & nwell |
| EXTERNAL diffResButtHV nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1170_hv.diff.3b" { |
| @ hv.diff.3b: 0.55 min. spacing of diffDiodeHV & nwell |
| EXTERNAL diffDiodeHV nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1171_hv.poly.1" { |
| @ hv.poly.1: hv poly can be drawn over only one diff |
| COPY badHvPoly |
| } |
| "r_1172_hv.poly.1" { |
| @ hv.poly.1: hvPolyExmpt must not straddle nwell |
| CUT hvPolyExmpt nwell |
| } |
| "r_1173_hv.poly.1" { |
| @ hv.poly.1: hvpoly cannot cross nwell boundary (except nwell hole edge |
| COPY badHvPoly2 |
| } |
| "r_1174_hv.poly.2" { |
| @ hv.poly.2: 0.3 min. spacing of hvPolyExmpt & unrelDiff |
| EXTERNAL hvPolyExmpt unrelDiff < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1175_hv.poly.3" { |
| @ hv.poly.3: 0.55 min. spacing of hvPolyExmpt2 & nwell |
| EXTERNAL hvPolyExmpt2 nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1176_hv.poly.4" { |
| @ hv.poly.4: 0.3 min. enclosure of hvPolyExmpt2 by nwell |
| q0hvPolyExmpt2and = hvPolyExmpt2 AND nwell |
| ENCLOSURE q0hvPolyExmpt2and nwell < 0.3 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1177_hv.poly.6a" { |
| @ hv.poly.6a: 0.16 min extension of poly beyond hv gate is |
| COPY hvGateExt |
| } |
| "r_1178_hv.poly.6b" { |
| @ hv.poly.6b: 0.16 min extension of hvpoly beyond gate |
| COPY p6bGateExt |
| } |
| capSz = SIZE capacitor BY 0.17 |
| x22_exempt = exempt_tech_CD OR |
| (inductor_exempt OR |
| (moduleCutAREA OR |
| (capSz OR (EXTENT CELL "s8blerf_*")))) |
| licon1ply = licon1 OUTSIDE diffTap |
| licon1fom = licon1 NOT licon1ply |
| licon1NDIFF = licon1fom AND NDIFF |
| licon1PDIFF = licon1fom AND PDIFF |
| licon1NTAP = licon1fom AND NTAP |
| licon1PTAP = licon1fom AND PTAP |
| topCell_li1_pin = INSIDE CELL li1_pin "s8pir_10r_vcells_drc" PRIMARY ONLY |
| topCell_poly_pin = INSIDE CELL poly_pin "s8pir_10r_vcells_drc" PRIMARY ONLY |
| topCell_met1_pin = INSIDE CELL met1_pin "s8pir_10r_vcells_drc" PRIMARY ONLY |
| topCell_met2_pin = INSIDE CELL met2_pin "s8pir_10r_vcells_drc" PRIMARY ONLY |
| topCell_met3_pin = INSIDE CELL met3_pin "s8pir_10r_vcells_drc" PRIMARY ONLY |
| polyToGateContact = COPY GATE |
| DISCONNECT |
| CONNECT li1 pSRCDRN BY licon1PDIFF |
| CONNECT li1 nSRCDRN BY licon1NDIFF |
| CONNECT li1 PTAP BY licon1PTAP |
| CONNECT li1 NTAP BY licon1NTAP |
| CONNECT li1 poly BY licon1ply |
| CONNECT poly GATE BY polyToGateContact |
| CONNECT met1 li1 BY mcon |
| CONNECT met2 met1 BY via |
| CONNECT met3 met3tt |
| CONNECT met2 met2tt |
| CONNECT met1 met1tt |
| CONNECT li1 li1tt |
| CONNECT poly polytt |
| CONNECT pad padtt |
| CONNECT poly topCell_poly_pin polypt |
| CONNECT li1 topCell_li1_pin li1pt |
| CONNECT met1 topCell_met1_pin met1pt |
| CONNECT met2 topCell_met2_pin met2pt |
| CONNECT met3 topCell_met3_pin met3pt |
| CONNECT pad pad_pin padpt |
| CONNECT met3 met2 BY via2 |
| topCell_met4_pin = INSIDE CELL met4_pin "s8pir_10r_vcells_drc" PRIMARY ONLY |
| topCell_met5_pin = INSIDE CELL met5_pin "s8pir_10r_vcells_drc" PRIMARY ONLY |
| CONNECT met4 met3 BY via3 |
| CONNECT met4 met4tt |
| CONNECT met4 topCell_met4_pin met4pt |
| CONNECT met5 met4 BY via4 |
| CONNECT met5 met5tt |
| CONNECT met5 topCell_met5_pin met5pt |
| CONNECT pad met5 |
| floating_poly_net_tmp = NET AREA RATIO poly OVER pSRCDRN nSRCDRN PTAP NTAP topCell_li1_pin topCell_met1_pin topCell_met2_pin topCell_met3_pin pad_pin topCell_met4_pin topCell_met5_pin topCell_poly_pin GATE == 0 |
| floating_poly_net_no_xmt = floating_poly_net_tmp NOT x22_exempt |
| float_text_poly_extent = EXPAND TEXT "poly_float" BY (0.005 * 2) |
| tie_text_poly_extent = EXPAND TEXT "poly_tie" BY (0.005 * 2) |
| floating_poly_netTexted = (WITH TEXT floating_poly_net_tmp "poly_float" textlabel) NOT x22_exempt |
| tie_poly_netTexted = (WITH TEXT floating_poly_net_tmp "poly_tie" textlabel) NOT x22_exempt |
| floating_tie_poly_netTexted = floating_poly_netTexted AND tie_poly_netTexted |
| floating_poly_netBad = floating_poly_net_no_xmt NOT floating_poly_netTexted |
| floating_poly_net = floating_poly_netBad AND SEALnoHoles_ORIGIN |
| floating_poly_net_tie = floating_poly_net AND tie_poly_netTexted |
| floating_poly_net_notie = floating_poly_net NOT tie_poly_netTexted |
| floating_poly_netIPtmp = floating_poly_netBad NOT SEALnoHoles_ORIGIN |
| floating_poly_netIPtmp2 = floating_poly_netIPtmp NOT tie_poly_netTexted |
| floating_poly_netIPsc = floating_poly_netIPtmp2 INSIDE STDCID |
| floating_poly_netIP = floating_poly_netIPtmp2 NOT floating_poly_netIPsc |
| connected_poly_net_tmp = poly NOT floating_poly_net_tmp |
| bad_connected_poly_net_tmp = WITH TEXT connected_poly_net_tmp "poly_float" textlabel |
| bad_connected_poly_net = bad_connected_poly_net_tmp AND SEALnoHoles_ORIGIN |
| bad_connected_poly_netIP = bad_connected_poly_net_tmp NOT SEALnoHoles_ORIGIN |
| floating_tie_poly_netTexted_IP = floating_tie_poly_netTexted NOT SEALnoHoles_ORIGIN |
| floating_tie_poly_netTexted_chip = floating_tie_poly_netTexted AND SEALnoHoles_ORIGIN |
| allChipNotpolytmppoly_float = chip NOT "poly" |
| allChipNotpoly = allChipNotpolytmppoly_float AND SEALnoHoles_ORIGIN |
| allChipNotpolyIP = allChipNotpolytmppoly_float NOT SEALnoHoles_ORIGIN |
| extraneous_poly_floatText = allChipNotpoly AND (float_text_poly_extent OR tie_text_poly_extent) |
| extraneous_poly_floatTextIP = allChipNotpolyIP AND (float_text_poly_extent OR tie_text_poly_extent) |
| "s_9_X.22" { |
| @ X.22: Floating poly_float or poly_tie text not over poly |
| COPY extraneous_poly_floatText |
| } |
| "s_10_X.22" { |
| @ X.22: poly marked with poly_float not floating |
| COPY bad_connected_poly_net |
| } |
| "s_11_X.22" { |
| @ X.22: Nets on poly is floating |
| COPY floating_poly_net_notie |
| } |
| "s_12_X.22" { |
| @ X.22: Floating poly marked with poly_tie at chiplevel without connecting |
| COPY floating_poly_net_tie |
| } |
| "s_13_X.22" { |
| @ X.22: Metal on poly is texted as both tied and floating (Chip level) |
| COPY floating_tie_poly_netTexted_chip |
| } |
| "r_1179_X.22" { |
| @ X.22: Floating poly_float or poly_tie text not over poly |
| COPY extraneous_poly_floatTextIP |
| } |
| "r_1180_X.22" { |
| @ X.22: poly marked with poly_float not floating |
| COPY bad_connected_poly_netIP |
| } |
| "r_1181_X.22" { |
| @ X.22: Nets on poly is floating |
| COPY floating_poly_netIP |
| } |
| "r_1182_X.22" { |
| @ X.22: Metal on poly is texted as both tied and floating (IP Level) |
| COPY floating_tie_poly_netTexted_IP |
| } |
| floating_li1_net_tmp = NET AREA RATIO li1 OVER pSRCDRN nSRCDRN PTAP NTAP topCell_li1_pin topCell_met1_pin topCell_met2_pin topCell_met3_pin pad_pin topCell_met4_pin topCell_met5_pin topCell_poly_pin GATE == 0 |
| floating_li1_net_no_xmt = floating_li1_net_tmp NOT x22_exempt |
| float_text_li1_extent = EXPAND TEXT "li1_float" BY (0.005 * 2) |
| tie_text_li1_extent = EXPAND TEXT "li1_tie" BY (0.005 * 2) |
| floating_li1_netTexted = (WITH TEXT floating_li1_net_tmp "li1_float" textlabel) NOT x22_exempt |
| tie_li1_netTexted = (WITH TEXT floating_li1_net_tmp "li1_tie" textlabel) NOT x22_exempt |
| floating_tie_li1_netTexted = floating_li1_netTexted AND tie_li1_netTexted |
| floating_li1_netBad = floating_li1_net_no_xmt NOT floating_li1_netTexted |
| floating_li1_net = floating_li1_netBad AND SEALnoHoles_ORIGIN |
| floating_li1_net_tie = floating_li1_net AND tie_li1_netTexted |
| floating_li1_net_notie = floating_li1_net NOT tie_li1_netTexted |
| floating_li1_netIPtmp = floating_li1_netBad NOT SEALnoHoles_ORIGIN |
| floating_li1_netIPtmp2 = floating_li1_netIPtmp NOT tie_li1_netTexted |
| floating_li1_netIPsc = floating_li1_netIPtmp2 INSIDE STDCID |
| floating_li1_netIP = floating_li1_netIPtmp2 NOT floating_li1_netIPsc |
| connected_li1_net_tmp = li1 NOT floating_li1_net_tmp |
| bad_connected_li1_net_tmp = WITH TEXT connected_li1_net_tmp "li1_float" textlabel |
| bad_connected_li1_net = bad_connected_li1_net_tmp AND SEALnoHoles_ORIGIN |
| bad_connected_li1_netIP = bad_connected_li1_net_tmp NOT SEALnoHoles_ORIGIN |
| floating_tie_li1_netTexted_IP = floating_tie_li1_netTexted NOT SEALnoHoles_ORIGIN |
| floating_tie_li1_netTexted_chip = floating_tie_li1_netTexted AND SEALnoHoles_ORIGIN |
| allChipNotli1tmpli1_float = chip NOT "li1" |
| allChipNotli1 = allChipNotli1tmpli1_float AND SEALnoHoles_ORIGIN |
| allChipNotli1IP = allChipNotli1tmpli1_float NOT SEALnoHoles_ORIGIN |
| extraneous_li1_floatText = allChipNotli1 AND (float_text_li1_extent OR tie_text_li1_extent) |
| extraneous_li1_floatTextIP = allChipNotli1IP AND (float_text_li1_extent OR tie_text_li1_extent) |
| "s_14_X.22" { |
| @ X.22: Floating li1_float or li1_tie text not over li1 |
| COPY extraneous_li1_floatText |
| } |
| "s_15_X.22" { |
| @ X.22: li1 marked with li1_float not floating |
| COPY bad_connected_li1_net |
| } |
| "s_16_X.22" { |
| @ X.22: Nets on li1 is floating |
| COPY floating_li1_net_notie |
| } |
| "s_17_X.22" { |
| @ X.22: Floating li1 marked with li1_tie at chiplevel without connecting |
| COPY floating_li1_net_tie |
| } |
| "s_18_X.22" { |
| @ X.22: Metal on li1 is texted as both tied and floating (Chip level) |
| COPY floating_tie_li1_netTexted_chip |
| } |
| "r_1183_X.22" { |
| @ X.22: Floating li1_float or li1_tie text not over li1 |
| COPY extraneous_li1_floatTextIP |
| } |
| "r_1184_X.22" { |
| @ X.22: li1 marked with li1_float not floating |
| COPY bad_connected_li1_netIP |
| } |
| "r_1185_X.22" { |
| @ X.22: Nets on li1 is floating |
| COPY floating_li1_netIP |
| } |
| "r_1186_X.22" { |
| @ X.22: Metal on li1 is texted as both tied and floating (IP Level) |
| COPY floating_tie_li1_netTexted_IP |
| } |
| floating_met1_net_tmp = NET AREA RATIO met1 OVER pSRCDRN nSRCDRN PTAP NTAP topCell_li1_pin topCell_met1_pin topCell_met2_pin topCell_met3_pin pad_pin topCell_met4_pin topCell_met5_pin topCell_poly_pin GATE == 0 |
| floating_met1_net_no_xmt = floating_met1_net_tmp NOT x22_exempt |
| float_text_met1_extent = EXPAND TEXT "m1_float" BY (0.005 * 2) |
| tie_text_met1_extent = EXPAND TEXT "m1_tie" BY (0.005 * 2) |
| floating_met1_netTexted = (WITH TEXT floating_met1_net_tmp "m1_float" textlabel) NOT x22_exempt |
| tie_met1_netTexted = (WITH TEXT floating_met1_net_tmp "m1_tie" textlabel) NOT x22_exempt |
| floating_tie_met1_netTexted = floating_met1_netTexted AND tie_met1_netTexted |
| floating_met1_netBad = floating_met1_net_no_xmt NOT floating_met1_netTexted |
| floating_met1_net = floating_met1_netBad AND SEALnoHoles_ORIGIN |
| floating_met1_net_tie = floating_met1_net AND tie_met1_netTexted |
| floating_met1_net_notie = floating_met1_net NOT tie_met1_netTexted |
| floating_met1_netIPtmp = floating_met1_netBad NOT SEALnoHoles_ORIGIN |
| floating_met1_netIPtmp2 = floating_met1_netIPtmp NOT tie_met1_netTexted |
| floating_met1_netIPsc = floating_met1_netIPtmp2 INSIDE STDCID |
| floating_met1_netIP = floating_met1_netIPtmp2 NOT floating_met1_netIPsc |
| connected_met1_net_tmp = met1 NOT floating_met1_net_tmp |
| bad_connected_met1_net_tmp = WITH TEXT connected_met1_net_tmp "m1_float" textlabel |
| bad_connected_met1_net = bad_connected_met1_net_tmp AND SEALnoHoles_ORIGIN |
| bad_connected_met1_netIP = bad_connected_met1_net_tmp NOT SEALnoHoles_ORIGIN |
| floating_tie_met1_netTexted_IP = floating_tie_met1_netTexted NOT SEALnoHoles_ORIGIN |
| floating_tie_met1_netTexted_chip = floating_tie_met1_netTexted AND SEALnoHoles_ORIGIN |
| allChipNotmet1tmpm1_float = chip NOT "met1" |
| allChipNotmet1 = allChipNotmet1tmpm1_float AND SEALnoHoles_ORIGIN |
| allChipNotmet1IP = allChipNotmet1tmpm1_float NOT SEALnoHoles_ORIGIN |
| extraneous_m1_floatText = allChipNotmet1 AND (float_text_met1_extent OR tie_text_met1_extent) |
| extraneous_m1_floatTextIP = allChipNotmet1IP AND (float_text_met1_extent OR tie_text_met1_extent) |
| "s_19_X.22" { |
| @ X.22: Floating m1_float or m1_tie text not over met1 |
| COPY extraneous_m1_floatText |
| } |
| "s_20_X.22" { |
| @ X.22: met1 marked with m1_float not floating |
| COPY bad_connected_met1_net |
| } |
| "s_21_X.22" { |
| @ X.22: Nets on met1 is floating |
| COPY floating_met1_net_notie |
| } |
| "s_22_X.22" { |
| @ X.22: Floating met1 marked with m1_tie at chiplevel without connecting |
| COPY floating_met1_net_tie |
| } |
| "s_23_X.22" { |
| @ X.22: Metal on met1 is texted as both tied and floating (Chip level) |
| COPY floating_tie_met1_netTexted_chip |
| } |
| "r_1187_X.22" { |
| @ X.22: Floating m1_float or m1_tie text not over met1 |
| COPY extraneous_m1_floatTextIP |
| } |
| "r_1188_X.22" { |
| @ X.22: met1 marked with m1_float not floating |
| COPY bad_connected_met1_netIP |
| } |
| "r_1189_X.22" { |
| @ X.22: Nets on met1 is floating |
| COPY floating_met1_netIP |
| } |
| "r_1190_X.22" { |
| @ X.22: Metal on met1 is texted as both tied and floating (IP Level) |
| COPY floating_tie_met1_netTexted_IP |
| } |
| floating_met2_net_tmp = NET AREA RATIO met2 OVER pSRCDRN nSRCDRN PTAP NTAP topCell_li1_pin topCell_met1_pin topCell_met2_pin topCell_met3_pin pad_pin topCell_met4_pin topCell_met5_pin topCell_poly_pin GATE == 0 |
| floating_met2_net_no_xmt = floating_met2_net_tmp NOT x22_exempt |
| float_text_met2_extent = EXPAND TEXT "m2_float" BY (0.005 * 2) |
| tie_text_met2_extent = EXPAND TEXT "m2_tie" BY (0.005 * 2) |
| floating_met2_netTexted = (WITH TEXT floating_met2_net_tmp "m2_float" textlabel) NOT x22_exempt |
| tie_met2_netTexted = (WITH TEXT floating_met2_net_tmp "m2_tie" textlabel) NOT x22_exempt |
| floating_tie_met2_netTexted = floating_met2_netTexted AND tie_met2_netTexted |
| floating_met2_netBad = floating_met2_net_no_xmt NOT floating_met2_netTexted |
| floating_met2_net = floating_met2_netBad AND SEALnoHoles_ORIGIN |
| floating_met2_net_tie = floating_met2_net AND tie_met2_netTexted |
| floating_met2_net_notie = floating_met2_net NOT tie_met2_netTexted |
| floating_met2_netIPtmp = floating_met2_netBad NOT SEALnoHoles_ORIGIN |
| floating_met2_netIPtmp2 = floating_met2_netIPtmp NOT tie_met2_netTexted |
| floating_met2_netIPsc = floating_met2_netIPtmp2 INSIDE STDCID |
| floating_met2_netIP = floating_met2_netIPtmp2 NOT floating_met2_netIPsc |
| connected_met2_net_tmp = met2 NOT floating_met2_net_tmp |
| bad_connected_met2_net_tmp = WITH TEXT connected_met2_net_tmp "m2_float" textlabel |
| bad_connected_met2_net = bad_connected_met2_net_tmp AND SEALnoHoles_ORIGIN |
| bad_connected_met2_netIP = bad_connected_met2_net_tmp NOT SEALnoHoles_ORIGIN |
| floating_tie_met2_netTexted_IP = floating_tie_met2_netTexted NOT SEALnoHoles_ORIGIN |
| floating_tie_met2_netTexted_chip = floating_tie_met2_netTexted AND SEALnoHoles_ORIGIN |
| allChipNotmet2tmpm2_float = chip NOT "met2" |
| allChipNotmet2 = allChipNotmet2tmpm2_float AND SEALnoHoles_ORIGIN |
| allChipNotmet2IP = allChipNotmet2tmpm2_float NOT SEALnoHoles_ORIGIN |
| extraneous_m2_floatText = allChipNotmet2 AND (float_text_met2_extent OR tie_text_met2_extent) |
| extraneous_m2_floatTextIP = allChipNotmet2IP AND (float_text_met2_extent OR tie_text_met2_extent) |
| "s_24_X.22" { |
| @ X.22: Floating m2_float or m2_tie text not over met2 |
| COPY extraneous_m2_floatText |
| } |
| "s_25_X.22" { |
| @ X.22: met2 marked with m2_float not floating |
| COPY bad_connected_met2_net |
| } |
| "s_26_X.22" { |
| @ X.22: Nets on met2 is floating |
| COPY floating_met2_net_notie |
| } |
| "s_27_X.22" { |
| @ X.22: Floating met2 marked with m2_tie at chiplevel without connecting |
| COPY floating_met2_net_tie |
| } |
| "s_28_X.22" { |
| @ X.22: Metal on met2 is texted as both tied and floating (Chip level) |
| COPY floating_tie_met2_netTexted_chip |
| } |
| "r_1191_X.22" { |
| @ X.22: Floating m2_float or m2_tie text not over met2 |
| COPY extraneous_m2_floatTextIP |
| } |
| "r_1192_X.22" { |
| @ X.22: met2 marked with m2_float not floating |
| COPY bad_connected_met2_netIP |
| } |
| "r_1193_X.22" { |
| @ X.22: Nets on met2 is floating |
| COPY floating_met2_netIP |
| } |
| "r_1194_X.22" { |
| @ X.22: Metal on met2 is texted as both tied and floating (IP Level) |
| COPY floating_tie_met2_netTexted_IP |
| } |
| floating_met3_net_tmp = NET AREA RATIO met3 OVER pSRCDRN nSRCDRN PTAP NTAP topCell_li1_pin topCell_met1_pin topCell_met2_pin topCell_met3_pin pad_pin topCell_met4_pin topCell_met5_pin topCell_poly_pin GATE == 0 |
| floating_met3_net_no_xmt = floating_met3_net_tmp NOT x22_exempt |
| float_text_met3_extent = EXPAND TEXT "m3_float" BY (0.005 * 2) |
| tie_text_met3_extent = EXPAND TEXT "m3_tie" BY (0.005 * 2) |
| floating_met3_netTexted = (WITH TEXT floating_met3_net_tmp "m3_float" textlabel) NOT x22_exempt |
| tie_met3_netTexted = (WITH TEXT floating_met3_net_tmp "m3_tie" textlabel) NOT x22_exempt |
| floating_tie_met3_netTexted = floating_met3_netTexted AND tie_met3_netTexted |
| floating_met3_netBad = floating_met3_net_no_xmt NOT floating_met3_netTexted |
| floating_met3_net = floating_met3_netBad AND SEALnoHoles_ORIGIN |
| floating_met3_net_tie = floating_met3_net AND tie_met3_netTexted |
| floating_met3_net_notie = floating_met3_net NOT tie_met3_netTexted |
| floating_met3_netIPtmp = floating_met3_netBad NOT SEALnoHoles_ORIGIN |
| floating_met3_netIPtmp2 = floating_met3_netIPtmp NOT tie_met3_netTexted |
| floating_met3_netIPsc = floating_met3_netIPtmp2 INSIDE STDCID |
| floating_met3_netIP = floating_met3_netIPtmp2 NOT floating_met3_netIPsc |
| connected_met3_net_tmp = met3 NOT floating_met3_net_tmp |
| bad_connected_met3_net_tmp = WITH TEXT connected_met3_net_tmp "m3_float" textlabel |
| bad_connected_met3_net = bad_connected_met3_net_tmp AND SEALnoHoles_ORIGIN |
| bad_connected_met3_netIP = bad_connected_met3_net_tmp NOT SEALnoHoles_ORIGIN |
| floating_tie_met3_netTexted_IP = floating_tie_met3_netTexted NOT SEALnoHoles_ORIGIN |
| floating_tie_met3_netTexted_chip = floating_tie_met3_netTexted AND SEALnoHoles_ORIGIN |
| allChipNotmet3tmpm3_float = chip NOT "met3" |
| allChipNotmet3 = allChipNotmet3tmpm3_float AND SEALnoHoles_ORIGIN |
| allChipNotmet3IP = allChipNotmet3tmpm3_float NOT SEALnoHoles_ORIGIN |
| extraneous_m3_floatText = allChipNotmet3 AND (float_text_met3_extent OR tie_text_met3_extent) |
| extraneous_m3_floatTextIP = allChipNotmet3IP AND (float_text_met3_extent OR tie_text_met3_extent) |
| "s_29_X.22" { |
| @ X.22: Floating m3_float or m3_tie text not over met3 |
| COPY extraneous_m3_floatText |
| } |
| "s_30_X.22" { |
| @ X.22: met3 marked with m3_float not floating |
| COPY bad_connected_met3_net |
| } |
| "s_31_X.22" { |
| @ X.22: Nets on met3 is floating |
| COPY floating_met3_net_notie |
| } |
| "s_32_X.22" { |
| @ X.22: Floating met3 marked with m3_tie at chiplevel without connecting |
| COPY floating_met3_net_tie |
| } |
| "s_33_X.22" { |
| @ X.22: Metal on met3 is texted as both tied and floating (Chip level) |
| COPY floating_tie_met3_netTexted_chip |
| } |
| "r_1195_X.22" { |
| @ X.22: Floating m3_float or m3_tie text not over met3 |
| COPY extraneous_m3_floatTextIP |
| } |
| "r_1196_X.22" { |
| @ X.22: met3 marked with m3_float not floating |
| COPY bad_connected_met3_netIP |
| } |
| "r_1197_X.22" { |
| @ X.22: Nets on met3 is floating |
| COPY floating_met3_netIP |
| } |
| "r_1198_X.22" { |
| @ X.22: Metal on met3 is texted as both tied and floating (IP Level) |
| COPY floating_tie_met3_netTexted_IP |
| } |
| floating_met4_net_tmp = NET AREA RATIO met4 OVER pSRCDRN nSRCDRN PTAP NTAP topCell_li1_pin topCell_met1_pin topCell_met2_pin topCell_met3_pin pad_pin topCell_met4_pin topCell_met5_pin topCell_poly_pin GATE == 0 |
| floating_met4_net_no_xmt = floating_met4_net_tmp NOT x22_exempt |
| float_text_met4_extent = EXPAND TEXT "m4_float" BY (0.005 * 2) |
| tie_text_met4_extent = EXPAND TEXT "m4_tie" BY (0.005 * 2) |
| floating_met4_netTexted = (WITH TEXT floating_met4_net_tmp "m4_float" textlabel) NOT x22_exempt |
| tie_met4_netTexted = (WITH TEXT floating_met4_net_tmp "m4_tie" textlabel) NOT x22_exempt |
| floating_tie_met4_netTexted = floating_met4_netTexted AND tie_met4_netTexted |
| floating_met4_netBad = floating_met4_net_no_xmt NOT floating_met4_netTexted |
| floating_met4_net = floating_met4_netBad AND SEALnoHoles_ORIGIN |
| floating_met4_net_tie = floating_met4_net AND tie_met4_netTexted |
| floating_met4_net_notie = floating_met4_net NOT tie_met4_netTexted |
| floating_met4_netIPtmp = floating_met4_netBad NOT SEALnoHoles_ORIGIN |
| floating_met4_netIPtmp2 = floating_met4_netIPtmp NOT tie_met4_netTexted |
| floating_met4_netIPsc = floating_met4_netIPtmp2 INSIDE STDCID |
| floating_met4_netIP = floating_met4_netIPtmp2 NOT floating_met4_netIPsc |
| connected_met4_net_tmp = met4 NOT floating_met4_net_tmp |
| bad_connected_met4_net_tmp = WITH TEXT connected_met4_net_tmp "m4_float" textlabel |
| bad_connected_met4_net = bad_connected_met4_net_tmp AND SEALnoHoles_ORIGIN |
| bad_connected_met4_netIP = bad_connected_met4_net_tmp NOT SEALnoHoles_ORIGIN |
| floating_tie_met4_netTexted_IP = floating_tie_met4_netTexted NOT SEALnoHoles_ORIGIN |
| floating_tie_met4_netTexted_chip = floating_tie_met4_netTexted AND SEALnoHoles_ORIGIN |
| allChipNotmet4tmpm4_float = chip NOT "met4" |
| allChipNotmet4 = allChipNotmet4tmpm4_float AND SEALnoHoles_ORIGIN |
| allChipNotmet4IP = allChipNotmet4tmpm4_float NOT SEALnoHoles_ORIGIN |
| extraneous_m4_floatText = allChipNotmet4 AND (float_text_met4_extent OR tie_text_met4_extent) |
| extraneous_m4_floatTextIP = allChipNotmet4IP AND (float_text_met4_extent OR tie_text_met4_extent) |
| "s_34_X.22" { |
| @ X.22: Floating m4_float or m4_tie text not over met4 |
| COPY extraneous_m4_floatText |
| } |
| "s_35_X.22" { |
| @ X.22: met4 marked with m4_float not floating |
| COPY bad_connected_met4_net |
| } |
| "s_36_X.22" { |
| @ X.22: Nets on met4 is floating |
| COPY floating_met4_net_notie |
| } |
| "s_37_X.22" { |
| @ X.22: Floating met4 marked with m4_tie at chiplevel without connecting |
| COPY floating_met4_net_tie |
| } |
| "s_38_X.22" { |
| @ X.22: Metal on met4 is texted as both tied and floating (Chip level) |
| COPY floating_tie_met4_netTexted_chip |
| } |
| "r_1199_X.22" { |
| @ X.22: Floating m4_float or m4_tie text not over met4 |
| COPY extraneous_m4_floatTextIP |
| } |
| "r_1200_X.22" { |
| @ X.22: met4 marked with m4_float not floating |
| COPY bad_connected_met4_netIP |
| } |
| "r_1201_X.22" { |
| @ X.22: Nets on met4 is floating |
| COPY floating_met4_netIP |
| } |
| "r_1202_X.22" { |
| @ X.22: Metal on met4 is texted as both tied and floating (IP Level) |
| COPY floating_tie_met4_netTexted_IP |
| } |
| floating_met5_net_tmp = NET AREA RATIO met5 OVER pSRCDRN nSRCDRN PTAP NTAP topCell_li1_pin topCell_met1_pin topCell_met2_pin topCell_met3_pin pad_pin topCell_met4_pin topCell_met5_pin topCell_poly_pin GATE == 0 |
| floating_met5_net_no_xmt = floating_met5_net_tmp NOT x22_exempt |
| float_text_met5_extent = EXPAND TEXT "m5_float" BY (0.005 * 2) |
| tie_text_met5_extent = EXPAND TEXT "m5_tie" BY (0.005 * 2) |
| floating_met5_netTexted = (WITH TEXT floating_met5_net_tmp "m5_float" textlabel) NOT x22_exempt |
| tie_met5_netTexted = (WITH TEXT floating_met5_net_tmp "m5_tie" textlabel) NOT x22_exempt |
| floating_tie_met5_netTexted = floating_met5_netTexted AND tie_met5_netTexted |
| floating_met5_netBad = floating_met5_net_no_xmt NOT floating_met5_netTexted |
| floating_met5_net = floating_met5_netBad AND SEALnoHoles_ORIGIN |
| floating_met5_net_tie = floating_met5_net AND tie_met5_netTexted |
| floating_met5_net_notie = floating_met5_net NOT tie_met5_netTexted |
| floating_met5_netIPtmp = floating_met5_netBad NOT SEALnoHoles_ORIGIN |
| floating_met5_netIPtmp2 = floating_met5_netIPtmp NOT tie_met5_netTexted |
| floating_met5_netIPsc = floating_met5_netIPtmp2 INSIDE STDCID |
| floating_met5_netIP = floating_met5_netIPtmp2 NOT floating_met5_netIPsc |
| connected_met5_net_tmp = met5 NOT floating_met5_net_tmp |
| bad_connected_met5_net_tmp = WITH TEXT connected_met5_net_tmp "m5_float" textlabel |
| bad_connected_met5_net = bad_connected_met5_net_tmp AND SEALnoHoles_ORIGIN |
| bad_connected_met5_netIP = bad_connected_met5_net_tmp NOT SEALnoHoles_ORIGIN |
| floating_tie_met5_netTexted_IP = floating_tie_met5_netTexted NOT SEALnoHoles_ORIGIN |
| floating_tie_met5_netTexted_chip = floating_tie_met5_netTexted AND SEALnoHoles_ORIGIN |
| allChipNotmet5tmpm5_float = chip NOT "met5" |
| allChipNotmet5 = allChipNotmet5tmpm5_float AND SEALnoHoles_ORIGIN |
| allChipNotmet5IP = allChipNotmet5tmpm5_float NOT SEALnoHoles_ORIGIN |
| extraneous_m5_floatText = allChipNotmet5 AND (float_text_met5_extent OR tie_text_met5_extent) |
| extraneous_m5_floatTextIP = allChipNotmet5IP AND (float_text_met5_extent OR tie_text_met5_extent) |
| "s_39_X.22" { |
| @ X.22: Floating m5_float or m5_tie text not over met5 |
| COPY extraneous_m5_floatText |
| } |
| "s_40_X.22" { |
| @ X.22: met5 marked with m5_float not floating |
| COPY bad_connected_met5_net |
| } |
| "s_41_X.22" { |
| @ X.22: Nets on met5 is floating |
| COPY floating_met5_net_notie |
| } |
| "s_42_X.22" { |
| @ X.22: Floating met5 marked with m5_tie at chiplevel without connecting |
| COPY floating_met5_net_tie |
| } |
| "s_43_X.22" { |
| @ X.22: Metal on met5 is texted as both tied and floating (Chip level) |
| COPY floating_tie_met5_netTexted_chip |
| } |
| "r_1203_X.22" { |
| @ X.22: Floating m5_float or m5_tie text not over met5 |
| COPY extraneous_m5_floatTextIP |
| } |
| "r_1204_X.22" { |
| @ X.22: met5 marked with m5_float not floating |
| COPY bad_connected_met5_netIP |
| } |
| "r_1205_X.22" { |
| @ X.22: Nets on met5 is floating |
| COPY floating_met5_netIP |
| } |
| "r_1206_X.22" { |
| @ X.22: Metal on met5 is texted as both tied and floating (IP Level) |
| COPY floating_tie_met5_netTexted_IP |
| } |
| isoPwellCondiode = dnwell NOT nwell |
| condiode = EXPAND TEXT condiode textdraw BY 0.001 |
| badCondiode = SIZE (condiode NOT isoPwellCondiode) BY 0.005 |
| "r_1207_X.24" { |
| @ X.24: condiode label must be in isolated pwell |
| COPY badCondiode |
| } |
| floatM1Shield = met1Shield AND floating_met1_net |
| met1ShieldConMet = met1 AND met1Shield |
| met1ShieldConPad = met1Shield AND (NET AREA RATIO met1ShieldConMet pad_pin > 0) |
| "r_1208_pad.20" { |
| @ pad.20: met1 shielding pad, must not float |
| COPY floatM1Shield |
| } |
| "r_1209_pad.20" { |
| @ pad.20: met1 shielding pad, must not connected to pad |
| COPY met1ShieldConPad |
| } |
| chipAreaBigEnough = AREA chip > 40000.0 |
| entireChipForDensity = INTERACT chip sealHoles |
| MM1outOxide_drc = SIZE met1 BY 0.6 |
| waffle1DropDensity70 = DENSITY cmm1WaffleDrop == 1.0 WINDOW 700 STEP 70 |
| mm1DensityUnder70 = DENSITY MM1outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity70 RDB mm1_70_window_700_err.rdb |
| mm1DensityUnder70Chip = INTERACT mm1DensityUnder70 entireChipForDensity |
| mm1DensityUnder70tmp = mm1DensityUnder70 NOT mm1DensityUnder70Chip |
| mm1DensityUnder70IP = mm1DensityUnder70tmp AND chipAreaBigEnough |
| "r_1210_m1.x.1" { |
| @ m1.x.1: <70% metal density when 700x700 window 100% covered by mm1.waffledrop |
| COPY mm1DensityUnder70IP |
| } |
| "s_44_m1.x.1" { |
| @ m1.x.1: <70% metal density when 700x700 window 100% covered by mm1.waffledrop |
| COPY mm1DensityUnder70Chip |
| } |
| waffle1DropDensity65 = DENSITY cmm1WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70 |
| mm1DensityUnder65 = DENSITY MM1outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity65 RDB mm1_65_window_700_err.rdb |
| mm1DensityUnder65Chip = INTERACT mm1DensityUnder65 entireChipForDensity |
| mm1DensityUnder65tmp = mm1DensityUnder65 NOT mm1DensityUnder65Chip |
| mm1DensityUnder65IP = mm1DensityUnder65tmp AND chipAreaBigEnough |
| "r_1211_m1.x.1" { |
| @ m1.x.1: <65% metal density when 700x700 window 80-100% covered by mm1.waffledrop |
| COPY mm1DensityUnder65IP |
| } |
| "s_45_m1.x.1" { |
| @ m1.x.1: <65% metal density when 700x700 window 80-100% covered by mm1.waffledrop |
| COPY mm1DensityUnder65Chip |
| } |
| waffle1DropDensity60 = DENSITY cmm1WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70 |
| mm1DensityUnder60 = DENSITY MM1outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity60 RDB mm1_60_window_700_err.rdb |
| mm1DensityUnder60Chip = INTERACT mm1DensityUnder60 entireChipForDensity |
| mm1DensityUnder60tmp = mm1DensityUnder60 NOT mm1DensityUnder60Chip |
| mm1DensityUnder60IP = mm1DensityUnder60tmp AND chipAreaBigEnough |
| "r_1212_m1.x.1" { |
| @ m1.x.1: <60% metal density when 700x700 window 60-80% covered by mm1.waffledrop |
| COPY mm1DensityUnder60IP |
| } |
| "s_46_m1.x.1" { |
| @ m1.x.1: <60% metal density when 700x700 window 60-80% covered by mm1.waffledrop |
| COPY mm1DensityUnder60Chip |
| } |
| waffle1DropDensity50 = DENSITY cmm1WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70 |
| mm1DensityUnder50 = DENSITY MM1outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity50 RDB mm1_50_window_700_err.rdb |
| mm1DensityUnder50Chip = INTERACT mm1DensityUnder50 entireChipForDensity |
| mm1DensityUnder50tmp = mm1DensityUnder50 NOT mm1DensityUnder50Chip |
| mm1DensityUnder50IP = mm1DensityUnder50tmp AND chipAreaBigEnough |
| "r_1213_m1.x.1" { |
| @ m1.x.1: <50% metal density when 700x700 window 50-60% covered by mm1.waffledrop |
| COPY mm1DensityUnder50IP |
| } |
| "s_47_m1.x.1" { |
| @ m1.x.1: <50% metal density when 700x700 window 50-60% covered by mm1.waffledrop |
| COPY mm1DensityUnder50Chip |
| } |
| waffle1DropDensity40 = DENSITY cmm1WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70 |
| mm1DensityUnder40 = DENSITY MM1outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity40 RDB mm1_40_window_700_err.rdb |
| mm1DensityUnder40Chip = INTERACT mm1DensityUnder40 entireChipForDensity |
| mm1DensityUnder40tmp = mm1DensityUnder40 NOT mm1DensityUnder40Chip |
| mm1DensityUnder40IP = mm1DensityUnder40tmp AND chipAreaBigEnough |
| "r_1214_m1.x.1" { |
| @ m1.x.1: <40% metal density when 700x700 window 40-50% covered by mm1.waffledrop |
| COPY mm1DensityUnder40IP |
| } |
| "s_48_m1.x.1" { |
| @ m1.x.1: <40% metal density when 700x700 window 40-50% covered by mm1.waffledrop |
| COPY mm1DensityUnder40Chip |
| } |
| waffle1DropDensity30 = DENSITY cmm1WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70 |
| mm1DensityUnder30 = DENSITY MM1outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity30 RDB mm1_30_window_700_err.rdb |
| mm1DensityUnder30Chip = INTERACT mm1DensityUnder30 entireChipForDensity |
| mm1DensityUnder30tmp = mm1DensityUnder30 NOT mm1DensityUnder30Chip |
| mm1DensityUnder30IP = mm1DensityUnder30tmp AND chipAreaBigEnough |
| "r_1215_m1.x.1" { |
| @ m1.x.1: <30% metal density when 700x700 window 30-40% covered by mm1.waffledrop |
| COPY mm1DensityUnder30IP |
| } |
| "s_49_m1.x.1" { |
| @ m1.x.1: <30% metal density when 700x700 window 30-40% covered by mm1.waffledrop |
| COPY mm1DensityUnder30Chip |
| } |
| MM2outOxide_drc = SIZE met2 BY 0.6 |
| waffle2DropDensity70 = DENSITY cmm2WaffleDrop == 1.0 WINDOW 700 STEP 70 |
| mm2DensityUnder70 = DENSITY MM2outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle2DropDensity70 RDB mm2_70_window_700_err.rdb |
| mm2DensityUnder70Chip = INTERACT mm2DensityUnder70 entireChipForDensity |
| mm2DensityUnder70tmp = mm2DensityUnder70 NOT mm2DensityUnder70Chip |
| mm2DensityUnder70IP = mm2DensityUnder70tmp AND chipAreaBigEnough |
| "r_1216_m2.x.1" { |
| @ m2.x.1: <70% metal density when 700x700 window 100% covered by mm2.waffledrop |
| COPY mm2DensityUnder70IP |
| } |
| "s_50_m2.x.1" { |
| @ m2.x.1: <70% metal density when 700x700 window 100% covered by mm2.waffledrop |
| COPY mm2DensityUnder70Chip |
| } |
| waffle2DropDensity65 = DENSITY cmm2WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70 |
| mm2DensityUnder65 = DENSITY MM2outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle2DropDensity65 RDB mm2_65_window_700_err.rdb |
| mm2DensityUnder65Chip = INTERACT mm2DensityUnder65 entireChipForDensity |
| mm2DensityUnder65tmp = mm2DensityUnder65 NOT mm2DensityUnder65Chip |
| mm2DensityUnder65IP = mm2DensityUnder65tmp AND chipAreaBigEnough |
| "r_1217_m2.x.1" { |
| @ m2.x.1: <65% metal density when 700x700 window 80-100% covered by mm2.waffledrop |
| COPY mm2DensityUnder65IP |
| } |
| "s_51_m2.x.1" { |
| @ m2.x.1: <65% metal density when 700x700 window 80-100% covered by mm2.waffledrop |
| COPY mm2DensityUnder65Chip |
| } |
| waffle2DropDensity60 = DENSITY cmm2WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70 |
| mm2DensityUnder60 = DENSITY MM2outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle2DropDensity60 RDB mm2_60_window_700_err.rdb |
| mm2DensityUnder60Chip = INTERACT mm2DensityUnder60 entireChipForDensity |
| mm2DensityUnder60tmp = mm2DensityUnder60 NOT mm2DensityUnder60Chip |
| mm2DensityUnder60IP = mm2DensityUnder60tmp AND chipAreaBigEnough |
| "r_1218_m2.x.1" { |
| @ m2.x.1: <60% metal density when 700x700 window 60-80% covered by mm2.waffledrop |
| COPY mm2DensityUnder60IP |
| } |
| "s_52_m2.x.1" { |
| @ m2.x.1: <60% metal density when 700x700 window 60-80% covered by mm2.waffledrop |
| COPY mm2DensityUnder60Chip |
| } |
| waffle2DropDensity50 = DENSITY cmm2WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70 |
| mm2DensityUnder50 = DENSITY MM2outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle2DropDensity50 RDB mm2_50_window_700_err.rdb |
| mm2DensityUnder50Chip = INTERACT mm2DensityUnder50 entireChipForDensity |
| mm2DensityUnder50tmp = mm2DensityUnder50 NOT mm2DensityUnder50Chip |
| mm2DensityUnder50IP = mm2DensityUnder50tmp AND chipAreaBigEnough |
| "r_1219_m2.x.1" { |
| @ m2.x.1: <50% metal density when 700x700 window 50-60% covered by mm2.waffledrop |
| COPY mm2DensityUnder50IP |
| } |
| "s_53_m2.x.1" { |
| @ m2.x.1: <50% metal density when 700x700 window 50-60% covered by mm2.waffledrop |
| COPY mm2DensityUnder50Chip |
| } |
| waffle2DropDensity40 = DENSITY cmm2WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70 |
| mm2DensityUnder40 = DENSITY MM2outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle2DropDensity40 RDB mm2_40_window_700_err.rdb |
| mm2DensityUnder40Chip = INTERACT mm2DensityUnder40 entireChipForDensity |
| mm2DensityUnder40tmp = mm2DensityUnder40 NOT mm2DensityUnder40Chip |
| mm2DensityUnder40IP = mm2DensityUnder40tmp AND chipAreaBigEnough |
| "r_1220_m2.x.1" { |
| @ m2.x.1: <40% metal density when 700x700 window 40-50% covered by mm2.waffledrop |
| COPY mm2DensityUnder40IP |
| } |
| "s_54_m2.x.1" { |
| @ m2.x.1: <40% metal density when 700x700 window 40-50% covered by mm2.waffledrop |
| COPY mm2DensityUnder40Chip |
| } |
| waffle2DropDensity30 = DENSITY cmm2WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70 |
| mm2DensityUnder30 = DENSITY MM2outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle2DropDensity30 RDB mm2_30_window_700_err.rdb |
| mm2DensityUnder30Chip = INTERACT mm2DensityUnder30 entireChipForDensity |
| mm2DensityUnder30tmp = mm2DensityUnder30 NOT mm2DensityUnder30Chip |
| mm2DensityUnder30IP = mm2DensityUnder30tmp AND chipAreaBigEnough |
| "r_1221_m2.x.1" { |
| @ m2.x.1: <30% metal density when 700x700 window 30-40% covered by mm2.waffledrop |
| COPY mm2DensityUnder30IP |
| } |
| "s_55_m2.x.1" { |
| @ m2.x.1: <30% metal density when 700x700 window 30-40% covered by mm2.waffledrop |
| COPY mm2DensityUnder30Chip |
| } |
| MM3outOxide_drc = SIZE met3 BY 1.15 |
| waffle3DropDensity70 = DENSITY cmm3WaffleDrop == 1.0 WINDOW 700 STEP 70 |
| mm3DensityUnder70 = DENSITY MM3outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle3DropDensity70 RDB mm3_70_window_700_err.rdb |
| mm3DensityUnder70Chip = INTERACT mm3DensityUnder70 entireChipForDensity |
| mm3DensityUnder70tmp = mm3DensityUnder70 NOT mm3DensityUnder70Chip |
| mm3DensityUnder70IP = mm3DensityUnder70tmp AND chipAreaBigEnough |
| "r_1222_m3.x.1" { |
| @ m3.x.1: <70% metal density when 700x700 window 100% covered by mm3.waffledrop |
| COPY mm3DensityUnder70IP |
| } |
| "s_56_m3.x.1" { |
| @ m3.x.1: <70% metal density when 700x700 window 100% covered by mm3.waffledrop |
| COPY mm3DensityUnder70Chip |
| } |
| waffle3DropDensity65 = DENSITY cmm3WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70 |
| mm3DensityUnder65 = DENSITY MM3outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle3DropDensity65 RDB mm3_65_window_700_err.rdb |
| mm3DensityUnder65Chip = INTERACT mm3DensityUnder65 entireChipForDensity |
| mm3DensityUnder65tmp = mm3DensityUnder65 NOT mm3DensityUnder65Chip |
| mm3DensityUnder65IP = mm3DensityUnder65tmp AND chipAreaBigEnough |
| "r_1223_m3.x.1" { |
| @ m3.x.1: <65% metal density when 700x700 window 80-100% covered by mm3.waffledrop |
| COPY mm3DensityUnder65IP |
| } |
| "s_57_m3.x.1" { |
| @ m3.x.1: <65% metal density when 700x700 window 80-100% covered by mm3.waffledrop |
| COPY mm3DensityUnder65Chip |
| } |
| waffle3DropDensity60 = DENSITY cmm3WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70 |
| mm3DensityUnder60 = DENSITY MM3outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle3DropDensity60 RDB mm3_60_window_700_err.rdb |
| mm3DensityUnder60Chip = INTERACT mm3DensityUnder60 entireChipForDensity |
| mm3DensityUnder60tmp = mm3DensityUnder60 NOT mm3DensityUnder60Chip |
| mm3DensityUnder60IP = mm3DensityUnder60tmp AND chipAreaBigEnough |
| "r_1224_m3.x.1" { |
| @ m3.x.1: <60% metal density when 700x700 window 60-80% covered by mm3.waffledrop |
| COPY mm3DensityUnder60IP |
| } |
| "s_58_m3.x.1" { |
| @ m3.x.1: <60% metal density when 700x700 window 60-80% covered by mm3.waffledrop |
| COPY mm3DensityUnder60Chip |
| } |
| waffle3DropDensity50 = DENSITY cmm3WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70 |
| mm3DensityUnder50 = DENSITY MM3outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle3DropDensity50 RDB mm3_50_window_700_err.rdb |
| mm3DensityUnder50Chip = INTERACT mm3DensityUnder50 entireChipForDensity |
| mm3DensityUnder50tmp = mm3DensityUnder50 NOT mm3DensityUnder50Chip |
| mm3DensityUnder50IP = mm3DensityUnder50tmp AND chipAreaBigEnough |
| "r_1225_m3.x.1" { |
| @ m3.x.1: <50% metal density when 700x700 window 50-60% covered by mm3.waffledrop |
| COPY mm3DensityUnder50IP |
| } |
| "s_59_m3.x.1" { |
| @ m3.x.1: <50% metal density when 700x700 window 50-60% covered by mm3.waffledrop |
| COPY mm3DensityUnder50Chip |
| } |
| waffle3DropDensity40 = DENSITY cmm3WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70 |
| mm3DensityUnder40 = DENSITY MM3outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle3DropDensity40 RDB mm3_40_window_700_err.rdb |
| mm3DensityUnder40Chip = INTERACT mm3DensityUnder40 entireChipForDensity |
| mm3DensityUnder40tmp = mm3DensityUnder40 NOT mm3DensityUnder40Chip |
| mm3DensityUnder40IP = mm3DensityUnder40tmp AND chipAreaBigEnough |
| "r_1226_m3.x.1" { |
| @ m3.x.1: <40% metal density when 700x700 window 40-50% covered by mm3.waffledrop |
| COPY mm3DensityUnder40IP |
| } |
| "s_60_m3.x.1" { |
| @ m3.x.1: <40% metal density when 700x700 window 40-50% covered by mm3.waffledrop |
| COPY mm3DensityUnder40Chip |
| } |
| waffle3DropDensity30 = DENSITY cmm3WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70 |
| mm3DensityUnder30 = DENSITY MM3outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle3DropDensity30 RDB mm3_30_window_700_err.rdb |
| mm3DensityUnder30Chip = INTERACT mm3DensityUnder30 entireChipForDensity |
| mm3DensityUnder30tmp = mm3DensityUnder30 NOT mm3DensityUnder30Chip |
| mm3DensityUnder30IP = mm3DensityUnder30tmp AND chipAreaBigEnough |
| "r_1227_m3.x.1" { |
| @ m3.x.1: <30% metal density when 700x700 window 30-40% covered by mm3.waffledrop |
| COPY mm3DensityUnder30IP |
| } |
| "s_61_m3.x.1" { |
| @ m3.x.1: <30% metal density when 700x700 window 30-40% covered by mm3.waffledrop |
| COPY mm3DensityUnder30Chip |
| } |
| MM4outOxide_drc = SIZE met4 BY 1.15 |
| waffle4DropDensity70 = DENSITY cmm4WaffleDrop == 1.0 WINDOW 700 STEP 70 |
| mm4DensityUnder70 = DENSITY MM4outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle4DropDensity70 RDB mm4_70_window_700_err.rdb |
| mm4DensityUnder70Chip = INTERACT mm4DensityUnder70 entireChipForDensity |
| mm4DensityUnder70tmp = mm4DensityUnder70 NOT mm4DensityUnder70Chip |
| mm4DensityUnder70IP = mm4DensityUnder70tmp AND chipAreaBigEnough |
| "r_1228_m4.x.1" { |
| @ m4.x.1: <70% metal density when 700x700 window 100% covered by mm4.waffledrop |
| COPY mm4DensityUnder70IP |
| } |
| "s_62_m4.x.1" { |
| @ m4.x.1: <70% metal density when 700x700 window 100% covered by mm4.waffledrop |
| COPY mm4DensityUnder70Chip |
| } |
| waffle4DropDensity65 = DENSITY cmm4WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70 |
| mm4DensityUnder65 = DENSITY MM4outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle4DropDensity65 RDB mm4_65_window_700_err.rdb |
| mm4DensityUnder65Chip = INTERACT mm4DensityUnder65 entireChipForDensity |
| mm4DensityUnder65tmp = mm4DensityUnder65 NOT mm4DensityUnder65Chip |
| mm4DensityUnder65IP = mm4DensityUnder65tmp AND chipAreaBigEnough |
| "r_1229_m4.x.1" { |
| @ m4.x.1: <65% metal density when 700x700 window 80-100% covered by mm4.waffledrop |
| COPY mm4DensityUnder65IP |
| } |
| "s_63_m4.x.1" { |
| @ m4.x.1: <65% metal density when 700x700 window 80-100% covered by mm4.waffledrop |
| COPY mm4DensityUnder65Chip |
| } |
| waffle4DropDensity60 = DENSITY cmm4WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70 |
| mm4DensityUnder60 = DENSITY MM4outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle4DropDensity60 RDB mm4_60_window_700_err.rdb |
| mm4DensityUnder60Chip = INTERACT mm4DensityUnder60 entireChipForDensity |
| mm4DensityUnder60tmp = mm4DensityUnder60 NOT mm4DensityUnder60Chip |
| mm4DensityUnder60IP = mm4DensityUnder60tmp AND chipAreaBigEnough |
| "r_1230_m4.x.1" { |
| @ m4.x.1: <60% metal density when 700x700 window 60-80% covered by mm4.waffledrop |
| COPY mm4DensityUnder60IP |
| } |
| "s_64_m4.x.1" { |
| @ m4.x.1: <60% metal density when 700x700 window 60-80% covered by mm4.waffledrop |
| COPY mm4DensityUnder60Chip |
| } |
| waffle4DropDensity50 = DENSITY cmm4WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70 |
| mm4DensityUnder50 = DENSITY MM4outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle4DropDensity50 RDB mm4_50_window_700_err.rdb |
| mm4DensityUnder50Chip = INTERACT mm4DensityUnder50 entireChipForDensity |
| mm4DensityUnder50tmp = mm4DensityUnder50 NOT mm4DensityUnder50Chip |
| mm4DensityUnder50IP = mm4DensityUnder50tmp AND chipAreaBigEnough |
| "r_1231_m4.x.1" { |
| @ m4.x.1: <50% metal density when 700x700 window 50-60% covered by mm4.waffledrop |
| COPY mm4DensityUnder50IP |
| } |
| "s_65_m4.x.1" { |
| @ m4.x.1: <50% metal density when 700x700 window 50-60% covered by mm4.waffledrop |
| COPY mm4DensityUnder50Chip |
| } |
| waffle4DropDensity40 = DENSITY cmm4WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70 |
| mm4DensityUnder40 = DENSITY MM4outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle4DropDensity40 RDB mm4_40_window_700_err.rdb |
| mm4DensityUnder40Chip = INTERACT mm4DensityUnder40 entireChipForDensity |
| mm4DensityUnder40tmp = mm4DensityUnder40 NOT mm4DensityUnder40Chip |
| mm4DensityUnder40IP = mm4DensityUnder40tmp AND chipAreaBigEnough |
| "r_1232_m4.x.1" { |
| @ m4.x.1: <40% metal density when 700x700 window 40-50% covered by mm4.waffledrop |
| COPY mm4DensityUnder40IP |
| } |
| "s_66_m4.x.1" { |
| @ m4.x.1: <40% metal density when 700x700 window 40-50% covered by mm4.waffledrop |
| COPY mm4DensityUnder40Chip |
| } |
| waffle4DropDensity30 = DENSITY cmm4WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70 |
| mm4DensityUnder30 = DENSITY MM4outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle4DropDensity30 RDB mm4_30_window_700_err.rdb |
| mm4DensityUnder30Chip = INTERACT mm4DensityUnder30 entireChipForDensity |
| mm4DensityUnder30tmp = mm4DensityUnder30 NOT mm4DensityUnder30Chip |
| mm4DensityUnder30IP = mm4DensityUnder30tmp AND chipAreaBigEnough |
| "r_1233_m4.x.1" { |
| @ m4.x.1: <30% metal density when 700x700 window 30-40% covered by mm4.waffledrop |
| COPY mm4DensityUnder30IP |
| } |
| "s_67_m4.x.1" { |
| @ m4.x.1: <30% metal density when 700x700 window 30-40% covered by mm4.waffledrop |
| COPY mm4DensityUnder30Chip |
| } |
| met1Routing = SIZE met1pin BY 0.07 INSIDE OF met1 STEP 0.095 |
| "r_1234_metblk.1" { |
| @ metblk.1: 0.14 min. spacing of met1 & met1Block |
| EXTERNAL met1 met1Block < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1235_metblk.1" { |
| @ metblk.1: met1 must not overlap met1Block |
| met1 AND met1Block |
| } |
| "r_1236_metblk.3" { |
| @ metblk.3: 0.145 min. spacing of met1Block & met1Routing |
| EXTERNAL met1Block met1Routing < 0.145 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met2Routing = SIZE met2pin BY 0.07 INSIDE OF met2 STEP 0.095 |
| "r_1237_metblk.1" { |
| @ metblk.1: 0.14 min. spacing of met2 & met2Block |
| EXTERNAL met2 met2Block < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1238_metblk.1" { |
| @ metblk.1: met2 must not overlap met2Block |
| met2 AND met2Block |
| } |
| "r_1239_metblk.3" { |
| @ metblk.3: 0.145 min. spacing of met2Block & met2Routing |
| EXTERNAL met2Block met2Routing < 0.145 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met3Routing = SIZE met3pin BY 0.15 INSIDE OF met3 STEP 0.21 |
| "r_1240_metblk.1" { |
| @ metblk.1: 0.3 min. spacing of met3 & met3Block |
| EXTERNAL met3 met3Block < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1241_metblk.1" { |
| @ metblk.1: met3 must not overlap met3Block |
| met3 AND met3Block |
| } |
| "r_1242_metblk.3" { |
| @ metblk.3: 0.305 min. spacing of met3Block & met3Routing |
| EXTERNAL met3Block met3Routing < 0.305 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met4Routing = SIZE met4pin BY 0.15 INSIDE OF met4 STEP 0.21 |
| "r_1243_metblk.1" { |
| @ metblk.1: 0.3 min. spacing of met4 & met4Block |
| EXTERNAL met4 met4Block < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1244_metblk.1" { |
| @ metblk.1: met4 must not overlap met4Block |
| met4 AND met4Block |
| } |
| "r_1245_metblk.3" { |
| @ metblk.3: 0.305 min. spacing of met4Block & met4Routing |
| EXTERNAL met4Block met4Routing < 0.305 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met5Routing = SIZE met5pin BY 0.8 INSIDE OF met5 STEP 1.13 |
| "r_1246_metblk.1" { |
| @ metblk.1: 1.6 min. spacing of met5 & met5Block |
| EXTERNAL met5 met5Block < 1.6 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1247_metblk.1" { |
| @ metblk.1: met5 must not overlap met5Block |
| met5 AND met5Block |
| } |
| "r_1248_metblk.3" { |
| @ metblk.3: 1.605 min. spacing of met5Block & met5Routing |
| EXTERNAL met5Block met5Routing < 1.605 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| li1Routing = SIZE li1pin BY 0.085 INSIDE OF li1 STEP 0.12 |
| prBndryChip = prBndry AND SEALnoHoles_ORIGIN |
| prBndryIP = prBndry NOT SEALnoHoles_ORIGIN |
| "r_1249_metblk.2" { |
| @ metblk.2: 0.17 min. spacing of li1 & li1Block |
| EXTERNAL li1 li1Block < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1250_metblk.2" { |
| @ metblk.2: li1 must not overlap li1Block |
| li1 AND li1Block |
| } |
| "r_1251_metblk.4" { |
| @ metblk.4: 0.17 min. spacing of li1Block & li1Routing |
| EXTERNAL li1Block li1Routing < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1252_metblk.6" { |
| @ metblk.6: prBoundary.boundary not allowed in layout |
| COPY prBndryIP |
| } |
| "s_68_metblk.6" { |
| @ metblk.6: prBoundary.boundary not allowed in layout |
| COPY prBndryChip |
| } |
| polyBndryChip = INTERACT polyBndry SEALnoHoles_ORIGIN |
| polyBndryIP = polyBndry NOT polyBndryChip |
| "r_1253_metblk.7" { |
| @ metblk.7: poly.boundary not allowed in layout |
| COPY polyBndryIP |
| } |
| "s_69_metblk.7" { |
| @ metblk.7: poly.boundary not allowed in layout |
| COPY polyBndryChip |
| } |
| diffBndryChip = INTERACT diffBndry SEALnoHoles_ORIGIN |
| diffBndryIP = diffBndry NOT diffBndryChip |
| "r_1254_metblk.7" { |
| @ metblk.7: diff.boundary not allowed in layout |
| COPY diffBndryIP |
| } |
| "s_70_metblk.7" { |
| @ metblk.7: diff.boundary not allowed in layout |
| COPY diffBndryChip |
| } |
| tapBndryChip = INTERACT tapBndry SEALnoHoles_ORIGIN |
| tapBndryIP = tapBndry NOT tapBndryChip |
| "r_1255_metblk.7" { |
| @ metblk.7: tap.boundary not allowed in layout |
| COPY tapBndryIP |
| } |
| "s_71_metblk.7" { |
| @ metblk.7: tap.boundary not allowed in layout |
| COPY tapBndryChip |
| } |
| ESD_pwr2gnd_clamps = (EXTENT CELL "s8_esd_pwr2gnd_rc_50_sym_hv_4k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_50_sym_hv_4k_aup1") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_50_sym_hv_2k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_50_sym_hv_2k_dnwl") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_b") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_50_sym_hv_2k_aup1_c") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_40_sym_hv_2k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_21_sym_hv_2k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_21_asym_hv_2k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_50_casc_sym_hv_2k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_40_asym_lv_4k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_40_asym_lv_2k") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_rc_40_asym_lv_2k_dnwl") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl") OR |
| ((EXTENT CELL "s8_esd_pwr2gnd_50_casc_sym_hv_2k_dnwl_aup1") OR (EXTENT CELL "s8_esd_pwr2gnd_rc_40_asym_lv_2k_aup1")))))))))))))))) |
| ESDIDDIFF_NoXmt = (ESDID AND diff) NOT ESD_pwr2gnd_clamps |
| ESDIDSz50 = SIZE ESDIDDIFF_NoXmt BY 50 |
| ESDIDSz150 = SIZE ESDIDDIFF_NoXmt BY 150 |
| ErrESDIDSz50 = ESDIDSz50 AND LDID |
| ErrESDIDSz150 = ESDIDSz150 AND IJID |
| "s_72_chipint.1" { |
| @ chipint.1: areaid.ld not allowed within 50.0 um of ESDID |
| COPY ErrESDIDSz50 |
| } |
| "s_73_chipint.2" { |
| @ chipint.2: areaid.ij not allowed within 150.0 um of ESDID |
| COPY ErrESDIDSz150 |
| } |
| bigfomDummy = LENGTH fomDummyDRC > 25.0 |
| photoArrayDRC = (nwellAndDnwellDRC OR nwellDnwellHolesDRC) ENCLOSE photoDiode |
| fomDmy_keepout_1 = diffTap OR |
| (poly OR |
| (PwellRes OR |
| (pad OR |
| (cfom OR |
| (FOMmk OR |
| (photoArrayDRC OR P1Mmk)))))) |
| "r_1256_fomdmy.1" { |
| @ fomdmy.1: 0.5 min. width of fomDummyDRC |
| INTERNAL fomDummyDRC < 0.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1257_fomdmy_1a" { |
| @ fomdmy_1a: max width of fom dummy 25.0 |
| COPY bigfomDummy |
| } |
| "r_1258_fomdmy.2" { |
| @ fomdmy.2: 0.4 min. spacing/notch of fomDummyDRC |
| EXTERNAL fomDummyDRC < 0.4 ABUT < 90 SINGULAR REGION |
| } |
| "r_1259_fomdmy.4" { |
| @ fomdmy.4: 1 min. spacing of fomDummyDRC & SEALID |
| EXTERNAL fomDummyDRC SEALID < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1260_fomdmy.4" { |
| @ fomdmy.4: fomDummyDRC must not overlap SEALID |
| fomDummyDRC AND SEALID |
| } |
| "r_1261_fomdmy.6" { |
| @ fomdmy.6: 3.25 min. spacing of fomDummyDRC & fuse |
| EXTERNAL fomDummyDRC fuse < 3.25 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1262_fomdmy.6" { |
| @ fomdmy.6: fomDummyDRC must not overlap fuse |
| fomDummyDRC AND fuse |
| } |
| "r_1263_fomdmy.7" { |
| @ fomdmy.7: 0.13 min. spacing of fomDummyDRC & nsdm |
| EXTERNAL fomDummyDRC nsdm < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1264_fomdmy.7" { |
| @ fomdmy.7: fomDummyDRC must not overlap nsdm |
| fomDummyDRC AND nsdm |
| } |
| "r_1265_fomdmy.7" { |
| @ fomdmy.7: 0.13 min. spacing of fomDummyDRC & psdm |
| EXTERNAL fomDummyDRC psdm < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1266_fomdmy.7" { |
| @ fomdmy.7: fomDummyDRC must not overlap psdm |
| fomDummyDRC AND psdm |
| } |
| "r_1267_fomdmy.8" { |
| @ fomdmy.8: 0.18 min. enclosure of fomDummyDRC by nwell |
| q0fomDummyDRCand = fomDummyDRC AND nwell |
| ENCLOSURE q0fomDummyDRCand nwell < 0.18 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1268_fomdmy.9" { |
| @ fomdmy.9: 0.34 min. spacing of fomDummyDRC & nwell |
| EXTERNAL fomDummyDRC nwell < 0.34 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1269_fomdmy.10" { |
| @ fomdmy.10: 0.43 min. enclosure of fomDummyDRC by HVnwell |
| q1fomDummyDRCand = fomDummyDRC AND HVnwell |
| ENCLOSURE q1fomDummyDRCand HVnwell < 0.43 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1270_fomdmy.11" { |
| @ fomdmy.11: 0.33 min. spacing of fomDummyDRC & HVnwell |
| EXTERNAL fomDummyDRC HVnwell < 0.33 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1271_fomdmy.12" { |
| @ fomdmy.12: 0.5 min. enclosure of fomDummyDRC by FRAMEID |
| q2fomDummyDRCand = fomDummyDRC AND FRAMEID |
| ENCLOSURE q2fomDummyDRCand FRAMEID < 0.5 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1272_fomdmy.13" { |
| @ fomdmy.13: 0.5 min. spacing of fomDummyDRC & dieCut |
| EXTERNAL fomDummyDRC dieCut < 0.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| rdlInScribe = ((rdl OR CU1Mmk) AND frameBndr) NOT dieCut |
| nonCSPRDL = NOT INTERACT rdl bump |
| "r_1273_rdl.1" { |
| @ rdl.1: 10 min. width of rdl |
| INTERNAL rdl < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1274_rdl.2" { |
| @ rdl.2: 10 min. spacing/notch of rdl |
| EXTERNAL rdl < 10.0 REGION CORNER TO EDGE |
| } |
| "r_1275_rdl.2" { |
| @ rdl.2: 10 min. spacing/notch of rdl |
| EXTERNAL rdl < 10.0 REGION OPPOSITE PARALLEL ONLY |
| } |
| "r_1276_rdl.3" { |
| @ rdl.3: 10.75 min. enclosure of pad by nonCSPRDL |
| q0padand = pad AND nonCSPRDL |
| ENCLOSURE q0padand nonCSPRDL < 10.75 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1277_rdl.4" { |
| @ rdl.4: 15 min. enclosure of rdl by SEALnoHoles_ORIGIN |
| q0rdland = rdl AND SEALnoHoles_ORIGIN |
| ENCLOSURE q0rdland SEALnoHoles_ORIGIN < 15.0 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1278_rdl.5" { |
| @ rdl.5: (rdl OR ccu1m.mk) in scribe must not overlap areaid.ft. |
| COPY rdlInScribe |
| } |
| "r_1279_rdl.6" { |
| @ rdl.6: 19.66 min. spacing of nonCSPRDL & pad |
| EXTERNAL nonCSPRDL pad < 19.66 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| metXopt = met3 OR |
| (metop1_met3 OR |
| (metop2_met3 OR |
| (metop3_met3 OR |
| (metop4_met3 OR |
| (metop5_met3 OR |
| (metop6_met3 OR |
| (metop7_met3 OR metop8_met3))))))) |
| /// s8tee-5r pad and fuse rules |
| /// $Id: s8_drcRules 1 2018/06/18 17:29:47 GMT ssoares Exp $ |
| METxFUSE = met4 AND fuse |
| q0METxFUSE = NOT RECTANGLE METxFUSE ORTHOGONAL ONLY |
| "r_1280_mf.1&2" { |
| @ mf.1&2: metal4 fuse should be rectangular |
| COPY q0METxFUSE |
| } |
| q1METxFUSE = INTERNAL METxFUSE < 0.8 REGION |
| "r_1281_mf.1&2" { |
| @ mf.1&2: 0.8 min. width of metal4 fuse |
| COPY q1METxFUSE |
| } |
| q2METxFUSE = INTERNAL METxFUSE <= 0.8 REGION |
| q3METxFUSE = METxFUSE NOT q2METxFUSE |
| "r_1282_mf.1&2" { |
| @ mf.1&2: 0.8 max. width of metal4 fuse |
| COPY q3METxFUSE |
| } |
| q4METxFUSE = INTERNAL METxFUSE < 7.2 PROJECTING < 7.2 REGION |
| "r_1283_mf.1&2" { |
| @ mf.1&2: 7.2 min. length of metal4 fuse |
| COPY q4METxFUSE |
| } |
| q5METxFUSE = METxFUSE WITH EDGE (LENGTH METxFUSE > 7.2) |
| "r_1284_mf.1&2" { |
| @ mf.1&2: 7.2 max. length of metal4 fuse |
| COPY q5METxFUSE |
| } |
| "r_1285_mf.3" { |
| @ mf.3: 2.75 min. spacing of target |
| EXTERNAL target < 2.75 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE |
| } |
| METxFSIZE = SIZE METxFUSE BY 0.83 |
| METxOVERFUSE = NOT TOUCH (INTERACT met4 fuse) fuse |
| METxContact = METxOVERFUSE NOT METxFUSE |
| FUSEstraddMETx = fuse AND (CUT METxOVERFUSE METxFSIZE) |
| "r_1286_mf.5" { |
| @ mf.5: 0.83 max extension of met4 beyond fuse boundary |
| COPY FUSEstraddMETx |
| } |
| "r_1287_mf.22" { |
| @ mf.22: 1.96 min. spacing of METxContact |
| EXTERNAL METxContact < 1.96 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE |
| } |
| "r_1288_mf.6" { |
| @ mf.6: 3.295 min. spacing of target & met1 |
| EXTERNAL target met1 < 3.295 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1289_mf.6" { |
| @ mf.6: target must not overlap met1 |
| target AND met1 |
| } |
| "r_1290_mf.7" { |
| @ mf.7: 3.295 min. spacing of target & li1 |
| EXTERNAL target li1 < 3.295 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1291_mf.7" { |
| @ mf.7: target must not overlap li1 |
| target AND li1 |
| } |
| "r_1292_mf.8" { |
| @ mf.8: 2.655 min. spacing of target & poly |
| EXTERNAL target poly < 2.655 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1293_mf.8" { |
| @ mf.8: target must not overlap poly |
| target AND poly |
| } |
| "r_1294_mf.9" { |
| @ mf.9: 2.635 min. spacing of target & tap |
| EXTERNAL target tap < 2.635 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1295_mf.9" { |
| @ mf.9: target must not overlap tap |
| target AND tap |
| } |
| "r_1296_mf.10" { |
| @ mf.10: 3.245 min. spacing of target & diff |
| EXTERNAL target diff < 3.245 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1297_mf.10" { |
| @ mf.10: target must not overlap diff |
| target AND diff |
| } |
| "r_1298_mf.11" { |
| @ mf.11: 3.315 min. spacing of target & nwell |
| EXTERNAL target nwell < 3.315 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1299_mf.11" { |
| @ mf.11: target must not overlap nwell |
| target AND nwell |
| } |
| "r_1300_mf.19" { |
| @ mf.19: 3.295 min. spacing of target & met2 |
| EXTERNAL target met2 < 3.295 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1301_mf.19" { |
| @ mf.19: target must not overlap met2 |
| target AND met2 |
| } |
| floatingMetal = met4 NOT (NOT TOUCH (INTERACT met4 via3) via3) |
| shieldArea = SIZE target BY 3.3 |
| fuseShieldMetal = NOT TOUCH (INTERACT floatingMetal shieldArea) shieldArea |
| fuseShield = RECTANGLE fuseShieldMetal == 2.4 BY == 0.5 |
| badShield = ((EXTERNAL target floatingMetal <= 3.295 ABUT < 90 SINGULAR REGION) COINCIDENT EDGE floatingMetal) NOT COINCIDENT EDGE fuseShield |
| "r_1302_mf.12" { |
| @ mf.12: mf.12: 2.40x0.50 size of a fuse_shield |
| COPY badShield |
| } |
| nonfusemetX = met4 NOT fuse |
| endfuse = fuse COINCIDENT EDGE nonfusemetX |
| endFuseSz = EXPAND EDGE endfuse OUTSIDE BY 0.005 |
| METnotFUSE = (met4 NOT (fuse OR fuseShield)) OUTSIDE endFuseSz |
| "r_1303_mf.4" { |
| @ mf.4: 3.295 min. spacing of target & METnotFUSE |
| EXTERNAL target METnotFUSE < 3.295 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| fuseGroup = INTERACT METxFUSE (EXTERNAL target <= 3.995 ABUT < 90 REGION) |
| singleFuse = METxFUSE NOT fuseGroup |
| nonIsolatedFuse_a = (EXTERNAL singleFuse METnotFUSE < 4.0 REGION) OUTSIDE nonfusemetX |
| nonIsolatedFuse_e = singleFuse COINCIDENT OUTSIDE EDGE nonIsolatedFuse_a |
| "r_1304_mf.13" { |
| @ mf.13: 2.195 min. spacing of target & fuseShield |
| EXTERNAL target fuseShield < 2.195 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| mf_14Good = EXTERNAL nonIsolatedFuse_e fuseShield <= 2.9 REGION |
| mf_14 = (NOT INTERACT (EXPAND EDGE nonIsolatedFuse_e OUTSIDE BY 0.005) mf_14Good) COINCIDENT OUTSIDE EDGE singleFuse |
| "r_1305_mf.14" { |
| @ mf.14: max shield to target spacing |
| COPY mf_14 |
| } |
| mf_15a = fuseShield OUTSIDE nonIsolatedFuse_a |
| mf_15b = nonIsolatedFuse_a NOT (NOT TOUCH (INTERACT nonIsolatedFuse_a fuseShield) fuseShield) |
| "r_1306_mf.15a" { |
| @ mf.15a: fuseShield is allowed for non_isolated fuse edges ONLY |
| COPY mf_15a |
| } |
| "r_1307_mf.15b" { |
| @ mf.15b: fuseShield is required between peri metal and non isolated fuse edges |
| COPY mf_15b |
| } |
| shieldedMetal = EXPAND EDGE ((METnotFUSE NOT fuseShield) COINCIDENT OUTSIDE EDGE nonIsolatedFuse_a) INSIDE BY 0.005 |
| mf_18good = EXTERNAL fuseShield shieldedMetal >= 0.595 <= 0.605 OPPOSITE REGION |
| mf_18 = NOT INTERACT shieldedMetal mf_18good |
| "r_1308_mf.18" { |
| @ mf.18: 0.6 min&max space between fuse_shield and met4 |
| COPY mf_18 |
| } |
| mf_20 = INTERACT METxOVERFUSE (METxOVERFUSE AND fuse) > 1 |
| "r_1309_mf.20" { |
| @ mf.20: only one fuse allowed per metal line |
| COPY mf_20 |
| } |
| "r_1310_mf.24" { |
| @ mf.24: 3.295 min. spacing of target & met5 |
| EXTERNAL target met5 < 3.295 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1311_mf.24" { |
| @ mf.24: target must not overlap met5 |
| target AND met5 |
| } |
| SEALhole = HOLES SEALID |
| dieEdgeHoriz = ANGLE SEALID == 0 |
| dieEdgePerp = ANGLE SEALID == 90 |
| dieEdgeHorizSz = EXPAND EDGE dieEdgeHoriz OUTSIDE BY 0.005 |
| dieEdgePerpSz = EXPAND EDGE dieEdgePerp OUTSIDE BY 0.005 |
| dieEdgeH = dieEdgeHorizSz COINCIDENT EDGE SEALhole |
| dieEdgeP = dieEdgePerpSz COINCIDENT EDGE SEALhole |
| hoizXaxis = COPY 4006 |
| perpXaxis = COPY 4007 |
| padNoSEAL = pad NOT SEALID |
| dieEdgStepH41 = EXPAND EDGE dieEdgeH INSIDE by 41 |
| dieEdgStepHpad41 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH41)) NOT perpXaxis |
| allHorizX41 = hoizXaxis OR dieEdgStepHpad41 |
| dieEdgStepP41 = EXPAND EDGE dieEdgeP INSIDE by 41 |
| dieEdgStepPpad41 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP41)) NOT dieEdgStepHpad41 |
| allPerpX41 = perpXaxis OR dieEdgStepPpad41 |
| newSetPad41 = padNoSEAL NOT (dieEdgStepHpad41 OR dieEdgStepPpad41) |
| cornerPads41 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH41)) AND (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP41)) |
| horzAndCornPad = dieEdgStepH41 AND cornerPads41 |
| vertAndCornPad = dieEdgStepP41 AND cornerPads41 |
| padEdgeHorzErr = EXTERNAL padCenter horzAndCornPad < 60.0 ABUT < 90 PARALLEL OPPOSITE |
| padEdgeVertErr = EXTERNAL padCenter vertAndCornPad < 60.0 ABUT < 90 PARALLEL OPPOSITE |
| dfmVertXedge = DFM PROPERTY cornerPads41 padEdgeHorzErr padEdgeVertErr OVERLAP [edgeCheck =MIN(EW(padEdgeHorzErr))-MIN(EW(padEdgeVertErr))]>0 |
| dfmHorzXedge = DFM PROPERTY cornerPads41 padEdgeHorzErr padEdgeVertErr OVERLAP [edgeCheck =MIN(EW(padEdgeVertErr))-MIN(EW(padEdgeHorzErr))]>0 |
| dieEdgStepH82 = EXPAND EDGE dieEdgeH INSIDE by 82 |
| dieEdgStepHpad82 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH82)) NOT allPerpX41 |
| allHorizX82 = allHorizX41 OR dieEdgStepHpad82 |
| dieEdgStepP82 = EXPAND EDGE dieEdgeP INSIDE by 82 |
| dieEdgStepPpad82 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP82)) NOT dieEdgStepHpad82 |
| allPerpX82 = allPerpX41 OR dieEdgStepPpad82 |
| newSetPad82 = padNoSEAL NOT (dieEdgStepHpad82 OR dieEdgStepPpad82) |
| dieEdgStepH123 = EXPAND EDGE dieEdgeH INSIDE by 123 |
| dieEdgStepHpad123 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH123)) NOT allPerpX82 |
| allHorizX123 = allHorizX82 OR dieEdgStepHpad123 |
| dieEdgStepP123 = EXPAND EDGE dieEdgeP INSIDE by 123 |
| dieEdgStepPpad123 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP123)) NOT dieEdgStepHpad123 |
| allPerpX123 = allPerpX82 OR dieEdgStepPpad123 |
| newSetPad123 = padNoSEAL NOT (dieEdgStepHpad123 OR dieEdgStepPpad123) |
| dieEdgStepH164 = EXPAND EDGE dieEdgeH INSIDE by 164 |
| dieEdgStepHpad164 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH164)) NOT allPerpX123 |
| allHorizX164 = allHorizX123 OR dieEdgStepHpad164 |
| dieEdgStepP164 = EXPAND EDGE dieEdgeP INSIDE by 164 |
| dieEdgStepPpad164 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP164)) NOT dieEdgStepHpad164 |
| allPerpX164 = allPerpX123 OR dieEdgStepPpad164 |
| newSetPad164 = padNoSEAL NOT (dieEdgStepHpad164 OR dieEdgStepPpad164) |
| dieEdgStepH205 = EXPAND EDGE dieEdgeH INSIDE by 205 |
| dieEdgStepHpad205 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH205)) NOT allPerpX164 |
| allHorizX205 = allHorizX164 OR dieEdgStepHpad205 |
| dieEdgStepP205 = EXPAND EDGE dieEdgeP INSIDE by 205 |
| dieEdgStepPpad205 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP205)) NOT dieEdgStepHpad205 |
| allPerpX205 = allPerpX164 OR dieEdgStepPpad205 |
| newSetPad205 = padNoSEAL NOT (dieEdgStepHpad205 OR dieEdgStepPpad205) |
| dieEdgStepH246 = EXPAND EDGE dieEdgeH INSIDE by 246 |
| dieEdgStepHpad246 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH246)) NOT allPerpX205 |
| allHorizX246 = allHorizX205 OR dieEdgStepHpad246 |
| dieEdgStepP246 = EXPAND EDGE dieEdgeP INSIDE by 246 |
| dieEdgStepPpad246 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP246)) NOT dieEdgStepHpad246 |
| allPerpX246 = allPerpX205 OR dieEdgStepPpad246 |
| newSetPad246 = padNoSEAL NOT (dieEdgStepHpad246 OR dieEdgStepPpad246) |
| dieEdgStepH287 = EXPAND EDGE dieEdgeH INSIDE by 287 |
| dieEdgStepHpad287 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH287)) NOT allPerpX246 |
| allHorizX287 = allHorizX246 OR dieEdgStepHpad287 |
| dieEdgStepP287 = EXPAND EDGE dieEdgeP INSIDE by 287 |
| dieEdgStepPpad287 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP287)) NOT dieEdgStepHpad287 |
| allPerpX287 = allPerpX246 OR dieEdgStepPpad287 |
| newSetPad287 = padNoSEAL NOT (dieEdgStepHpad287 OR dieEdgStepPpad287) |
| dieEdgStepH328 = EXPAND EDGE dieEdgeH INSIDE by 328 |
| dieEdgStepHpad328 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH328)) NOT allPerpX287 |
| allHorizX328 = allHorizX287 OR dieEdgStepHpad328 |
| dieEdgStepP328 = EXPAND EDGE dieEdgeP INSIDE by 328 |
| dieEdgStepPpad328 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP328)) NOT dieEdgStepHpad328 |
| allPerpX328 = allPerpX287 OR dieEdgStepPpad328 |
| newSetPad328 = padNoSEAL NOT (dieEdgStepHpad328 OR dieEdgStepPpad328) |
| dieEdgStepH369 = EXPAND EDGE dieEdgeH INSIDE by 369 |
| dieEdgStepHpad369 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH369)) NOT allPerpX328 |
| allHorizX369 = allHorizX328 OR dieEdgStepHpad369 |
| dieEdgStepP369 = EXPAND EDGE dieEdgeP INSIDE by 369 |
| dieEdgStepPpad369 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP369)) NOT dieEdgStepHpad369 |
| allPerpX369 = allPerpX328 OR dieEdgStepPpad369 |
| newSetPad369 = padNoSEAL NOT (dieEdgStepHpad369 OR dieEdgStepPpad369) |
| dieEdgStepH410 = EXPAND EDGE dieEdgeH INSIDE by 410 |
| dieEdgStepHpad410 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH410)) NOT allPerpX369 |
| allHorizX410 = allHorizX369 OR dieEdgStepHpad410 |
| dieEdgStepP410 = EXPAND EDGE dieEdgeP INSIDE by 410 |
| dieEdgStepPpad410 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP410)) NOT dieEdgStepHpad410 |
| allPerpX410 = allPerpX369 OR dieEdgStepPpad410 |
| newSetPad410 = padNoSEAL NOT (dieEdgStepHpad410 OR dieEdgStepPpad410) |
| dieEdgStepH451 = EXPAND EDGE dieEdgeH INSIDE by 451 |
| dieEdgStepHpad451 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH451)) NOT allPerpX410 |
| allHorizX451 = allHorizX410 OR dieEdgStepHpad451 |
| dieEdgStepP451 = EXPAND EDGE dieEdgeP INSIDE by 451 |
| dieEdgStepPpad451 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP451)) NOT dieEdgStepHpad451 |
| allPerpX451 = allPerpX410 OR dieEdgStepPpad451 |
| newSetPad451 = padNoSEAL NOT (dieEdgStepHpad451 OR dieEdgStepPpad451) |
| dieEdgStepH492 = EXPAND EDGE dieEdgeH INSIDE by 492 |
| dieEdgStepHpad492 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH492)) NOT allPerpX451 |
| allHorizX492 = allHorizX451 OR dieEdgStepHpad492 |
| dieEdgStepP492 = EXPAND EDGE dieEdgeP INSIDE by 492 |
| dieEdgStepPpad492 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP492)) NOT dieEdgStepHpad492 |
| allPerpX492 = allPerpX451 OR dieEdgStepPpad492 |
| newSetPad492 = padNoSEAL NOT (dieEdgStepHpad492 OR dieEdgStepPpad492) |
| dieEdgStepH533 = EXPAND EDGE dieEdgeH INSIDE by 533 |
| dieEdgStepHpad533 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH533)) NOT allPerpX492 |
| allHorizX533 = allHorizX492 OR dieEdgStepHpad533 |
| dieEdgStepP533 = EXPAND EDGE dieEdgeP INSIDE by 533 |
| dieEdgStepPpad533 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP533)) NOT dieEdgStepHpad533 |
| allPerpX533 = allPerpX492 OR dieEdgStepPpad533 |
| newSetPad533 = padNoSEAL NOT (dieEdgStepHpad533 OR dieEdgStepPpad533) |
| padXorg = COPY allHorizX533 |
| padYorg = COPY allPerpX533 |
| padCornerXtmp = COPY dfmHorzXedge |
| padCornerYtmp = COPY dfmVertXedge |
| padCornXpitchPadX = EXPAND EDGE (ANGLE padCornerXtmp == 90) OUTSIDE BY 7 |
| padCornXpitchPadY = EXPAND EDGE (ANGLE padCornerXtmp == 0) OUTSIDE BY 7 |
| padCornXtouchPitchInY = TOUCH padCornXpitchPadY pad == 2 |
| padCornXtouchPitchInX = TOUCH padCornXpitchPadX pad == 2 |
| padCornerSwapxtoY = NOT TOUCH (TOUCH padCornerXtmp padCornXtouchPitchInY) padCornXtouchPitchInX |
| padCornerX = (padCornerXtmp OR padCornerSwapYtoX) NOT padCornerSwapXtoY |
| padCornYpitchPadY = EXPAND EDGE (ANGLE padCornerYtmp == 90) OUTSIDE BY 7 |
| padCornYpitchPadX = EXPAND EDGE (ANGLE padCornerYtmp == 0) OUTSIDE BY 7 |
| padCornYtouchPitchInY = TOUCH padCornYpitchPadY pad == 2 |
| padCornYtouchPitchInX = TOUCH padCornYpitchPadX pad == 2 |
| padCornerSwapYtoX = NOT TOUCH (TOUCH padCornerYtmp padCornYtouchPitchInY) padCornYtouchPitchInX |
| padCornerY = (padCornerYtmp OR padCornerSwapXtoY) NOT padCornerSwapYtoX |
| padX = (padXorg OR padCornerX) NOT padCornerY |
| padY = (padYorg OR padCornerY) NOT padCornerX |
| minSpacepadYedges = EXPAND EDGE (ANGLE padY == 0) INSIDE BY 0.005 |
| minSpacepadYyEdge = EXPAND EDGE (ANGLE padY == 90) INSIDE BY 0.005 |
| minSpacepadXedges = EXPAND EDGE (ANGLE padX == 90) INSIDE BY 0.005 |
| minSpacepadXyEdge = EXPAND EDGE (ANGLE padX == 0) INSIDE BY 0.005 |
| laser_targetCells = EXTENT CELL "lazX_*" "lazY_*" ORIGINAL |
| BONDPAD = pad OUTSIDE (SEALID OR |
| (moduleCutAREA OR |
| (fuse OR |
| (FRAMEID OR laser_targetCells)))) |
| padInInd = pad AND inductor |
| viapcell = EXTENT CELL "M5RDL*" ORIGINAL |
| bondpadPcell = (EXTENT CELL "padPL*" ORIGINAL) OR bondpadCuPillar |
| plasticPackPad = WITH TEXT bondpadPcell "plastic" textlabel |
| hermeticPackPad = WITH TEXT bondpadPcell "hermetic" textlabel |
| PadPLhp = WITH TEXT bondpadPcell "HP" textlabel |
| PadPLfp = WITH TEXT bondpadPcell "FP" textlabel |
| PadPLstg = WITH TEXT bondpadPcell "STG" textlabel |
| PadPLwlbi = WITH TEXT bondpadPcell "WLBI" textlabel |
| bondpadCuPillar = EXTENT CELL "s8fpafeg1_io_amkor_pad*" "fpg1_amkor_39x39_pad*" ORIGINAL |
| notValidbondPad = BONDPAD NOT (viapcell OR |
| (padInInd OR |
| (bondpadPcell OR bondpadCuPillar))) |
| bondpadPcellNoText = bondpadPcell NOT plasticPackPad |
| anyPadPlastic = pad AND plasticPackPad |
| "r_1312_pad.1" { |
| @ pad.1: padPL pcells should be used for bondpad |
| COPY notValidbondPad |
| } |
| "r_1313_pad.1" { |
| @ pad.1: padPL pcells should have text plastic to be used for bondpad |
| COPY bondpadPcellNoText |
| } |
| "r_1314_pad.16" { |
| @ pad.16: Hermetic package pads are not supported inthis flow |
| COPY hermeticPackPad |
| } |
| bondpadNormal = BONDPAD AND bondpadPcell |
| bondpadNormalPlastic = BONDPAD AND plasticPackPad |
| bondpadHP = BONDPAD AND PadPLhp |
| bondpadFP = BONDPAD AND PadPLfp |
| bondpadSTG = BONDPAD AND PadPLstg |
| bondpadWLBI = BONDPAD AND PadPLwlbi |
| "r_1315_pad.4/4a" { |
| @ pad.4/4a: 2.7 min. enclosure of bondpadNormal by met5 |
| q0bondpadNormaland = bondpadNormal AND met5 |
| ENCLOSURE q0bondpadNormaland met5 < 2.7 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| met4_ring = DONUT (met4 AND (bondpadPcell NOT BONDPAD)) |
| met4_err_ringSpc = INTERACT met4_ring (met4_ring AND bondpadNormal) |
| "r_1316_pad.5" { |
| @ pad.5: Zero Spacing between lower level met4 ring and Advanced Bondpad |
| COPY met4_err_ringSpc |
| } |
| bondpadEdges = BONDPAD COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges) |
| bondpadEdgesSz = EXPAND EDGE bondpadEdges INSIDE BY 30 |
| bondpadEdgesSide = EXPAND EDGE (LENGTH (bondpadEdgesSz INSIDE EDGE BONDPAD) <= 60.0 > (60.0 / 2.0)) INSIDE BY 0.005 |
| SmallBondPad = INTERACT BONDPAD bondpadEdgesSide |
| LargeBondPad = BONDPAD NOT SmallBondPad |
| padGroupingY = (INTERACT BONDPAD (BONDPAD AND (padCenter AND padCenterDieY))) OR padCenterDieY |
| smallGroupingY = (INTERACT padGroupingY (padGroupingY AND (padCenter AND SmallBondPad))) AND BONDPAD |
| largeGroupingY = (padGroupingY NOT smallGroupingY) AND BONDPAD |
| padGroupingX = (INTERACT BONDPAD (BONDPAD AND (padCenter AND padCenterDieX))) OR padCenterDieX |
| smallGroupingX = (INTERACT padGroupingX (padGroupingX AND (padCenter AND SmallBondPad))) AND BONDPAD |
| largeGroupingX = (padGroupingX NOT smallGroupingX) AND BONDPAD |
| met5OutsidePad = met5 OUTSIDE bondPadPcell |
| "r_1317_pad.6" { |
| @ pad.6: 5 min. spacing of smallGroupingY & met5OutsidePad |
| EXTERNAL smallGroupingY met5OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1318_pad.7" { |
| @ pad.7: 10 min. spacing of largeGroupingY & met5OutsidePad |
| EXTERNAL largeGroupingY met5OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1319_pad.6" { |
| @ pad.6: 5 min. spacing of smallGroupingX & met5OutsidePad |
| EXTERNAL smallGroupingX met5OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1320_pad.7" { |
| @ pad.7: 10 min. spacing of largeGroupingX & met5OutsidePad |
| EXTERNAL largeGroupingX met5OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| met4OutsidePad = met4 OUTSIDE bondPadPcell |
| "r_1321_pad.6" { |
| @ pad.6: 5 min. spacing of smallGroupingY & met4OutsidePad |
| EXTERNAL smallGroupingY met4OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1322_pad.7" { |
| @ pad.7: 10 min. spacing of largeGroupingY & met4OutsidePad |
| EXTERNAL largeGroupingY met4OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1323_pad.6" { |
| @ pad.6: 5 min. spacing of smallGroupingX & met4OutsidePad |
| EXTERNAL smallGroupingX met4OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1324_pad.7" { |
| @ pad.7: 10 min. spacing of largeGroupingX & met4OutsidePad |
| EXTERNAL largeGroupingX met4OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| bondpadNormalprobe = WITH TEXT bondpadNormalPlastic "probe-only" textlabel |
| bondpadNormalNoprobe = bondpadNormalPlastic NOT (cuPillarPadText OR bondpadNormalprobe) |
| "r_1325_pad.10" { |
| @ pad.10: bondpadNormalNoprobe must not overlap met4 |
| bondpadNormalNoprobe AND met4 |
| } |
| BONDPADangleless45 = EXPAND EDGE (ANGLE bondpadNormalPlastic > 0 < 45) INSIDE BY 0.005 |
| BONDPADangle45_90 = EXPAND EDGE (ANGLE bondpadNormalPlastic > 45 < 90) INSIDE BY 0.005 |
| errBondpadEdgeAngle = BONDPADangleless45 OR BONDPADangle45_90 |
| BONDPADangle45 = ANGLE bondpadNormalPlastic > 44.9 < 45.1 |
| BONDPADangle45Sz = EXPAND EDGE BONDPADangle45 INSIDE BY 0.005 |
| BONDPADangle90 = EXPAND EDGE (ANGLE bondpadNormalPlastic == 90) INSIDE BY 0.005 |
| BONDPADangle0 = EXPAND EDGE (ANGLE bondpadNormalPlastic == 0) INSIDE BY 0.005 |
| errBondapadEdges45 = bondpadNormalPlastic NOT (INTERACT bondpadNormalPlastic (bondpadNormalPlastic AND BONDPADangle45Sz) == 4) |
| errBondapadEdges90 = bondpadNormalPlastic NOT (INTERACT bondpadNormalPlastic (bondpadNormalPlastic AND BONDPADangle90) == 2) |
| errBondapadEdges0 = bondpadNormalPlastic NOT (INTERACT bondpadNormalPlastic (bondpadNormalPlastic AND BONDPADangle0) == 2) |
| errBondapadEdges0_90 = errBondapadEdges90 OR errBondapadEdges0 |
| errBONDPADangle45minLen = LENGTH BONDPADangle45 < 7.0 |
| errBONDPADangle45maxLen = LENGTH BONDPADangle45 > 8.8 |
| bondPad90degCor = INTERNAL bondpadNormalPlastic < 0.005 ABUT == 90 INTERSECTING REGION |
| "r_1326_pad.11" { |
| @ pad.11: Bondpad should not have 90 degree corner |
| COPY bondPad90degCor |
| } |
| "r_1327_pad.11" { |
| @ pad.11: Bondpad should have 45 degree corner |
| COPY errBondpadEdgeAngle |
| } |
| "r_1328_pad.11" { |
| @ pad.11: Bondpad should have only 4 45 degree corner |
| COPY errBondapadEdges45 |
| } |
| "r_1329_pad.11" { |
| @ pad.11: Bondpad should have only 4 orthogonal edges |
| COPY errBondapadEdges0_90 |
| } |
| "r_1330_pad.12" { |
| @ pad.12: 7.0 Min length of 45 degree bevel on Bond pad |
| COPY errBONDPADangle45minLen |
| } |
| "r_1331_pad.13" { |
| @ pad.13: 8.8 Max length of 45 degree bevel on Bond pad |
| COPY errBONDPADangle45maxLen |
| } |
| solid_seal = (HOLES SEALID) OR (DONUT SEALID) |
| solid_seal_shrink = SIZE solid_seal BY -500.0 |
| maxSpcPadSeal = bondpadNormalPlastic WITH EDGE (bondpadNormalPlastic COINCIDENT INSIDE EDGE solid_seal_shrink) |
| lessMaxSpcPadSeal = CUT bondpadNormalPlastic solid_seal_shrink |
| cuPillarPadText = INTERACT pad (WITH TEXT pad "CU-PILLAR-PAD" textlabel) |
| aupDummyPadText = INTERACT bondpadCuPillar (WITH TEXT pad "AUP-DUMMY-OK" textlabel) |
| psoc4xmt = EXTENT CELL "psoc4*_top" ORIGINAL |
| cadXmpt = (EXTENT CELL "tsg5_m_tcg5_top*" ORIGINAL) OR |
| (cuPillarPadText OR psoc4xmt) |
| err_pad_15 = (bondpadNormalPlastic NOT (maxSpcPadSeal OR |
| (lessMaxSpcPadSeal OR cadXmpt))) AND solid_seal_shrink |
| "r_1332_pad.14" { |
| @ pad.14: 16.99 min. enclosure of anyPadPlastic by solid_seal |
| q0anyPadPlasticand = anyPadPlastic AND solid_seal |
| ENCLOSURE q0anyPadPlasticand solid_seal < 16.99 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1333_pad.15" { |
| @ pad.15: 500.0 Max spacing between bondpad opening and edge of scribe line(outer end of seal ring) |
| COPY err_pad_15 |
| } |
| padMetal = pad AND (bondPadPcell AND met5) |
| met1Shield = COPY 4008 |
| met1UndPadMet = INTERACT met1 (met1 AND padMetal) |
| met1UndPadMetOnly = met1UndPadMet AND (BONDPAD NOT aupDummyPadText) |
| met1UndPadMetMinW = INTERNAL met1UndPadMetOnly < 0.14 PARALLEL OPPOSITE REGION |
| "r_1334_pad.17" { |
| @ pad.17: 1.5 min. spacing/notch of met1UndPadMetOnly |
| EXTERNAL met1UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE |
| } |
| "r_1335_pad.18" { |
| @ pad.18: 0.14 min width of met1 under pad metal |
| COPY met1UndPadMetMinW |
| } |
| met2UndPadMet = INTERACT met2 (met2 AND padMetal) |
| met2UndPadMetOnly = met2UndPadMet AND (BONDPAD NOT aupDummyPadText) |
| met2UndPadMetMinW = INTERNAL met2UndPadMetOnly < 0.14 PARALLEL OPPOSITE REGION |
| "r_1336_pad.17" { |
| @ pad.17: 1.5 min. spacing/notch of met2UndPadMetOnly |
| EXTERNAL met2UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE |
| } |
| "r_1337_pad.18" { |
| @ pad.18: 0.14 min width of met2 under pad metal |
| COPY met2UndPadMetMinW |
| } |
| met3UndPadMet = INTERACT met3 (met3 AND padMetal) |
| met3UndPadMetOnly = met3UndPadMet AND (BONDPAD NOT aupDummyPadText) |
| met3UndPadMetMinW = INTERNAL met3UndPadMetOnly < 0.3 PARALLEL OPPOSITE REGION |
| "r_1338_pad.17" { |
| @ pad.17: 1.5 min. spacing/notch of met3UndPadMetOnly |
| EXTERNAL met3UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE |
| } |
| "r_1339_pad.18" { |
| @ pad.18: 0.3 min width of met3 under pad metal |
| COPY met3UndPadMetMinW |
| } |
| met1UndPadMetMaxW = WITH WIDTH ((met1 AND padMetal) NOT met1Shield) > 25.0 |
| "r_1340_pad.19" { |
| @ pad.19: 25 max width of met1 under pad metal |
| COPY met1UndPadMetMaxW |
| } |
| met2UndPadMetMaxW = WITH WIDTH ((met2 AND padMetal) NOT met1Shield) > 25.0 |
| "r_1341_pad.19" { |
| @ pad.19: 25 max width of met2 under pad metal |
| COPY met2UndPadMetMaxW |
| } |
| hpb_exemptions = EXTENT CELL "hpb_esdTriggerULB_b*" "s8hpbtoolkit_dual_rx_2*" "s8hpbtoolkit_dual_rx_inv*" ORIGINAL |
| ind_exemptions = EXTENT CELL "s8bio_top_biocmux_vccio*" ORIGINAL |
| k2_exemptions = EXTENT CELL "k2_east_pads_top*" "k2_west_pads_top*" ORIGINAL |
| kry_exemptions = EXTENT CELL "krypton_io_pframe*" "krypton2_toplevel" ORIGINAL |
| leo_exemptons = EXTENT CELL "s8ppscio_top_vca_2*" "s8ppscio_top_vcd_2*" "s8ppscio_top_vda_2*" "s8ppscio_top_vdd_2*" "s8ppscio_top_vdd_3*" "s8ppscio_top_vddabuf*" "s8ppscio_top_vio*" "s8ppscio_top_vssa_2*" "s8ppscio_top_vssd_2*" "s8ppscio_top_vssio_2*" "s8ppscio_top_vssio_3*" "s8ppscio_top_vssio_2*" "s8ppscio_top_vssabuf*" "s8ppscio_top_vusb_2" ORIGINAL |
| tsg_exemptions = EXTENT CELL "s8esdg4_net_io_b*" "s8ppscio_top_vcd_2*" "s8ppscio_top_vdd_2*" "s8tsg4io_top_vio*" "s8tsg4io_top_vssd_2*" "s8tsg4io_top_vssio_2*" "s8tkm0s8_corner_tp2*" ORIGINAL |
| qspi_exemptions = EXTENT CELL "s8tnvsio18_io_top" "s8tnviso18_io_top_hv" "quadspinvsram_top*" ORIGINAL |
| pad_19_exemptions = hpb_exemptions OR |
| (ind_exemptions OR |
| (k2_exemptions OR |
| (kry_exemptions OR |
| (leo_exemptons OR |
| (tsg_exemptions OR qspi_exemptions))))) |
| aupmetUndPadMetMaxW = (WITH WIDTH (met3 AND padMetal) > 6.0) NOT pad_19_exemptions |
| "r_1342_pad.19" { |
| @ pad.19: 6 max width of met3 under pad metal |
| COPY aupmetUndPadMetMaxW |
| } |
| padFPedgX = bondpadFP COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges) |
| padFPedgXsz = EXPAND EDGE padFPedgX INSIDE BY 30 |
| badFPwEdg = LENGTH (padFPedgXsz NOT COINCIDENT EDGE padFPedgX) > 30.0 < 60.0 |
| badFPwEdgSz = EXPAND EDGE badFPwEdg INSIDE BY 0.005 |
| badFPwidth = INTERACT (bondpadFP NOT bondpadCuPillar) ((bondpadFP NOT bondpadCuPillar) AND (INTERACT (EXPAND EDGE padFPedgX INSIDE BY 0.005) ((EXPAND EDGE padFPedgX INSIDE BY 0.005) AND badFPwEdgSz) == 2)) |
| padFPedgY = bondpadFP COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge) |
| padFPedgYsz = EXPAND EDGE padFPedgY INSIDE BY 30 |
| badFPlEdg = LENGTH (padFPedgYsz NOT COINCIDENT EDGE padFPedgY) > 30.0 < 60.0 |
| badFPlEdgSz = EXPAND EDGE badFPlEdg INSIDE BY 0.005 |
| badFPlength = INTERACT (bondpadFP NOT bondpadCuPillar) ((bondpadFP NOT bondpadCuPillar) AND (INTERACT (EXPAND EDGE padFPedgY INSIDE BY 0.005) ((EXPAND EDGE padFPedgY INSIDE BY 0.005) AND badFPlEdgSz) == 2)) |
| padSTGedgX = bondpadSTG COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges) |
| padSTGedgXsz = EXPAND EDGE padSTGedgX INSIDE BY 30 |
| badSTGwEdg = LENGTH (padSTGedgXsz NOT COINCIDENT EDGE padSTGedgX) > 30.0 < 60.0 |
| badSTGwEdgSz = EXPAND EDGE badSTGwEdg INSIDE BY 0.005 |
| badSTGwidth = INTERACT bondpadSTG (bondpadSTG AND (INTERACT (EXPAND EDGE padSTGedgX INSIDE BY 0.005) ((EXPAND EDGE padSTGedgX INSIDE BY 0.005) AND badSTGwEdgSz) == 2)) |
| padSTGedgY = bondpadSTG COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge) |
| padSTGedgYsz = EXPAND EDGE padSTGedgY INSIDE BY 30 |
| badSTGlEdg = LENGTH (padSTGedgYsz NOT COINCIDENT EDGE padSTGedgY) > 30.0 < 60.0 |
| badSTGlEdgSz = EXPAND EDGE badSTGlEdg INSIDE BY 0.005 |
| badSTGlength = INTERACT bondpadSTG (bondpadSTG AND (INTERACT (EXPAND EDGE padSTGedgY INSIDE BY 0.005) ((EXPAND EDGE padSTGedgY INSIDE BY 0.005) AND badSTGlEdgSz) == 2)) |
| psoc4cuCells = EXTENT CELL "psoc4*_top*" |
| bondpadHPcu = bondpadHP AND psoc4cuCells |
| bondpadHPorg = bondpadHP NOT bondpadHPcu |
| padHPedgX = bondpadHPorg COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges) |
| padHPedgXsz = EXPAND EDGE padHPedgX INSIDE BY 30 |
| badHPwEdg = LENGTH (padHPedgXsz NOT COINCIDENT EDGE padHPedgX) > 30.0 < 60.0 |
| badHPwEdgSz = EXPAND EDGE badHPwEdg INSIDE BY 0.005 |
| badHPwidth = INTERACT bondpadHP (bondpadHP AND (INTERACT (EXPAND EDGE padHPedgX INSIDE BY 0.005) ((EXPAND EDGE padHPedgX INSIDE BY 0.005) AND badHPwEdgSz) == 2)) |
| padHPedgY = bondpadHPorg COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge) |
| padHPedgYsz = EXPAND EDGE padHPedgY INSIDE BY 30 |
| badHPlEdg = LENGTH (padHPedgYsz NOT COINCIDENT EDGE padHPedgY) > 30.0 < 60.0 |
| badHPlEdgSz = EXPAND EDGE badHPlEdg INSIDE BY 0.005 |
| badHPlength = INTERACT bondpadHP (bondpadHP AND (INTERACT (EXPAND EDGE padHPedgY INSIDE BY 0.005) ((EXPAND EDGE padHPedgY INSIDE BY 0.005) AND badHPlEdgSz) == 2)) |
| padHPcuedgX = bondpadHPcu COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges) |
| padHPcuedgXsz = EXPAND EDGE padHPcuedgX INSIDE BY 29 |
| badHPcuwEdg = LENGTH (padHPcuedgXsz NOT COINCIDENT EDGE padHPcuedgX) > 29.0 < 58.0 |
| badHPcuwEdgSz = EXPAND EDGE badHPcuwEdg INSIDE BY 0.005 |
| badHPcuwidth = INTERACT (bondpadHPcu NOT bondpadHPcuSolo) ((bondpadHPcu NOT bondpadHPcuSolo) AND (INTERACT (EXPAND EDGE padHPcuedgX INSIDE BY 0.005) ((EXPAND EDGE padHPcuedgX INSIDE BY 0.005) AND badHPcuwEdgSz) == 2)) |
| padHPcuedgY = bondpadHPcu COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge) |
| padHPcuedgYsz = EXPAND EDGE padHPcuedgY INSIDE BY 30 |
| badHPculEdg = LENGTH (padHPcuedgYsz NOT COINCIDENT EDGE padHPcuedgY) > 30.0 < 60.0 |
| badHPculEdgSz = EXPAND EDGE badHPculEdg INSIDE BY 0.005 |
| badHPculength = INTERACT (bondpadHPcu NOT (psoc4xmt OR bondpadHPcuSolo)) ((bondpadHPcu NOT (psoc4xmt OR bondpadHPcuSolo)) AND (INTERACT (EXPAND EDGE padHPcuedgY INSIDE BY 0.005) ((EXPAND EDGE padHPcuedgY INSIDE BY 0.005) AND badHPculEdgSz) == 2)) |
| bondpadHPcuSz = SIZE bondPadHPcu BY (50.0 / 2) |
| bondpadHPcuSolo = bondpadHPcu AND (INTERACT bondpadHPcuSz bondpadHPcu == 1) |
| bondpadHPcuSoloSz = SIZE bondPadHPcuSolo BY 10 UNDEROVER |
| badHPcuSoloWL = NOT RECTANGLE bondpadHPcuSoloSz >= 58.0 BY >= 60.0 |
| padWLBIedgX = bondpadWLBI COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges) |
| padWLBIedgXsz = EXPAND EDGE padWLBIedgX INSIDE BY 25 |
| badWLBIwEdg = LENGTH (padWLBIedgXsz NOT COINCIDENT EDGE padWLBIedgX) > 25.0 < 50.0 |
| badWLBIwEdgSz = EXPAND EDGE badWLBIwEdg INSIDE BY 0.005 |
| badWLBIwidth = INTERACT bondpadWLBI (bondpadWLBI AND (INTERACT (EXPAND EDGE padWLBIedgX INSIDE BY 0.005) ((EXPAND EDGE padWLBIedgX INSIDE BY 0.005) AND badWLBIwEdgSz) == 2)) |
| padWLBIedgY = bondpadWLBI COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge) |
| padWLBIedgYsz = EXPAND EDGE padWLBIedgY INSIDE BY 30 |
| badWLBIlEdg = LENGTH (padWLBIedgYsz NOT COINCIDENT EDGE padWLBIedgY) > 30.0 < 60.0 |
| badWLBIlEdgSz = EXPAND EDGE badWLBIlEdg INSIDE BY 0.005 |
| badWLBIlength = INTERACT bondpadWLBI (bondpadWLBI AND (INTERACT (EXPAND EDGE padWLBIedgY INSIDE BY 0.005) ((EXPAND EDGE padWLBIedgY INSIDE BY 0.005) AND badWLBIlEdgSz) == 2)) |
| "r_1343_pad.2.1" { |
| @ pad.2.1: 60 min width of padPLFP in x direction |
| COPY badFPwidth |
| } |
| "r_1344_pad.3.1" { |
| @ pad.3.1: 60 min length of padPLFP in y direction |
| COPY badFPlength |
| } |
| "r_1345_pad.4.1" { |
| @ pad.4.1: 60 min width of padPLSTG in x direction |
| COPY badSTGwidth |
| } |
| "r_1346_pad.5.1" { |
| @ pad.5.1: 60 min length of padPLSTG in y direction |
| COPY badSTGlength |
| } |
| "r_1347_pad.6.1" { |
| @ pad.6.1: 60 min width of padPLHP in x direction |
| COPY badHPwidth |
| } |
| "r_1348_pad.6.1" { |
| @ pad.6.1: 60 min length of padPLHP in y direction |
| COPY badHPlength |
| } |
| "r_1349_pad.6.1a" { |
| @ pad.6.1a: 58 min width of padPLHPcu in x direction |
| COPY badHPcuwidth |
| } |
| "r_1350_pad.6.1b" { |
| @ pad.6.1b: 60 min length of padPLHPcu in y direction |
| COPY badHPculength |
| } |
| "r_1351_pad.6.1a/b" { |
| @ pad.6.1a/b: 58x60 min dimensions of padPLHPcu which are not within 50 of other pad |
| COPY badHPcuSoloWL |
| } |
| "r_1352_pad.7.1" { |
| @ pad.7.1: 50 min width of padPLWLBI in x direction |
| COPY badWLBIwidth |
| } |
| "r_1353_pad.8.1" { |
| @ pad.8.1: 60 min length of padPLWLBI in y direction |
| COPY badWLBIlength |
| } |
| bondpadCuPillarSz = SIZE (pad AND bondpadCuPillar) UNDEROVER BY 10 |
| q0bondpadCuPillarSz = NOT RECTANGLE bondpadCuPillarSz ORTHOGONAL ONLY |
| "r_1354_pad_2/3.1" { |
| @ pad_2/3.1: bondpadCuPillarSz should be rectangular |
| COPY q0bondpadCuPillarSz |
| } |
| q1bondpadCuPillarSz = INTERNAL bondpadCuPillarSz < 39.0 REGION |
| "r_1355_pad_2/3.1" { |
| @ pad_2/3.1: 39 min. width of bondpadCuPillarSz |
| COPY q1bondpadCuPillarSz |
| } |
| q2bondpadCuPillarSz = bondpadCuPillarSz WITH EDGE (LENGTH bondpadCuPillarSz > 39.0) |
| "r_1356_pad_2/3.1" { |
| @ pad_2/3.1: 39 max. length of bondpadCuPillarSz |
| COPY q2bondpadCuPillarSz |
| } |
| padFPedgSzXsp = EXPAND EDGE padFPedgX OUTSIDE BY 8 |
| padFPspaceBad = INTERACT padFPedgSzXsp (padFPedgSzXsp AND (bondpadFP OR (bondpadHP OR (bondpadSTG OR bondpadWLBI)))) |
| padHPedgSzXsp = EXPAND EDGE padHPedgX OUTSIDE BY 15 |
| padHPspaceBad = INTERACT padHPedgSzXsp (padHPedgSzXsp AND (bondpadHPorg OR (bondpadSTG OR bondpadWLBI))) |
| padHPedgSzXspCu = EXPAND EDGE padHPcuedgX OUTSIDE BY 7 |
| padHPspaceBadCu = INTERACT padHPedgSzXspCu (padHPedgSzXspCu AND (bondpadHPcu OR (bondpadSTG OR bondpadWLBI))) |
| padWLBIedgSzXsp = EXPAND EDGE padWLBIedgX OUTSIDE BY 50 |
| padWLBIspaceBad = INTERACT padWLBIedgSzXsp (padWLBIedgSzXsp AND bondpadWLBI) |
| padSTGedgSzXsp = EXPAND EDGE padSTGedgX OUTSIDE BY 30 |
| padSTGspaceBad = INTERACT padSTGedgSzXsp (padSTGedgSzXsp AND bondpadSTG) |
| "r_1357_pad.1.2" { |
| @ pad.1.2: 8 min space of padPLFP in x direction to padPLFP/HP/STG/WLBI |
| COPY padFPspaceBad |
| } |
| "r_1358_pad.2.2" { |
| @ pad.2.2: 15 min space of padPLHPorg in x direction to padPLHP/STG/WLBI |
| COPY padHPspaceBad |
| } |
| "r_1359_pad.2.2a" { |
| @ pad.2.2a: 7 min space of padPLHPcu in x direction to padPLHPcu/STG/WLBI |
| COPY padHPspaceBadCu |
| } |
| "r_1360_pad.3.2" { |
| @ pad.3.2: 50 min space of padPLWLBI in x direction to padPLSTG/WLBI |
| COPY padWLBIspaceBad |
| } |
| "r_1361_pad.4.2" { |
| @ pad.4.2: 30 min space of padPLSTG in x direction to padPLSTG |
| COPY padSTGspaceBad |
| } |
| maxBondPadWidth1 = INTERNAL BONDPAD <= 150.0 ABUT < 90 SINGULAR PARALLEL ONLY OPPOSITE REGION |
| maxBondPadWidth2 = INTERACT BONDPAD (BONDPAD AND maxBondPadWidth1) |
| maxBondPadWidthErr = BONDPAD NOT maxBondPadWidth2 |
| BondPadWidthDiff = BONDPAD NOT maxBondPadWidth1 |
| maxBondPadWidthErr1 = INTERACT BONDPAD (BONDPAD AND BondPadWidthDiff) == 2 |
| errMaxBondPadWidth = maxBondPadWidthErr OR maxBondPadWidthErr1 |
| "r_1362_pad.9.1" { |
| @ pad.9.1: 150.0um Max Width/Length of bond pad |
| COPY errMaxBondPadWidth |
| } |
| padCenterAllX = padCenter AND (BONDPAD AND padX) |
| padCenterAllY = padCenter AND (BONDPAD AND padY) |
| padCenterAllxSz = EXPAND EDGE (ANGLE padCenterAllX == 90) OUTSIDE BY 200000 |
| padCenterAllySz = EXPAND EDGE (ANGLE padCenterAllY == 0) OUTSIDE BY 200000 |
| padCenterDieX = (padCenterAllX OR padCenterAllxSz) AND solid_seal |
| padCenterDieY = (padCenterAllY OR padCenterAllySz) AND solid_seal |
| padCenterinDieXw = INTERNAL padCenterDieX == 0.2 ABUT < 90 OPPOSITE PARALLEL REGION |
| padCenterinDieYw = INTERNAL padCenterDieY == 0.2 ABUT < 90 OPPOSITE PARALLEL REGION |
| padCenterinDieXsp = EXTERNAL padCenterDieX < 9.0 ABUT < 90 SINGULAR REGION |
| padCenterinDieYsp = EXTERNAL padCenterDieY < 9.0 ABUT < 90 SINGULAR REGION |
| padCenterinDieXwBad = padCenterDieX NOT padCenterinDieXw |
| padCenterinDieYwBad = padCenterDieY NOT padCenterinDieYw |
| padCenterinDieXspBad = padCenterinDieXsp OR (INTERACT BONDPAD (BONDPAD AND (INTERACT padCenterAllX padCenterinDieXsp))) |
| padCenterinDieYspBad = padCenterinDieYsp OR (INTERACT BONDPAD (BONDPAD AND (INTERACT padCenterAllY padCenterinDieYsp))) |
| padCenterSTGxySz = EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllX) == 0) OUTSIDE BY 5000 |
| padCenterSTGyySz = EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllY) == 90) OUTSIDE BY 5000 |
| padCenterSTGinDieXy = (padCenterAllX OR padCenterSTGxySz) AND solid_seal |
| padCenterSTGinDieYy = (padCenterAllY OR padCenterSTGyySz) AND solid_seal |
| "r_1363_pad_6_2" { |
| @ pad_6_2: 39.8 min. spacing of padCenterSTGinDieXy |
| EXTERNAL padCenterSTGinDieXy < 39.8 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE |
| } |
| "r_1364_pad_6_2" { |
| @ pad_6_2: 39.8 min. spacing of padCenterSTGinDieYy |
| EXTERNAL padCenterSTGinDieYy < 39.8 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE |
| } |
| padCenterSTGxxSz = EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllX) == 90) OUTSIDE BY 5000 |
| padCenterSTGinDieXx = (padCenterAllX OR padCenterSTGxxSz) AND solid_seal |
| padCenterinDieXspSTG = EXTERNAL padCenterSTGinDieXx < 9.0 ABUT < 90 SINGULAR REGION |
| padCenterinDieXspSTGGood = padCenterSTGinDieXx NOT padCenterinDieXspSTG |
| padSTGinDieXsp = INTERACT bondPadSTG (bondPadSTG AND (INTERACT (padCenterAllX AND bondPadSTG) padCenterinDieXspSTGGood)) |
| "r_1365_pad_5_2_4" { |
| @ pad_5_2_4: 9 min. spacing of padSTGinDieXsp & bondPadSTG |
| EXTERNAL padSTGinDieXsp bondPadSTG < 9.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| bondpadSTGscribe = EXPAND EDGE padSTGedgX OUTSIDE BY 284 |
| bondpadFPscribe = EXPAND EDGE padFPedgX OUTSIDE BY 200 |
| bondpadHPscribe = EXPAND EDGE padHPedgX OUTSIDE BY 200 |
| bondpadWLBIscribe = EXPAND EDGE padWLBIedgX OUTSIDE BY 200 |
| outsideSEALedge = EXPAND EDGE (solid_seal COINCIDENT EDGE SEALID) OUTSIDE BY 0.005 |
| bondpadSTGscribeBad = INTERACT bondpadSTGscribe (bondpadSTGscribe AND outsideSEALedge) |
| bondpadFPscribeBad = INTERACT bondpadFPscribe (bondpadFPscribe AND outsideSEALedge) |
| bondpadHPscribeBad = INTERACT bondpadHPscribe (bondpadHPscribe AND outsideSEALedge) |
| bondpadWLBIscribeBad = INTERACT bondpadWLBIscribe (bondpadWLBIscribe AND outsideSEALedge) |
| "r_1366_pad.7.2.1" { |
| @ pad.7.2.1: 284 min space of padPLSTG in x direction to adjacent scribe |
| COPY bondpadSTGscribeBad |
| } |
| "r_1367_pad.7.2.2" { |
| @ pad.7.2.2: 200 min space of padPLFP in x direction to adjacent scribe |
| COPY bondpadFPscribeBad |
| } |
| "r_1368_pad.7.2.2" { |
| @ pad.7.2.2: 200 min space of padPLWLBI in x direction to adjacent scribe |
| COPY bondpadWLBIscribeBad |
| } |
| pmmInInd = pmm AND inductor |
| "r_1369_cupad.1" { |
| @ cupad.1: 5 min. width of pad opening inside inductor |
| INTERNAL padInInd < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1370_cupad.2" { |
| @ cupad.2: 0 min. enclosure of pad opening inside inductor by pmm |
| q0padInIndand = padInInd AND pmm |
| padInInd NOT pmm |
| } |
| "r_1371_cupad.2" { |
| @ cupad.2: pad opening inside inductor must be enclosed by pmm |
| padInInd NOT pmm |
| } |
| "r_1372_cupad.3" { |
| @ cupad.3: 2.7 min. enclosure of pad opening inside inductor by met5 |
| q1padInIndand = padInInd AND met5 |
| ENCLOSURE q1padInIndand met5 < 2.7 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1373_cupad.3" { |
| @ cupad.3: pad opening inside inductor must be enclosed by met5 |
| padInInd NOT met5 |
| } |
| "r_1374_cupad.4" { |
| @ cupad.4: 10.75 min. enclosure of pmm inside inductor by rdl |
| q0pmmInIndand = pmmInInd AND rdl |
| ENCLOSURE q0pmmInIndand rdl < 10.75 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_1375_cupad.4" { |
| @ cupad.4: pmm inside inductor must be enclosed by rdl |
| pmmInInd NOT rdl |
| } |
| FRAMEPAD = pad AND (FRAMEID OR moduleCutAREA) |
| ETESTPAD = WITH TEXT FRAMEPAD "e-test" padText |
| UTESTPAD = WITH TEXT FRAMEPAD "u-test" padText |
| RFTESTPAD = WITH TEXT FRAMEPAD "RF" padText |
| EUTESTPAD = ETESTPAD OR |
| (UTESTPAD OR RFTESTPAD) |
| FRAMEPADnoTXT = FRAMEPAD NOT (EUTESTPAD OR laser_targetCells) |
| mconOrVia = mcon OR via |
| ModulecutAndEtest = moduleCutAREA AND ETESTID |
| dieCut150 = CONVEX EDGE dieCut == 2 WITH LENGTH >= 150.0 |
| dieCutCorner = INTERNAL [dieCut150] <= 150.0 INTERSECTING ONLY ABUT == 90 |
| dieCutCornerSz = EXPAND EDGE dieCutCorner INSIDE BY 0.005 CORNER FILL |
| dieCutCornerSzOut = EXPAND EDGE dieCutCorner OUTSIDE BY 150 CORNER FILL |
| scribeJunc150 = frameBndr AND (dieCutCornerSzOut NOT (INTERACT dieCut dieCutCornerSz)) |
| realScribeLine = frameBndr NOT (INTERACT dieCut dieCutCornerSz) |
| widediff = WITH WIDTH diff >= 10.0 |
| wideScribJuncBaddiff = widediff AND scribeJunc150 |
| "r_1376_scribe.5" { |
| @ scribe.5: Wide diff >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBaddiff |
| } |
| widepoly = WITH WIDTH poly >= 10.0 |
| wideScribJuncBadpoly = widepoly AND scribeJunc150 |
| "r_1377_scribe.5" { |
| @ scribe.5: Wide poly >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadpoly |
| } |
| wideli1 = WITH WIDTH li1 >= 10.0 |
| wideScribJuncBadli1 = wideli1 AND scribeJunc150 |
| "r_1378_scribe.5" { |
| @ scribe.5: Wide li1 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadli1 |
| } |
| widemet1 = WITH WIDTH met1 >= 10.0 |
| wideScribJuncBadmet1 = widemet1 AND scribeJunc150 |
| "r_1379_scribe.5" { |
| @ scribe.5: Wide met1 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmet1 |
| } |
| widemet2 = WITH WIDTH met2 >= 10.0 |
| wideScribJuncBadmet2 = widemet2 AND scribeJunc150 |
| "r_1380_scribe.5" { |
| @ scribe.5: Wide met2 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmet2 |
| } |
| widemet3 = WITH WIDTH met3 >= 10.0 |
| wideScribJuncBadmet3 = widemet3 AND scribeJunc150 |
| "r_1381_scribe.5" { |
| @ scribe.5: Wide met3 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmet3 |
| } |
| widemcon = WITH WIDTH mcon >= 10.0 |
| wideScribJuncBadmcon = widemcon AND scribeJunc150 |
| "r_1382_scribe.5" { |
| @ scribe.5: Wide mcon >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmcon |
| } |
| widelicon1 = WITH WIDTH licon1 >= 10.0 |
| wideScribJuncBadlicon1 = widelicon1 AND scribeJunc150 |
| "r_1383_scribe.5" { |
| @ scribe.5: Wide licon1 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadlicon1 |
| } |
| widevia = WITH WIDTH via >= 10.0 |
| wideScribJuncBadvia = widevia AND scribeJunc150 |
| "r_1384_scribe.5" { |
| @ scribe.5: Wide via >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvia |
| } |
| widevia2 = WITH WIDTH via2 >= 10.0 |
| wideScribJuncBadvia2 = widevia2 AND scribeJunc150 |
| "r_1385_scribe.5" { |
| @ scribe.5: Wide via2 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvia2 |
| } |
| widemet4 = WITH WIDTH met4 >= 10.0 |
| wideScribJuncBadmet4 = widemet4 AND scribeJunc150 |
| "r_1386_scribe.5" { |
| @ scribe.5: Wide met4 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmet4 |
| } |
| widemet5 = WITH WIDTH met5 >= 10.0 |
| wideScribJuncBadmet5 = widemet5 AND scribeJunc150 |
| "r_1387_scribe.5" { |
| @ scribe.5: Wide met5 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmet5 |
| } |
| widevia3 = WITH WIDTH via3 >= 10.0 |
| wideScribJuncBadvia3 = widevia3 AND scribeJunc150 |
| "r_1388_scribe.5" { |
| @ scribe.5: Wide via3 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvia3 |
| } |
| widevia4 = WITH WIDTH via4 >= 10.0 |
| wideScribJuncBadvia4 = widevia4 AND scribeJunc150 |
| "r_1389_scribe.5" { |
| @ scribe.5: Wide via4 >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvia4 |
| } |
| widemm1mk = WITH WIDTH mm1mk >= 10.0 |
| wideScribJuncBadmm1mk = widemm1mk AND scribeJunc150 |
| "r_1390_scribe.5" { |
| @ scribe.5: Wide mm1mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmm1mk |
| } |
| widemm2mk = WITH WIDTH mm2mk >= 10.0 |
| wideScribJuncBadmm2mk = widemm2mk AND scribeJunc150 |
| "r_1391_scribe.5" { |
| @ scribe.5: Wide mm2mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmm2mk |
| } |
| widemm3mk = WITH WIDTH mm3mk >= 10.0 |
| wideScribJuncBadmm3mk = widemm3mk AND scribeJunc150 |
| "r_1392_scribe.5" { |
| @ scribe.5: Wide mm3mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmm3mk |
| } |
| widep1mmk = WITH WIDTH p1mmk >= 10.0 |
| wideScribJuncBadp1mmk = widep1mmk AND scribeJunc150 |
| "r_1393_scribe.5" { |
| @ scribe.5: Wide p1mmk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadp1mmk |
| } |
| widefommk = WITH WIDTH fommk >= 10.0 |
| wideScribJuncBadfommk = widefommk AND scribeJunc150 |
| "r_1394_scribe.5" { |
| @ scribe.5: Wide fommk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadfommk |
| } |
| widectm1mk = WITH WIDTH ctm1mk >= 10.0 |
| wideScribJuncBadctm1mk = widectm1mk AND scribeJunc150 |
| "r_1395_scribe.5" { |
| @ scribe.5: Wide ctm1mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadctm1mk |
| } |
| widelicm1mk = WITH WIDTH licm1mk >= 10.0 |
| wideScribJuncBadlicm1mk = widelicm1mk AND scribeJunc150 |
| "r_1396_scribe.5" { |
| @ scribe.5: Wide licm1mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadlicm1mk |
| } |
| wideli1mmk = WITH WIDTH li1mmk >= 10.0 |
| wideScribJuncBadli1mmk = wideli1mmk AND scribeJunc150 |
| "r_1397_scribe.5" { |
| @ scribe.5: Wide li1mmk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadli1mmk |
| } |
| widevimmk = WITH WIDTH vimmk >= 10.0 |
| wideScribJuncBadvimmk = widevimmk AND scribeJunc150 |
| "r_1398_scribe.5" { |
| @ scribe.5: Wide vimmk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvimmk |
| } |
| widevim2mk = WITH WIDTH vim2mk >= 10.0 |
| wideScribJuncBadvim2mk = widevim2mk AND scribeJunc150 |
| "r_1399_scribe.5" { |
| @ scribe.5: Wide vim2mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvim2mk |
| } |
| widemm4mk = WITH WIDTH mm4mk >= 10.0 |
| wideScribJuncBadmm4mk = widemm4mk AND scribeJunc150 |
| "r_1400_scribe.5" { |
| @ scribe.5: Wide mm4mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmm4mk |
| } |
| widemm5mk = WITH WIDTH mm5mk >= 10.0 |
| wideScribJuncBadmm5mk = widemm5mk AND scribeJunc150 |
| "r_1401_scribe.5" { |
| @ scribe.5: Wide mm5mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadmm5mk |
| } |
| widevim3mk = WITH WIDTH vim3mk >= 10.0 |
| wideScribJuncBadvim3mk = widevim3mk AND scribeJunc150 |
| "r_1402_scribe.5" { |
| @ scribe.5: Wide vim3mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvim3mk |
| } |
| widevim4mk = WITH WIDTH vim4mk >= 10.0 |
| wideScribJuncBadvim4mk = widevim4mk AND scribeJunc150 |
| "r_1403_scribe.5" { |
| @ scribe.5: Wide vim4mk >= 10.0x10.0um within 150.0 of scribe junction |
| COPY wideScribJuncBadvim4mk |
| } |
| "r_1404_scribe.6a" { |
| @ scribe.6a: pad inside frame or moduleCut without text label |
| COPY FRAMEPADnoTXT |
| } |
| "r_1405_scribe.6d" { |
| @ scribe.6d: mconOrVia must not overlap EUTESTPAD |
| mconOrVia AND EUTESTPAD |
| } |
| "r_1406_scribe.6e" { |
| @ scribe.6e: EUTESTPAD must be enclosed by areaid module cut AND areaid etest |
| EUTESTPAD NOT ModulecutAndEtest |
| } |
| err_stradMod_nwell = CUT nwell (INTERACT moduleCutAREA ETESTPAD) |
| "r_1407_scribe.7" { |
| @ scribe.7: nwell drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_nwell |
| } |
| err_stradMod_diff = CUT diff (INTERACT moduleCutAREA ETESTPAD) |
| "r_1408_scribe.7" { |
| @ scribe.7: diff drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_diff |
| } |
| err_stradMod_dnwell = CUT dnwell (INTERACT moduleCutAREA ETESTPAD) |
| "r_1409_scribe.7" { |
| @ scribe.7: dnwell drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_dnwell |
| } |
| err_stradMod_tap = CUT tap (INTERACT moduleCutAREA ETESTPAD) |
| "r_1410_scribe.7" { |
| @ scribe.7: tap drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_tap |
| } |
| err_stradMod_lvtn = CUT lvtn (INTERACT moduleCutAREA ETESTPAD) |
| "r_1411_scribe.7" { |
| @ scribe.7: lvtn drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_lvtn |
| } |
| err_stradMod_hvtp = CUT hvtp (INTERACT moduleCutAREA ETESTPAD) |
| "r_1412_scribe.7" { |
| @ scribe.7: hvtp drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_hvtp |
| } |
| err_stradMod_hvi = CUT hvi (INTERACT moduleCutAREA ETESTPAD) |
| "r_1413_scribe.7" { |
| @ scribe.7: hvi drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_hvi |
| } |
| err_stradMod_tunm = CUT tunm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1414_scribe.7" { |
| @ scribe.7: tunm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_tunm |
| } |
| err_stradMod_poly = CUT poly (INTERACT moduleCutAREA ETESTPAD) |
| "r_1415_scribe.7" { |
| @ scribe.7: poly drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_poly |
| } |
| err_stradMod_npc = CUT npc (INTERACT moduleCutAREA ETESTPAD) |
| "r_1416_scribe.7" { |
| @ scribe.7: npc drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_npc |
| } |
| err_stradMod_nsdm = CUT nsdm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1417_scribe.7" { |
| @ scribe.7: nsdm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_nsdm |
| } |
| err_stradMod_psdm = CUT psdm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1418_scribe.7" { |
| @ scribe.7: psdm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_psdm |
| } |
| err_stradMod_licon1 = CUT licon1 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1419_scribe.7" { |
| @ scribe.7: licon1 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_licon1 |
| } |
| err_stradMod_li1 = CUT li1 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1420_scribe.7" { |
| @ scribe.7: li1 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_li1 |
| } |
| err_stradMod_mcon = CUT mcon (INTERACT moduleCutAREA ETESTPAD) |
| "r_1421_scribe.7" { |
| @ scribe.7: mcon drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_mcon |
| } |
| err_stradMod_met1 = CUT met1 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1422_scribe.7" { |
| @ scribe.7: met1 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_met1 |
| } |
| err_stradMod_via = CUT via (INTERACT moduleCutAREA ETESTPAD) |
| "r_1423_scribe.7" { |
| @ scribe.7: via drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_via |
| } |
| err_stradMod_met2 = CUT met2 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1424_scribe.7" { |
| @ scribe.7: met2 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_met2 |
| } |
| err_stradMod_vhvi = CUT vhvi (INTERACT moduleCutAREA ETESTPAD) |
| "r_1425_scribe.7" { |
| @ scribe.7: vhvi drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_vhvi |
| } |
| err_stradMod_via2 = CUT via2 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1426_scribe.7" { |
| @ scribe.7: via2 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_via2 |
| } |
| err_stradMod_met3 = CUT met3 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1427_scribe.7" { |
| @ scribe.7: met3 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_met3 |
| } |
| err_stradMod_via3 = CUT via3 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1428_scribe.7" { |
| @ scribe.7: via3 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_via3 |
| } |
| err_stradMod_met4 = CUT met4 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1429_scribe.7" { |
| @ scribe.7: met4 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_met4 |
| } |
| err_stradMod_via4 = CUT via4 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1430_scribe.7" { |
| @ scribe.7: via4 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_via4 |
| } |
| err_stradMod_met5 = CUT met5 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1431_scribe.7" { |
| @ scribe.7: met5 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_met5 |
| } |
| err_stradMod_nsm = CUT nsm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1432_scribe.7" { |
| @ scribe.7: nsm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_nsm |
| } |
| err_stradMod_pad = CUT pad (INTERACT moduleCutAREA ETESTPAD) |
| "r_1433_scribe.7" { |
| @ scribe.7: pad drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_pad |
| } |
| err_stradMod_ldntm = CUT ldntm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1434_scribe.7" { |
| @ scribe.7: ldntm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_ldntm |
| } |
| err_stradMod_hvntm = CUT hvntm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1435_scribe.7" { |
| @ scribe.7: hvntm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_hvntm |
| } |
| err_stradMod_pmm = CUT pmm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1436_scribe.7" { |
| @ scribe.7: pmm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_pmm |
| } |
| err_stradMod_pnp = CUT pnp (INTERACT moduleCutAREA ETESTPAD) |
| "r_1437_scribe.7" { |
| @ scribe.7: pnp drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_pnp |
| } |
| err_stradMod_capacitor = CUT capacitor (INTERACT moduleCutAREA ETESTPAD) |
| "r_1438_scribe.7" { |
| @ scribe.7: capacitor drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_capacitor |
| } |
| err_stradMod_ncm = CUT ncm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1439_scribe.7" { |
| @ scribe.7: ncm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_ncm |
| } |
| err_stradMod_pmm2 = CUT pmm2 (INTERACT moduleCutAREA ETESTPAD) |
| "r_1440_scribe.7" { |
| @ scribe.7: pmm2 drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_pmm2 |
| } |
| err_stradMod_inductor = CUT inductor (INTERACT moduleCutAREA ETESTPAD) |
| "r_1441_scribe.7" { |
| @ scribe.7: inductor drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_inductor |
| } |
| err_stradMod_rdl = CUT rdl (INTERACT moduleCutAREA ETESTPAD) |
| "r_1442_scribe.7" { |
| @ scribe.7: rdl drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_rdl |
| } |
| err_stradMod_rpm = CUT (rpm OR urpm) (INTERACT moduleCutAREA ETESTPAD) |
| "r_1443_scribe.7" { |
| @ scribe.7: rpm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_rpm |
| } |
| err_stradMod_hvtr = CUT hvtr (INTERACT moduleCutAREA ETESTPAD) |
| "r_1444_scribe.7" { |
| @ scribe.7: hvtr drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_hvtr |
| } |
| err_stradMod_ubm = CUT ubm (INTERACT moduleCutAREA ETESTPAD) |
| "r_1445_scribe.7" { |
| @ scribe.7: ubm drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_ubm |
| } |
| err_stradMod_bump = CUT bump (INTERACT moduleCutAREA ETESTPAD) |
| "r_1446_scribe.7" { |
| @ scribe.7: bump drawn layer cannot straddle areaid:ModuleCut |
| COPY err_stradMod_bump |
| } |
| ETESTPAD_67Edges = EXPAND EDGE (LENGTH ETESTPAD == 67.0) OUTSIDE BY 0.005 |
| ETESTPAD_35Edges = EXPAND EDGE (LENGTH ETESTPAD == 35.0) OUTSIDE BY 0.005 |
| ETESTPAD_67 = TOUCH ETESTPAD ETESTPAD_67Edges == 4 |
| ETESTPAD_35 = TOUCH ETESTPAD ETESTPAD_35Edges == 4 |
| err_scribe_8 = INTERACT (INTERACT moduleCutAREA (moduleCutAREA AND ETESTPAD_67)) ((INTERACT moduleCutAREA (moduleCutAREA AND ETESTPAD_67)) AND ETESTPAD_35) |
| err_scribe_9 = ETESTPAD NOT (ETESTPAD_67 OR ETESTPAD_35) |
| "r_1447_scribe.8" { |
| @ scribe.8: Etest-pad-67 and Etest-pad-35 should not exist in the same module |
| COPY err_scribe_8 |
| } |
| "r_1448_scribe.9" { |
| @ scribe.9: Etest pad Width and Length is either 67.00 um or 35.00um |
| COPY err_scribe_9 |
| } |
| ETESTPAD_spcless905 = NOT CUT (EXTERNAL ETESTPAD_67 < 90.5 ABUT < 90 SINGULAR PARALLEL OPPOSITE REGION) ETESTID |
| ETESTPADSz = SIZE ETESTPAD_67 BY (90.5 / 2) INSIDE OF ETESTID |
| moduleCutAREA_err = ETESTPADSz AND (INTERACT ETESTID (INTERACT ETESTPADSz ETESTPAD_67) > 1) |
| "r_1449_scribe.10" { |
| @ scribe.10: Min/Max Spacing between Etest pad (67um*67um) with in same module should be 90.5um |
| COPY ETESTPAD_spcless905 |
| } |
| "r_1450_scribe.10" { |
| @ scribe.10: Min/MaxSpacing between Etest pad (67um*67um)with in same module should be 90.5um |
| COPY moduleCutAREA_err |
| } |
| ETESTPAD_spcless55 = NOT CUT (EXTERNAL ETESTPAD_35 < 55.0 ABUT < 90 SINGULAR PARALLEL OPPOSITE REGION) ETESTID |
| ETESTPADSz1 = SIZE ETESTPAD_35 BY (55.0 / 2) INSIDE OF ETESTID |
| moduleCutAREA_err1 = ETESTPADSz1 AND (INTERACT ETESTID (INTERACT ETESTPADSz1 ETESTPAD_35) > 1) |
| "r_1451_scribe.11" { |
| @ scribe.11: Min/Max Spacing between Etest pad (35um*35um) with in same module should be 55um |
| COPY ETESTPAD_spcless55 |
| } |
| "r_1452_scribe.11" { |
| @ scribe.11: Min/MaxSpacing between Etest pad (35um*35um)with in same module should be 55um |
| COPY moduleCutAREA_err1 |
| } |
| "r_1453_scribe.12" { |
| @ scribe.12: 7.5 min. enclosure of ETESTPAD by areaid module cut |
| q0ETESTPADand = ETESTPAD AND moduleCutAREA |
| ENCLOSURE q0ETESTPADand moduleCutAREA < 7.5 MEASURE ALL ABUT < 90 REGION |
| } |
| met1_badETESTmet = INTERACT ETESTPAD (ETESTPAD NOT met1) |
| ETESTPAD_met1 = ETESTPAD NOT met1_badETESTmet |
| "r_1454_scribe.13" { |
| @ scribe.13: 2.50um min. enclosure of Etest pad by met1 |
| COPY met1_badETESTmet |
| } |
| "r_1455_scribe.13" { |
| @ scribe.13: 2.5 min. enclosure of ETESTPAD_met1 by met1 |
| q0ETESTPAD_met1and = ETESTPAD_met1 AND met1 |
| ENCLOSURE q0ETESTPAD_met1and met1 < 2.5 MEASURE ALL ABUT < 90 REGION |
| } |
| met2_badETESTmet = INTERACT ETESTPAD (ETESTPAD NOT met2) |
| ETESTPAD_met2 = ETESTPAD NOT met2_badETESTmet |
| "r_1456_scribe.13" { |
| @ scribe.13: 2.50um min. enclosure of Etest pad by met2 |
| COPY met2_badETESTmet |
| } |
| "r_1457_scribe.13" { |
| @ scribe.13: 2.5 min. enclosure of ETESTPAD_met2 by met2 |
| q0ETESTPAD_met2and = ETESTPAD_met2 AND met2 |
| ENCLOSURE q0ETESTPAD_met2and met2 < 2.5 MEASURE ALL ABUT < 90 REGION |
| } |
| met3_badETESTmet = INTERACT ETESTPAD (ETESTPAD NOT met3) |
| ETESTPAD_met3 = ETESTPAD NOT met3_badETESTmet |
| "r_1458_scribe.13" { |
| @ scribe.13: 2.50um min. enclosure of Etest pad by met3 |
| COPY met3_badETESTmet |
| } |
| "r_1459_scribe.13" { |
| @ scribe.13: 2.5 min. enclosure of ETESTPAD_met3 by met3 |
| q0ETESTPAD_met3and = ETESTPAD_met3 AND met3 |
| ENCLOSURE q0ETESTPAD_met3and met3 < 2.5 MEASURE ALL ABUT < 90 REGION |
| } |
| met4_badETESTmet = INTERACT ETESTPAD (ETESTPAD NOT met4) |
| ETESTPAD_met4 = ETESTPAD NOT met4_badETESTmet |
| "r_1460_scribe.13" { |
| @ scribe.13: 2.50um min. enclosure of Etest pad by met4 |
| COPY met4_badETESTmet |
| } |
| "r_1461_scribe.13" { |
| @ scribe.13: 2.5 min. enclosure of ETESTPAD_met4 by met4 |
| q0ETESTPAD_met4and = ETESTPAD_met4 AND met4 |
| ENCLOSURE q0ETESTPAD_met4and met4 < 2.5 MEASURE ALL ABUT < 90 REGION |
| } |
| met5_badETESTmet = INTERACT ETESTPAD (ETESTPAD NOT met5) |
| ETESTPAD_met5 = ETESTPAD NOT met5_badETESTmet |
| "r_1462_scribe.13" { |
| @ scribe.13: 2.50um min. enclosure of Etest pad by met5 |
| COPY met5_badETESTmet |
| } |
| "r_1463_scribe.13" { |
| @ scribe.13: 2.5 min. enclosure of ETESTPAD_met5 by met5 |
| q0ETESTPAD_met5and = ETESTPAD_met5 AND met5 |
| ENCLOSURE q0ETESTPAD_met5and met5 < 2.5 MEASURE ALL ABUT < 90 REGION |
| } |
| err_etest_14 = INTERNAL UTESTPAD < 10.0 PARALLEL OPPOSITE REGION |
| "r_1464_scribe.14" { |
| @ scribe.14: Minimum Utest pad Width and Length is 10um |
| COPY err_etest_14 |
| } |
| err_etest_15 = NOT CUT (EXTERNAL UTESTPAD < 15.0 ABUT < 90 SINGULAR REGION) moduleCutAREA |
| "r_1465_scribe.15" { |
| @ scribe.15: Min Spacing between Utest pad opening should be 15um |
| COPY err_etest_15 |
| } |
| err_etest_16 = NOT CUT (EXTERNAL UTESTPAD ETESTPAD < 7.0 ABUT < 90 SINGULAR REGION) moduleCutAREA |
| "r_1466_scribe.16" { |
| @ scribe.16: Min Spacing between Utest pad and Etest pad opening should be 7um |
| COPY err_etest_16 |
| } |
| "r_1467_scribe.17" { |
| @ scribe.17: 2.5 min. enclosure of UTESTPAD by met5 |
| q0UTESTPADand = UTESTPAD AND met5 |
| ENCLOSURE q0UTESTPADand met5 < 2.5 MEASURE ALL ABUT < 90 REGION |
| } |
| ETESTPAD_spcequal905 = NOT CUT (EXTERNAL ETESTPAD_67 == 90.5 ABUT < 90 SINGULAR PARALLEL OPPOSITE REGION) moduleCutAREA |
| sameSpcError905 = NOT INTERACT ETESTPAD_67 ETESTPAD_spcequal905 |
| "r_1468_scribe.18" { |
| @ scribe.18: Spacing of E-test pad opening to E-test pad opening in the same module must all be equal |
| COPY sameSpcError905 |
| } |
| ETESTPAD_spcequal55 = NOT CUT (EXTERNAL ETESTPAD_35 == 55.0 ABUT < 90 SINGULAR PARALLEL OPPOSITE REGION) moduleCutAREA |
| sameSpcError55 = NOT INTERACT ETESTPAD_35 ETESTPAD_spcequal55 |
| "r_1469_scribe.18" { |
| @ scribe.18: Spacing of E-test pad opening to E-test pad opening in the same module must all be equal |
| COPY sameSpcError55 |
| } |
| "r_1470_scribe.19" { |
| @ scribe.19: 76 min. width of realScribeLine |
| INTERNAL realScribeLine < 76.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| scribe20_xmpt = EXTENT CELL "s8Fab_*" "cys8_*" |
| dieCutSizeLarge = (SIZE dieCut BY 13) NOT dieCut |
| dieCutSizeSmall = (SIZE dieCut BY 3) NOT dieCut |
| padAreaToCheck = dieCutSizeLarge NOT (dieCutSizeSmall OR scribe20_xmpt) |
| padNotCoverArea = padAreaToCheck NOT pad |
| "r_1471_scribe.20" { |
| @ scribe.20: Pad.dg is to be drawn from 3.0um from scribe edge to 13.0um from scribe edge |
| COPY padNotCoverArea |
| } |
| padInScribe = (pad OR PDMmk) AND realScribeLine |
| padRing = padAreaToCheck AND pad |
| padError = padInScribe NOT (padRing OR moduleCutArea) |
| "r_1472_scribe.21" { |
| @ scribe.21: Scribe must not enclose pdm.dg nor pdm.mk except for etest pads, die pad rings |
| COPY padError |
| } |
| ///adding capm, cap2m rules |
| DISCONNECT |
| CONNECT dnwell nwell |
| CONNECT nwell tap BY NTAP |
| CONNECT tap li1 BY licon1 |
| CONNECT poly li1 BY npccon |
| CONNECT li1 met1 BY mcon |
| CONNECT met1 met2 BY via |
| CONNECT met2 met3 BY via2 |
| capm_via3 = via3 AND capm |
| via3_notcapm = via3 NOT capm_via3 |
| CONNECT met3 met4 BY via3_notcapm |
| CONNECT capm met4 BY capm_via3 |
| cap2m_via4 = via4 AND cap2m |
| via4_notcap2m = via4 NOT cap2m_via4 |
| CONNECT met4 met5 BY via4_notcap2m |
| CONNECT cap2m met5 BY cap2m_via4 |
| CONNECT met5 pad |
| CONNECT rdl pad |
| |
| m3_bot_plate = SIZE (capm AND met3) BY 0.14 |
| m3_bot_plate_err = INTERACT (EXTERNAL m3_bot_plate < 1.2 REGION) met3 > 1 BY NET |
| capmAspectRatio = RECTANGLE capm ASPECT > 20.0 |
| mimcap = capm ENCLOSE via3 |
| LshapeCap_tmp = EXPAND EDGE (CONVEX EDGE m3_bot_plate == 1) OUTSIDE BY 0.005 |
| LshapeCap_err = INTERACT m3_bot_plate LshapeCap_tmp > 1 |
| otherCap = INTERACT mimcap LshapeCap_err |
| CONNECT m3_bot_plate met3 |
| "r_734_capm.1" { |
| @ capm.1: 2 min. width of capm |
| INTERNAL capm < 2.0 ABUT < 90 SINGULAR REGION |
| } |
| "r_735_capm.2a" { |
| @ capm.2a: 0.84 min. spacing/notch of capm |
| EXTERNAL capm < 0.84 ABUT < 90 SINGULAR REGION |
| } |
| "r_736_capm.2b" { |
| @ capm.2b: 1.2 min spacing between bottom plates |
| COPY m3_bot_plate_err |
| } |
| "r_737_capm.2b" { |
| @ capm.2b: 1.2 min. spacing of m3_bot_plate & met3 |
| EXTERNAL m3_bot_plate met3 < 1.2 ABUT < 90 SINGULAR REGION NOT CONNECTED |
| } |
| "r_738_capm.3" { |
| @ capm.3: 0.14 min. enclosure of capm by met3 |
| q1capmand = capm AND met3 |
| ENCLOSURE q1capmand met3 < 0.14 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_739_capm.4" { |
| @ capm.4: 0.14 min. enclosure of via3 by capm |
| q3via3and = via3 AND capm |
| ENCLOSURE q3via3and capm < 0.14 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_740_capm.5" { |
| @ capm.5: 0.14 min. spacing of capm & via3 |
| EXTERNAL capm via3 < 0.14 ABUT < 90 SINGULAR REGION |
| } |
| "r_741_capm.6" { |
| @ capm.6: Maximum aspect ratio (L/W) is 20.00 |
| COPY capmAspectRatio |
| } |
| "r_742_capm.7" { |
| @ capm.7: Only Rectangular or L-shape Capacitors allowed |
| COPY otherCap |
| } |
| "r_743_capm.8" { |
| @ capm.8: 0.14 min. spacing of capm & via2 |
| EXTERNAL capm via2 < 0.14 ABUT < 90 SINGULAR REGION |
| } |
| "r_744_capm.8" { |
| @ capm.8: capm must not overlap via2 |
| capm AND via2 |
| } |
| "r_745_capm.9" { |
| @ capm.9: capm must be enclosed by met3 |
| capm NOT met3 |
| } |
| m4_bot_plate = SIZE (cap2m AND met4) BY 0.14 |
| m4_bot_plate_err = INTERACT (EXTERNAL m4_bot_plate < 1.2 REGION) met4 > 1 BY NET |
| cap2mAspectRatio = RECTANGLE cap2m ASPECT > 20.0 |
| mimcap2 = cap2m ENCLOSE via4 |
| LshapeCap2_tmp = EXPAND EDGE (CONVEX EDGE m4_bot_plate == 1) OUTSIDE BY 0.005 |
| LshapeCap2_err = INTERACT m4_bot_plate LshapeCap2_tmp > 1 |
| otherCap2 = INTERACT mimcap2 LshapeCap2_err |
| CONNECT m4_bot_plate met4 |
| "r_746_cap2m.1" { |
| @ cap2m.1: 2 min. width of cap2m |
| INTERNAL cap2m < 2.0 ABUT < 90 SINGULAR REGION |
| } |
| "r_747_cap2m.2a" { |
| @ cap2m.2a: 0.84 min. spacing/notch of cap2m |
| EXTERNAL cap2m < 0.84 ABUT < 90 SINGULAR REGION |
| } |
| "r_748_cap2m.2b" { |
| @ cap2m.2b: 1.2 min spacing between bottom plates |
| COPY m4_bot_plate_err |
| } |
| "r_749_cap2m.2b" { |
| @ cap2m.2b: 1.2 min. spacing of m4_bot_plate & met4 |
| EXTERNAL m4_bot_plate met4 < 1.2 ABUT < 90 SINGULAR REGION NOT CONNECTED |
| } |
| "r_750_cap2m.3" { |
| @ cap2m.3: 0.14 min. enclosure of cap2m by met4 |
| q1cap2mand = cap2m AND met4 |
| ENCLOSURE q1cap2mand met4 < 0.14 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_751_cap2m.4" { |
| @ cap2m.4: 0.20 min. enclosure of via4 by cap2m |
| q3via4and = via4 AND cap2m |
| ENCLOSURE q3via4and cap2m < 0.20 MEASURE ALL ABUT < 90 SINGULAR |
| } |
| "r_752_cap2m.5" { |
| @ cap2m.5: 0.20 min. spacing of cap2m & via4 |
| EXTERNAL cap2m via4 < 0.20 ABUT < 90 SINGULAR REGION |
| } |
| "r_753_cap2m.6" { |
| @ cap2m.6: Maximum aspect ratio (L/W) is 20.00 |
| COPY cap2mAspectRatio |
| } |
| "r_754_cap2m.7" { |
| @ cap2m.7: Only Rectangular or L-shape Capacitors allowed |
| COPY otherCap2 |
| } |
| "r_755_cap2m.8" { |
| @ cap2m.8: 0.14 min. spacing of cap2m & via3 |
| EXTERNAL cap2m via3 < 0.14 ABUT < 90 SINGULAR REGION |
| } |
| "r_756_cap2m.8" { |
| @ cap2m.8: cap2m must not overlap via3 |
| cap2m AND via3 |
| } |
| |
| /// |
| /// end drc rules |
| /// start created layer rules |
| LAYER fomDummy 1233 |
| // 1233 -> fom dummy |
| |
| LAYER ccornerID 1162 |
| // 1162 -> areaid critCorner |
| |
| LAYER critsideID 1163 |
| // 1163 -> areaid critSid |
| |
| LAYER localSub_cldrc 1234 |
| // 1234 -> areaid substrateCut |
| |
| LAYER mm5WaffDrop 1235 |
| LAYER MAP 117 DATATYPE 4 1235 // cmm5 waffleDrop |
| |
| hvNdiff = NDIFF AND hvi |
| hvNdiffRes = INTERACT hvNdiff (hvNdiff AND diffres) |
| NDIFFnoHV = NDIFF NOT hvi |
| PDIFFnoHV = PDIFF NOT hvi |
| laser_target = EXTENT CELL "*lazX_*" "*lazY_*" |
| SEALnoHoles = (DONUT SEALID) OR (HOLES SEALID) |
| SEALwithHole = HOLES SEALID |
| SEALwithHoleNoPho = SEALwithHole NOT photoArray |
| extentOrSeal = (NOT INTERACT (EXTENT) SEALwithHole) OR SEALwithHole |
| lvNwell = nwell NOT hvi |
| lvNwell_PERI = lvNwell NOT COREID |
| varacChannel = (NTAP AND poly) AND lvNwell_PERI |
| varacNwell = INTERACT nwell varacChannel |
| lvNWnoVar = lvNwell NOT varacNwell |
| lvNWnoVarNoLvtn = lvNWnoVar NOT lvtn |
| lvNWoverVar = INTERACT lvNwell (lvNwell AND varacChannel) |
| lvNWoverVarHvtp = lvNWoverVar AND hvtp |
| photoDiode_cldrc = dnwell AND photoID |
| nwellAndDnwell = dnwell AND nwell |
| nwellDnwellHoles = HOLES nwellAndDnwell INNER |
| photoArray = (nwellAndDnwell OR nwellDnwellHoles) ENCLOSE photoDiode_cldrc |
| pnpDiffSize = SIZE (PDIFF AND pnp) BY 0.03 |
| nwellPwellRes = (INTERACT nwell pwellres) OR pwellres |
| dieCut_keepout = SIZE dieCut BY 3 |
| inductor_metal = COPY 4009 |
| frameBndrNotDieCut = frameBndr NOT dieCut |
| waffleFrmBnd = (SIZE frameBndr BY -3) NOT (dieCut OR SEALnoHoles) |
| waffleFrmDensity = waffleFrmBnd NOT (WITH TEXT textlabel "falseScribe") |
| /// ******************** HVTPM ******************** |
| q0CLHVTPM = lvNWnoVarNoLvtn OR lvNWoverVarHvtp |
| CLHVTPM = q0CLHVTPM OR HVTPMdg |
| "r_1473_chvtpm.1" { |
| @ chvtpm.1: 0.38 min. width of CLHVTPM |
| INTERNAL CLHVTPM < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1474_chvtpm.2a" { |
| @ chvtpm.2a: 0.38 min. spacing/notch of CLHVTPM |
| EXTERNAL CLHVTPM < 0.38 ABUT < 90 SINGULAR REGION |
| } |
| "r_1475_chvtpm.3" { |
| @ chvtpm.3: 0 min. enclosure of ((LVnwell not overlapping Var_channel) NOT lvtn) by CLHVTPM |
| q0lvNWnoVarNoLvtnand = lvNWnoVarNoLvtn AND CLHVTPM |
| lvNWnoVarNoLvtn NOT CLHVTPM |
| } |
| "r_1476_chvtpm.4" { |
| @ chvtpm.4: 0 min. enclosure of ((LVnwell overlapping Var_channel) AND hvtp) by CLHVTPM |
| q0lvNWoverVarHvtpand = lvNWoverVarHvtp AND CLHVTPM |
| lvNWoverVarHvtp NOT CLHVTPM |
| } |
| |
| /// ******************** LVTNM ******************** |
| nwellHvtpCore = nwell AND (hvtp OR COREID) |
| clvtnm_all = lvtn OR (nwellHvtpCore OR |
| (lvNWoverVar OR LVTNMdg)) |
| LVTNMmerge = EXTERNAL clvtnm_all < 0.38 PARALLEL ONLY OPPOSITE REGION |
| q0CLLVTNM = clvtnm_all OR LVTNMmerge |
| CLLVTNM = q0CLLVTNM OR LVTNMdg |
| CLLVTNMPeri = CLLVTNM OUTSIDE COREID |
| "r_1477_clvtnm.1" { |
| @ clvtnm.1: 0.38 min. width of clvtnm in periphery |
| INTERNAL CLLVTNMPeri < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1478_clvtnm.2" { |
| @ clvtnm.2: 0.38 min. spacing/notch of CLLVTNM |
| EXTERNAL CLLVTNM < 0.38 ABUT < 90 SINGULAR REGION parallel opposite |
| } |
| |
| /// ******************** NTM ******************** |
| nwellTmp = COPY nwell |
| hvitmp = hvi NOT COREID |
| ldntmTmp = COPY ldntm |
| ntmTMP = NTMdg OR |
| (nwelltmp OR |
| (ldntmtmp OR |
| (hvitmp OR (rpm OR urpm)))) |
| NtmMergedTMP = ntmTMP OR (EXTERNAL ntmTMP < 0.7 SPACE OPPOSITE PARALLEL ONLY REGION) |
| NtmMergedTMP2 = NtmMergedTMP OR (EXTERNAL NtmMergedTMP < 0.7 NOTCH OPPOSITE PARALLEL ONLY REGION) |
| NtmMerged = NtmMergedTMP2 OR (EXTERNAL NtmMergedTMP2 < 0.7 NOTCH OPPOSITE PARALLEL ONLY REGION) |
| ntmAll = COPY NtmMerged |
| q0ntmAll = INTERNAL ntmAll (LENGTH ntmAll <= 0.0) < 0.84 REGION OPPOSITE PARALLEL ONLY |
| q1ntmAll = ntmAll NOT (q0ntmAll OUTSIDE ntmTMP) |
| q4ntmAll = COPY q1ntmAll |
| q5ntmAll = INTERNAL q4ntmAll (LENGTH q4ntmAll <= 0.0) < 0.84 REGION OPPOSITE PARALLEL ONLY |
| q6ntmAll = q4ntmAll NOT (q5ntmAll OUTSIDE ntmTMP) |
| q9ntmAll = COPY q6ntmAll |
| q0CLNTM = COPY q9ntmAll |
| "r_1479_cntm.2" { |
| @ cntm.2: 0.7 min. spacing/notch of CLNTM |
| EXTERNAL CLNTM < 0.7 ABUT < 90 SINGULAR REGION |
| } |
| CLNTM = q0CLNTM OR NTMdg |
| "r_1480_cntm.1" { |
| @ cntm.1: 0.84 min. width of CLNTM |
| INTERNAL CLNTM < 0.84 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1481_cntm.3" { |
| @ cntm.3: 0 min. enclosure of nwell by CLNTM |
| q0nwelland = nwell AND CLNTM |
| nwell NOT CLNTM |
| } |
| "r_1482_cntm.3" { |
| @ cntm.3: nwell must be enclosed by CLNTM |
| nwell NOT CLNTM |
| } |
| "r_1483_cntm.4a" { |
| @ cntm.4a: 0 min. enclosure of hvitmp by CLNTM |
| q0hvitmpand = hvitmp AND CLNTM |
| hvitmp NOT CLNTM |
| } |
| "r_1484_cntm.4a" { |
| @ cntm.4a: hvitmp must be enclosed by CLNTM |
| hvitmp NOT CLNTM |
| } |
| "r_1485_cntm.7" { |
| @ cntm.7: 0 min. enclosure of ldntm by CLNTM |
| q0ldntmand = ldntm AND CLNTM |
| ldntm NOT CLNTM |
| } |
| "r_1486_cntm.7" { |
| @ cntm.7: ldntm must be enclosed by CLNTM |
| ldntm NOT CLNTM |
| } |
| |
| /// ******************** HVNTM ******************** |
| ntapRing = (DONUT NTAP) NOT SEALID |
| ptapRing = (DONUT PTAP) NOT SEALID |
| ntapRingFilled = HOLES ntapRing |
| ptapRingFilled = HOLES ptapRing |
| doubleRingRegion = ntapRingFilled AND ptapRingFilled |
| doubleRingESD = doubleRingRegion AND ESDID |
| nDiffHoled = DONUT (SRCDRN AND NDIFF) |
| nDiffHole = HOLES nDiffHoled |
| nWellTap = nwell INSIDE NTAP |
| nWellTapInHole = nDiffHole INSIDE nWellTap |
| ESDnWellTap = nWellTapInHole AND doubleRingESD |
| diffTapButtEdge_cl = hvNdiff COINCIDENT OUTSIDE EDGE PTAP |
| ESDnWellTapHV = ESDnwellTap AND hvi |
| hvNdiffNotCore = hvNdiff NOT COREID |
| de_pFet_source = INTERACT (diff AND ENID) ((diff AND ENID) AND (INTERACT (poly AND ENID) ((poly AND ENID) AND (diff AND dnwell)))) |
| PDIFF_noENID = NOT INTERACT PDIFF ENID |
| hvNdiffSz = SIZE hvNdiffNotCore BY 0.185 |
| chvntmNdiff = hvNdiffSz NOT (EXPAND EDGE diffTapButtEdge_cl OUTSIDE BY 0.185 EXTEND BY 0.185) |
| hvntmTMP = hvntm OR |
| (HVNTMdg OR |
| (ESDnWellTapHV OR chvntmNdiff)) |
| hvNtmMergedTMP = hvntmTMP OR (EXTERNAL hvntmTMP < 0.7 SPACE OPPOSITE PARALLEL ONLY REGION) |
| hvNtmMerged = hvNtmMergedTMP OR (EXTERNAL hvNtmMergedTMP < 0.7 NOTCH OPPOSITE PARALLEL ONLY REGION) |
| hvntmKeepOut = (SIZE NDIFFnoHV BY 0.185) OR (PTAP OR (EXPAND EDGE (PTAP OUTSIDE EDGE NDIFF) OUTSIDE BY 0.185 CORNER FILL)) |
| hvntmAll = NOT INTERACT (hvNtmMerged NOT hvntmKeepOut) (INTERACT diff de_pFet_source) |
| q0hvntmAll = INTERNAL hvntmAll (LENGTH hvntmAll <= 0.185) < 0.7 REGION OPPOSITE PARALLEL ONLY |
| q1hvntmAll = hvntmAll NOT (q0hvntmAll OUTSIDE hvNdiffNotCore) |
| q4hvntmAll = COPY q1hvntmAll |
| q5hvntmAll = INTERNAL q4hvntmAll (LENGTH q4hvntmAll <= 0.185) < 0.7 REGION OPPOSITE PARALLEL ONLY |
| q6hvntmAll = q4hvntmAll NOT (q5hvntmAll OUTSIDE hvNdiffNotCore) |
| q9hvntmAll = COPY q6hvntmAll |
| q0CLHVNTM = COPY q9hvntmAll |
| CLHVNTM = q0CLHVNTM OR HVNTMdg |
| "r_1487_chvntm.1" { |
| @ chvntm.1: 0.7 min. width of CLHVNTM |
| INTERNAL CLHVNTM < 0.7 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1488_chvntm.2a" { |
| @ chvntm.2a: 0.7 min. spacing/notch of CLHVNTM |
| EXTERNAL CLHVNTM < 0.7 ABUT < 90 SINGULAR REGION |
| } |
| hvNdiffEnc = ENCLOSURE (hvNdiffNotCore OUTSIDE EDGE PTAP) CLHVNTM < 0.185 ABUT < 90 REGION |
| chvntm_3 = (NOT INTERACT ((hvNdiffNotCore NOT CLHVNTM) OR hvNdiffEnc) (ENID AND dnwell)) NOT de_pFet_source |
| "r_1489_chvntm.4" { |
| @ chvntm.4: 0.185 min. spacing of CLHVNTM & NDIFFnoHV |
| EXTERNAL CLHVNTM NDIFFnoHV < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1490_chvntm.4" { |
| @ chvntm.4: CLHVNTM must not overlap NDIFFnoHV |
| CLHVNTM AND NDIFFnoHV |
| } |
| "r_1491_chvntm.5" { |
| @ chvntm.5: 0.185 min. spacing of CLHVNTM & PDIFF_noENID |
| EXTERNAL CLHVNTM PDIFF_noENID < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE |
| } |
| "r_1492_chvntm.5" { |
| @ chvntm.5: CLHVNTM must not overlap PDIFF_noENID |
| CLHVNTM AND PDIFF_noENID |
| } |
| "r_1493_chvntm.3" { |
| @ chvntm.3: 0.185 Min Enclosure of ndiff inside hvi by chvntm |
| COPY chvntm_3 |
| } |
| PTAPnoButtE = PTAP OUTSIDE EDGE NDIFF |
| diffTapButtEdge_sz = EXPAND EDGE (NDIFF COINCIDENT OUTSIDE EDGE PTAP) OUTSIDE BY 0.005 |
| "r_1494_chvntm.6a" { |
| @ chvntm.6a: 0.185 min. spacing of CLHVNTM & p+tap (except along the diff butting edge) |
| EXTERNAL CLHVNTM PTAPnoButtE < 0.185 ABUT < 90 REGION EXCLUDE FALSE |
| } |
| "r_1495_chvntm.6a" { |
| @ chvntm.6a: CLHVNTM must not overlap ptap |
| CLHVNTM AND PTAP |
| } |
| "r_1496_chvntm.6b" { |
| @ chvntm.6b: CLHVNTM must not overlap p+diff along diff butting edge (ESDnWellTap excluded) |
| CLHVNTM AND diffTapButtEdge_sz |
| } |
| "r_1497_chvntm.7" { |
| @ chvntm.7: ESDnWellTapHV must be enclosed by CLHVNTM |
| ESDnWellTapHV NOT CLHVNTM |
| } |
| |
| /// end created layer rules |
| GROUP drcErrors "r_1497_chvntm.7" "r_1496_chvntm.6b" "r_1495_chvntm.6a" "r_1494_chvntm.6a" |
| "r_1493_chvntm.3" "r_1492_chvntm.5" "r_1491_chvntm.5" "r_1490_chvntm.4" "r_1489_chvntm.4" |
| "r_1488_chvntm.2a" "r_1487_chvntm.1" "r_1486_cntm.7" "r_1485_cntm.7" "r_1484_cntm.4a" |
| "r_1483_cntm.4a" "r_1482_cntm.3" "r_1481_cntm.3" "r_1480_cntm.1" "r_1479_cntm.2" |
| "r_1478_clvtnm.2" "r_1477_clvtnm.1" "r_1476_chvtpm.4" "r_1475_chvtpm.3" "r_1474_chvtpm.2a" |
| "r_1473_chvtpm.1" "r_1472_scribe.21" "r_1471_scribe.20" "r_1470_scribe.19" "r_1469_scribe.18" |
| "r_1468_scribe.18" "r_1467_scribe.17" "r_1466_scribe.16" "r_1465_scribe.15" "r_1464_scribe.14" |
| "r_1463_scribe.13" "r_1462_scribe.13" "r_1461_scribe.13" "r_1460_scribe.13" "r_1459_scribe.13" |
| "r_1458_scribe.13" "r_1457_scribe.13" "r_1456_scribe.13" "r_1455_scribe.13" "r_1454_scribe.13" |
| "r_1453_scribe.12" "r_1452_scribe.11" "r_1451_scribe.11" "r_1450_scribe.10" "r_1449_scribe.10" |
| "r_1448_scribe.9" "r_1447_scribe.8" "r_1446_scribe.7" "r_1445_scribe.7" "r_1444_scribe.7" |
| "r_1443_scribe.7" "r_1442_scribe.7" "r_1441_scribe.7" "r_1440_scribe.7" "r_1439_scribe.7" |
| "r_1438_scribe.7" "r_1437_scribe.7" "r_1436_scribe.7" "r_1435_scribe.7" "r_1434_scribe.7" |
| "r_1433_scribe.7" "r_1432_scribe.7" "r_1431_scribe.7" "r_1430_scribe.7" "r_1429_scribe.7" |
| "r_1428_scribe.7" "r_1427_scribe.7" "r_1426_scribe.7" "r_1425_scribe.7" "r_1424_scribe.7" |
| "r_1423_scribe.7" "r_1422_scribe.7" "r_1421_scribe.7" "r_1420_scribe.7" "r_1419_scribe.7" |
| "r_1418_scribe.7" "r_1417_scribe.7" "r_1416_scribe.7" "r_1415_scribe.7" "r_1414_scribe.7" |
| "r_1413_scribe.7" "r_1412_scribe.7" "r_1411_scribe.7" "r_1410_scribe.7" "r_1409_scribe.7" |
| "r_1408_scribe.7" "r_1407_scribe.7" "r_1406_scribe.6e" "r_1405_scribe.6d" "r_1404_scribe.6a" |
| "r_1403_scribe.5" "r_1402_scribe.5" "r_1401_scribe.5" "r_1400_scribe.5" "r_1399_scribe.5" |
| "r_1398_scribe.5" "r_1397_scribe.5" "r_1396_scribe.5" "r_1395_scribe.5" "r_1394_scribe.5" |
| "r_1393_scribe.5" "r_1392_scribe.5" "r_1391_scribe.5" "r_1390_scribe.5" "r_1389_scribe.5" |
| "r_1388_scribe.5" "r_1387_scribe.5" "r_1386_scribe.5" "r_1385_scribe.5" "r_1384_scribe.5" |
| "r_1383_scribe.5" "r_1382_scribe.5" "r_1381_scribe.5" "r_1380_scribe.5" "r_1379_scribe.5" |
| "r_1378_scribe.5" "r_1377_scribe.5" "r_1376_scribe.5" "r_1375_cupad.4" "r_1374_cupad.4" |
| "r_1373_cupad.3" "r_1372_cupad.3" "r_1371_cupad.2" "r_1370_cupad.2" "r_1369_cupad.1" |
| "r_1368_pad.7.2.2" "r_1367_pad.7.2.2" "r_1366_pad.7.2.1" "r_1365_pad_5_2_4" "r_1364_pad_6_2" |
| "r_1363_pad_6_2" "r_1362_pad.9.1" "r_1361_pad.4.2" "r_1360_pad.3.2" "r_1359_pad.2.2a" |
| "r_1358_pad.2.2" "r_1357_pad.1.2" "r_1356_pad_2/3.1" "r_1355_pad_2/3.1" "r_1354_pad_2/3.1" |
| "r_1353_pad.8.1" "r_1352_pad.7.1" "r_1351_pad.6.1a/b" "r_1350_pad.6.1b" "r_1349_pad.6.1a" |
| "r_1348_pad.6.1" "r_1347_pad.6.1" "r_1346_pad.5.1" "r_1345_pad.4.1" "r_1344_pad.3.1" |
| "r_1343_pad.2.1" "r_1342_pad.19" "r_1341_pad.19" "r_1340_pad.19" "r_1339_pad.18" |
| "r_1338_pad.17" "r_1337_pad.18" "r_1336_pad.17" "r_1335_pad.18" "r_1334_pad.17" |
| "r_1333_pad.15" "r_1332_pad.14" "r_1331_pad.13" "r_1330_pad.12" "r_1329_pad.11" |
| "r_1328_pad.11" "r_1327_pad.11" "r_1326_pad.11" "r_1325_pad.10" "r_1324_pad.7" |
| "r_1323_pad.6" "r_1322_pad.7" "r_1321_pad.6" "r_1320_pad.7" "r_1319_pad.6" |
| "r_1318_pad.7" "r_1317_pad.6" "r_1316_pad.5" "r_1315_pad.4/4a" "r_1314_pad.16" |
| "r_1313_pad.1" "r_1312_pad.1" "r_1311_mf.24" "r_1310_mf.24" "r_1309_mf.20" |
| "r_1308_mf.18" "r_1307_mf.15b" "r_1306_mf.15a" "r_1305_mf.14" "r_1304_mf.13" |
| "r_1303_mf.4" "r_1302_mf.12" "r_1301_mf.19" "r_1300_mf.19" "r_1299_mf.11" |
| "r_1298_mf.11" "r_1297_mf.10" "r_1296_mf.10" "r_1295_mf.9" "r_1294_mf.9" |
| "r_1293_mf.8" "r_1292_mf.8" "r_1291_mf.7" "r_1290_mf.7" "r_1289_mf.6" |
| "r_1288_mf.6" "r_1287_mf.22" "r_1286_mf.5" "r_1285_mf.3" "r_1284_mf.1&2" |
| "r_1283_mf.1&2" "r_1282_mf.1&2" "r_1281_mf.1&2" "r_1280_mf.1&2" "r_1279_rdl.6" |
| "r_1278_rdl.5" "r_1277_rdl.4" "r_1276_rdl.3" "r_1275_rdl.2" "r_1274_rdl.2" |
| "r_1273_rdl.1" "r_1272_fomdmy.13" "r_1271_fomdmy.12" "r_1270_fomdmy.11" "r_1269_fomdmy.10" |
| "r_1268_fomdmy.9" "r_1267_fomdmy.8" "r_1266_fomdmy.7" "r_1265_fomdmy.7" "r_1264_fomdmy.7" |
| "r_1263_fomdmy.7" "r_1262_fomdmy.6" "r_1261_fomdmy.6" "r_1260_fomdmy.4" "r_1259_fomdmy.4" |
| "r_1258_fomdmy.2" "r_1257_fomdmy_1a" "r_1256_fomdmy.1" "r_1255_metblk.7" "r_1254_metblk.7" |
| "r_1253_metblk.7" "r_1252_metblk.6" "r_1251_metblk.4" "r_1250_metblk.2" "r_1249_metblk.2" |
| "r_1248_metblk.3" "r_1247_metblk.1" "r_1246_metblk.1" "r_1245_metblk.3" "r_1244_metblk.1" |
| "r_1243_metblk.1" "r_1242_metblk.3" "r_1241_metblk.1" "r_1240_metblk.1" "r_1239_metblk.3" |
| "r_1238_metblk.1" "r_1237_metblk.1" "r_1236_metblk.3" "r_1235_metblk.1" "r_1234_metblk.1" |
| "r_1233_m4.x.1" "r_1232_m4.x.1" "r_1231_m4.x.1" "r_1230_m4.x.1" "r_1229_m4.x.1" |
| "r_1228_m4.x.1" "r_1227_m3.x.1" "r_1226_m3.x.1" "r_1225_m3.x.1" "r_1224_m3.x.1" |
| "r_1223_m3.x.1" "r_1222_m3.x.1" "r_1221_m2.x.1" "r_1220_m2.x.1" "r_1219_m2.x.1" |
| "r_1218_m2.x.1" "r_1217_m2.x.1" "r_1216_m2.x.1" "r_1215_m1.x.1" "r_1214_m1.x.1" |
| "r_1213_m1.x.1" "r_1212_m1.x.1" "r_1211_m1.x.1" "r_1210_m1.x.1" "r_1209_pad.20" |
| "r_1208_pad.20" "r_1207_X.24" "r_1206_X.22" "r_1205_X.22" "r_1204_X.22" |
| "r_1203_X.22" "r_1202_X.22" "r_1201_X.22" "r_1200_X.22" "r_1199_X.22" |
| "r_1198_X.22" "r_1197_X.22" "r_1196_X.22" "r_1195_X.22" "r_1194_X.22" |
| "r_1193_X.22" "r_1192_X.22" "r_1191_X.22" "r_1190_X.22" "r_1189_X.22" |
| "r_1188_X.22" "r_1187_X.22" "r_1186_X.22" "r_1185_X.22" "r_1184_X.22" |
| "r_1183_X.22" "r_1182_X.22" "r_1181_X.22" "r_1180_X.22" "r_1179_X.22" |
| "r_1178_hv.poly.6b" "r_1177_hv.poly.6a" "r_1176_hv.poly.4" "r_1175_hv.poly.3" "r_1174_hv.poly.2" |
| "r_1173_hv.poly.1" "r_1172_hv.poly.1" "r_1171_hv.poly.1" "r_1170_hv.diff.3b" "r_1169_hv.diff.3b" |
| "r_1168_hv.diff.3a" "r_1167_hv.diff.2" "r_1166_hv.diff.1b" "r_1165_hv.diff.1b" "r_1164_hv.diff.1a" |
| "r_1163_vhvi.8" "r_1162_vhvi.7" "r_1161_vhvi.6" "r_1160_vhvi.5" "r_1159_vhvi.4" |
| "r_1158_vhvi.3" "r_1157_vhvi.2" "r_1156_vhvi.1" "r_1155_vhvi.vhv.5" "r_1154_vpp.9" |
| "r_1153_vpp.8" "r_1152_vpp.4" "r_1151_vpp.4" "r_1150_vpp.3" "r_1149_vpp.1c" |
| "r_1148_vpp.1c" "r_1147_vpp.1c" "r_1146_vpp.1b" "r_1145_vpp.1" "r_1144_vpp.12c" |
| "r_1143_vpp.12b" "r_1142_vpp.12a" "r_1141_vpp.11" "r_1140_vpp.10" "r_1139_vpp.5c" |
| "r_1138_vpp.5b" "r_1137_vpp.5a" "r_1136_vpp.5" "r_1135_vpp.5" "r_1134_vpp.5" |
| "r_1133_vpp.5" "r_1132_areaid.1" "r_1131_crpm_nikon" "r_1130_crpm_nikon" "r_1129_cmm5_nikon" |
| "r_1128_cmm5_nikon" "r_1127_cviam4_nikon" "r_1126_cviam4_nikon" "r_1125_cmm4_nikon" "r_1124_cmm4_nikon" |
| "r_1123_cviam3_nikon" "r_1122_cviam3_nikon" "r_1121_cmm3_nikon" "r_1120_cmm3_nikon" "r_1119_cviam2_nikon" |
| "r_1118_cviam2_nikon" "r_1117_cpdm_nikon" "r_1116_cpdm_nikon" "r_1115_cnsm_nikon" "r_1114_cnsm_nikon" |
| "r_1113_cmm2_nikon" "r_1112_cmm2_nikon" "r_1111_cviam_nikon" "r_1110_cviam_nikon" "r_1109_cmm1_nikon" |
| "r_1108_cmm1_nikon" "r_1107_cctm1_nikon" "r_1106_cctm1_nikon" "r_1105_cli1m_nikon" "r_1104_cli1m_nikon" |
| "r_1103_clicm1_nikon" "r_1102_clicm1_nikon" "r_1101_cpsdm_nikon" "r_1100_cpsdm_nikon" "r_1099_cnsdm_nikon" |
| "r_1098_cnsdm_nikon" "r_1097_cnpc_nikon" "r_1096_cnpc_nikon" "r_1095_cldntm_nikon" "r_1094_cldntm_nikon" |
| "r_1093_chvntm_nikon" "r_1092_chvntm_nikon" "r_1091_cntm_nikon" "r_1090_cntm_nikon" "r_1089_cp1m_nikon" |
| "r_1088_cp1m_nikon" "r_1087_clvom_nikon" "r_1086_clvom_nikon" "r_1085_clvtnm_nikon" "r_1084_clvtnm_nikon" |
| "r_1083_chvtpm_nikon" "r_1082_chvtpm_nikon" "r_1081_cnwm_nikon" "r_1080_cnwm_nikon" "r_1079_cdnm_nikon" |
| "r_1078_cdnm_nikon" "r_1077_cfom_nikon" "r_1076_cfom_nikon" "r_1075_hvntm.10" "r_1074_hvntm.9" |
| "r_1073_hvntm.7" "r_1072_hvntm.7" "r_1071_hvntm.6b" "r_1070_hvntm.6a" "r_1069_hvntm.6a" |
| "r_1068_hvntm.5" "r_1067_hvntm.5" "r_1066_hvntm.4" "r_1065_hvntm.4" "r_1064_hvntm.3" |
| "r_1063_hvntm.2" "r_1062_hvntm.1" "r_1061_hvntm.X.1" "r_1060_rpm.10" "r_1059_rpm.10" |
| "r_1058_rpm.9" "r_1057_rpm.9" "r_1056_rpm.8" "r_1055_rpm.7" "r_1054_rpm.6" |
| "r_1053_rpm.6" "r_1052_rpm.5" "r_1051_rpm.5" "r_1050_rpm.4" "r_1049_rpm.4" |
| "r_1048_rpm.3" "r_1047_rpm.3" "r_1046_rpm.2" "r_1045_rpm.1k" "r_1044_rpm.1j" |
| "r_1043_rpm.1i" "r_1042_rpm.1h" "r_1041_rpm.1g" "r_1040_rpm.1b/c/d/e/f" "r_1039_rpm.1a" |
| "r_1038_ldntm.c6" "r_1037_ldntm.c5" "r_1036_ldntm.c4" "r_1035_ldntm.c3" "r_1034_ldntm.c2" |
| "r_1033_ldntm.c1" "r_1032_ncm.c10" "r_1031_ncm.c9" "r_1030_ncm.c9" "r_1029_ncm.c8" |
| "r_1028_ncm.8" "r_1027_ncm.7" "r_1026_ncm.2a" "r_1025_ncm.1" "r_1024_ncm.X.3" |
| "r_1023_nsm.3b" "r_1022_nsm.3b" "r_1021_nsm.3b" "r_1020_nsm.3b" "r_1019_nsm.3b" |
| "r_1018_nsm.3b" "r_1017_nsm.3b" "r_1016_nsm.3b" "r_1015_nsm.3b" "r_1014_nsm.3b" |
| "r_1013_nsm.3b" "r_1012_nsm.3b" "r_1011_nsm.3b" "r_1010_nsm.3b" "r_1009_nsm.3b" |
| "r_1008_nsm.3b" "r_1007_nsm.3b" "r_1006_nsm.3b" "r_1005_nsm.3a" "r_1004_nsm.3a" |
| "r_1003_nsm.3a" "r_1002_nsm.3a" "r_1001_nsm.3a" "r_1000_nsm.3a" "r_999_nsm.3a" |
| "r_998_nsm.3a" "r_997_nsm.3a" "r_996_nsm.3a" "r_995_nsm.3a" "r_994_nsm.3a" |
| "r_993_nsm.3a" "r_992_nsm.3a" "r_991_nsm.3a" "r_990_nsm.3a" "r_989_nsm.3a" |
| "r_988_nsm.3a" "r_987_nsm.3" "r_986_nsm.3" "r_985_nsm.3" "r_984_nsm.3" |
| "r_983_nsm.3" "r_982_nsm.3" "r_981_nsm.3" "r_980_nsm.3" "r_979_nsm.3" |
| "r_978_nsm.3" "r_977_nsm.3" "r_976_nsm.3" "r_975_nsm.3" "r_974_nsm.3" |
| "r_973_nsm.3" "r_972_nsm.3" "r_971_nsm.3" "r_970_nsm.3" "r_969_nsm.3" |
| "r_968_nsm.3" "r_967_nsm.3" "r_966_nsm.3" "r_965_nsm.3" "r_964_nsm.3" |
| "r_963_nsm.3" "r_962_nsm.3" "r_961_nsm.3" "r_960_nsm.3" "r_959_nsm.3" |
| "r_958_nsm.3" "r_957_nsm.3" "r_956_nsm.3" "r_955_nsm.3" "r_954_nsm.3" |
| "r_953_nsm.3" "r_952_nsm.3" "r_951_nsm.2" "r_950_nsm.1" "r_949_rfdiode.3" |
| "r_948_rfdiode.2" "r_947_rfdiode.1" "r_946_pwres.10" "r_945_pwres.11" "r_944_pwres.9" |
| "r_943_pwres.8b" "r_942_pwres.8a" "r_941_pwres.7b" "r_940_pwres.7a" "r_939_pwres.6" |
| "r_938_pwres.6" "r_937_pwres.5" "r_936_pwres.2" "r_935_pwres.2" "r_934_pwres.2" |
| "r_933_pwres.2" "r_932_pwres.2" "r_931_pwres.1" "r_930_extd.3" "r_929_extd.2" |
| "r_928_extd.1" "r_927_depmos.13" "r_926_depmos.12" "r_925_depmos.12" "r_924_depmos.11" |
| "r_923_depmos.10" "r_922_depmos.8" "r_921_depmos.7" "r_920_depmos.6" "r_919_depmos.5" |
| "r_918_depmos.4" "r_917_depmos.3" "r_916_depmos.2" "r_915_depmos.1" |
| "r_913_denmos.13" "r_912_denmos.13" "r_911_denmos.12" "r_910_denmos.11" "r_909_denmos.10" |
| "r_908_denmos.8" "r_907_denmos.7" "r_906_denmos.6" "r_905_denmos.5" "r_904_denmos.4" |
| "r_903_denmos.3" "r_902_denmos.2" "r_901_denmos.1" "r_900_pad.3" "r_899_pad.2" |
| "r_898_m5.4" "r_897_m5.3" "r_896_m5.3" "r_895_m5.2" "r_894_m5.1" |
| "r_893_via4.4" "r_892_via4.4" "r_891_via4.3" "r_890_via4.3" "r_889_via4.3" |
| "r_888_via4.2" "r_887_via4.1" "r_886_via4.1" "r_885_via4.1" "r_884_m4.5a" |
| "r_883_m4.5b" "r_882_m4.4a" "r_881_m4.3" "r_880_m4.3" "r_879_m4.2" |
| "r_878_m4.1" "r_877_via3.5" "r_876_via3.4" "r_875_via3.4" "r_874_via3.3" |
| "r_873_via3.3" "r_872_via3.3" "r_871_via3.2" "r_870_via3.1a" "r_869_via3.1" |
| "r_868_via3.1" "r_867_via3.1" "r_866_m3.3c" "r_865_m3.3d" "r_864_m3.6" |
| "r_863_m3.4" "r_862_m3.4" "r_861_m3.2" "r_860_m3.1" "r_859_via2.5" |
| "r_858_via2.4a" "r_857_via2.4a" "r_856_via2.4" "r_855_via2.4" "r_854_via2.3" |
| "r_853_via2.3" "r_852_via2.3" "r_851_via2.2" "r_850_via2.1a" "r_849_via2.1a" |
| "r_848_via2.1a" "r_847_via2.1d" "r_846_photo.11" "r_845_photo.10" "r_844_photo.9" |
| "r_843_photo.8" "r_842_photo.7" "r_841_photo.6" "r_840_photo.5" "r_839_photo.4" |
| "r_838_photo.3" "r_837_photo.2" "r_836_varac.8" "r_835_varac.7" "r_834_varac.6" |
| "r_833_varac.5" "r_832_varac.4" "r_831_varac.3" "r_830_varac.2" "r_829_varac.1" |
| "r_828_m2.c4" "r_827_m2.c4" "r_826_m2.7" "r_825_m2.7" "r_824_m2.6" |
| "r_823_m2.5" "r_822_m2.4" "r_821_m2.4" "r_820_m2.3a" "r_819_m2.3b" |
| "r_818_m2.2" "r_817_m2.1" "r_816_via.5c" "r_815_via.5b" "r_814_via.5a" |
| "r_813_via.4c" "r_812_via.4c" "r_811_via.4b" "r_810_via.4b" "r_809_via.4a" |
| "r_808_via.4a" "r_807_via.3" "r_806_via.3" "r_805_via.3" "r_804_via.2" |
| "r_803_via.1b" "r_802_via.1a" "r_801_via.1a" "r_800_via.1a" "r_799_m1.c1" |
| "r_798_m1.7" "r_797_m1.7" "r_796_m1.6" "r_795_m1.5" "r_794_m1.4a" |
| "r_793_m1.4a" "r_792_m1.4" "r_791_m1.4" "r_790_m1.3a" "r_789_m1.3b" |
| "r_788_m1.2" "r_787_m1.1" "r_786_ct.c2" "r_785_ct.c1" "r_784_ct.4" |
| "r_783_ct.3" "r_782_ct.3" "r_781_ct.3" "r_780_ct.2" "r_779_ct.1" |
| "r_778_ct.1" "r_777_ct.1" "r_776_li.c2" "r_775_li.c1" "r_774_li.7" |
| "r_773_li.6" "r_772_li.6" "r_771_li.5" "r_770_li.4" "r_769_li.3a" |
| "r_768_li.3" "r_767_li.3" "r_766_li.1a" "r_765_li.c1" "r_764_li.1" |
| "r_763_li.1" "r_762_licon.c4" "r_761_licon.c3" "r_760_licon.c1" "r_759_licon.19" |
| "r_758_licon.18" "r_757_licon.17" "r_756_licon.16" "r_755_licon.16" "r_754_npcon.c6" |
| "r_753_npcon.c6" "r_752_licon.15" "r_751_licon.15" "r_750_licon.14" "r_749_licon.13" |
| "r_748_licon.13" "r_747_licon.9" "r_746_licon.9" "r_745_licon.2d" "r_744_licon.2c" |
| "r_743_licon.2b" "r_742_licon.1b/c" "r_741_licon.1b/c" "r_740_licon.1b/c" "r_739_licon.1b/c" |
| "r_738_licon.1b/c" "r_737_licon.1" "r_736_licon.1" "r_735_licon.1" "r_734_licon.11d" |
| "r_733_licon.11d" "r_732_licon.11c" "r_731_licon.11c" "r_730_licon.11b" "r_729_licon.11b" |
| "r_728_licon.11a" "r_727_licon.11a" "r_726_licon.11" "r_725_licon.11" "r_724_licon.10" |
| "r_723_licon.8a" "r_722_licon.8" "r_721_licon.7" "r_720_licon.6" "r_719_licon.5c" |
| "r_718_licon.5b" "r_717_licon.5a" "r_716_licon.4" "r_715_licon.3" "r_714_licon.3" |
| "r_713_licon.3" "r_712_licon.2" "r_711_licon.2" "r_710_npc.5" "r_709_npc.4" |
| "r_708_npc.4" "r_707_npc.2" "r_706_npc.1" "r_705_poly.16" "r_704_diff.13" |
| "r_703_diff.13" "r_702_diff.13" "r_701_diff.13" "r_700_diff.13" "r_699_diff.13" |
| "r_698_diff.13" "r_697_diff.13" "r_696_diff.13" "r_695_diff.13" "r_694_diff.13" |
| "r_693_diff.13" "r_692_diff.13" "r_691_diff.13" "r_690_diff.13" "r_689_diff.13" |
| "r_688_diff.13" "r_687_diff.13" "r_686_diff.13" "r_685_diff.13" "r_684_diff.13" |
| "r_683_diff.13" "r_682_diff.13" "r_681_diff.13" "r_680_diff.13" "r_679_diff.13" |
| "r_678_diff.13" "r_677_diff.13" "r_676_diff.13" "r_675_diff.13" "r_674_diff.13" |
| "r_673_diff.13" "r_672_diff.13" "r_671_diff.13" "r_670_diff.13" "r_669_diff.13" |
| "r_668_diff.13" "r_667_diff.13" "r_666_diff.13" "r_665_diff.13" "r_664_diff.13" |
| "r_663_diff.13" "r_662_diff.13" "r_661_diff.13" "r_660_diff.13" "r_659_diff.13" |
| "r_658_diff.13" "r_657_diff.13" "r_656_diff.13" "r_655_diff.13" "r_654_diff.13" |
| "r_653_diff.13" "r_652_diff.13" "r_651_diff.13" "r_650_diff.13" "r_649_diff.13" |
| "r_648_diff.13" "r_647_diff.13" "r_646_diff.13" "r_645_diff.13" "r_644_Poly.X.1" |
| "r_643_Poly.X.1" "r_642_Poly.X.1" "r_641_Poly.X.1" "r_640_Poly.X.1" "r_639_Poly.X.1" |
| "r_638_Poly.X.1" "r_637_Poly.X.1" "r_636_Poly.X.1" "r_635_Poly.X.1" "r_634_Poly.X.1" |
| "r_633_Poly.X.1" "r_632_Poly.X.1" "r_631_Poly.X.1" "r_630_Poly.X.1" "r_629_Poly.X.1" |
| "r_628_Poly.X.1" "r_627_Poly.X.1" "r_626_Poly.X.1" "r_625_Poly.X.1" "r_624_Poly.X.1" |
| "r_623_Poly.X.1" "r_622_Poly.X.1" "r_621_Poly.X.1" "r_620_Poly.X.1" "r_619_Poly.X.1" |
| "r_618_Poly.X.1" "r_617_Poly.X.1" "r_616_Poly.X.1" "r_615_Poly.X.1" "r_614_Poly.X.1" |
| "r_613_Poly.X.1" "r_612_Poly.X.1" "r_611_Poly.X.1" "r_610_Poly.X.1" "r_609_Poly.X.1" |
| "r_608_Poly.X.1" "r_607_Poly.X.1" "r_606_Poly.X.1" "r_605_Poly.X.1" "r_604_Poly.X.1" |
| "r_603_Poly.X.1" "r_602_Poly.X.1" "r_601_Poly.X.1" "r_600_Poly.X.1" "r_599_Poly.X.1" |
| "r_598_Poly.X.1" "r_597_Poly.X.1" "r_596_Poly.X.1" "r_595_Poly.X.1" "r_594_Poly.X.1" |
| "r_593_Poly.X.1" "r_592_Poly.X.1" "r_591_Poly.X.1" "r_590_Poly.X.1" "r_589_Poly.X.1" |
| "r_588_Poly.X.1" "r_587_Poly.X.1" "r_586_Poly.X.1" "r_585_Poly.X.1" "r_584_Poly.X.1" |
| "r_583_Poly.X.1" "r_582_Poly.X.1" "r_581_Poly.X.1" "r_580_Poly.X.1" "r_579_Poly.X.1" |
| "r_578_Poly.X.1" "r_577_Poly.X.1" "r_576_Poly.X.1" "r_575_Poly.X.1" "r_574_Poly.X.1" |
| "r_573_Poly.X.1" "r_572_Poly.X.1" "r_571_Poly.X.1" "r_570_Poly.X.1" "r_569_Poly.X.1" |
| "r_568_Poly.X.1" "r_567_Poly.X.1" "r_566_Poly.X.1" "r_565_Poly.X.1" "r_564_Poly.X.1" |
| "r_563_Poly.X.1" "r_562_Poly.X.1" "r_561_Poly.X.1" "r_560_Poly.X.1" "r_559_Poly.X.1" |
| "r_558_Poly.X.1" "r_557_Poly.X.1" "r_556_Poly.X.1" "r_555_Poly.X.1" "r_554_Poly.X.1" |
| "r_553_Poly.X.1" "r_552_Poly.X.1" "r_551_Poly.X.1" "r_550_Poly.X.1" "r_549_Poly.X.1" |
| "r_548_Poly.X.1" "r_547_Poly.X.1" "r_546_Poly.X.1" "r_545_POLY.X.1" "r_544_POLY.X.1" |
| "r_543_POLY.X.1" "r_542_poly.X.1a" "r_541_poly.X.1a" "r_540_poly.X.1a" "r_539_poly.X.1a" |
| "r_538_poly.X.1a" "r_537_dnwell.6" "r_536_poly.c1" "r_535_poly.c1" "r_534_poly.15" |
| "r_533_poly.12" "r_532_poly.11" "r_531_poly.10" "r_530_poly.9" "r_529_poly.9" |
| "r_528_poly.9" "r_527_poly.8" "r_526_poly.7" "r_525_poly.6" "r_524_poly.5" |
| "r_523_poly.4" "r_522_poly.3" "r_521_poly.c2" "r_520_poly.c3" "r_519_poly.2" |
| "r_518_poly.2" "r_517_poly.1b" "r_516_poly.1a" "r_515_poly.14" "r_514_poly.13" |
| "r_513_difftap.c11" "r_512_difftap.24" "r_511_difftap.23" "r_510_difftap.22" "r_509_difftap.21" |
| "r_508_difftap.20" "r_507_difftap.19" "r_506_difftap.18" "r_505_difftap.17" "r_504_difftap.16" |
| "r_503_difftap.16" "r_502_difftap.15b" "r_501_difftap.15a" "r_500_difftap.14a" "r_499_difftap.14" |
| "r_498_nwell.10" "r_497_nwell.9" "r_496_hv.nwell.1" "r_495_nwell.8" "r_494_hvi.5" |
| "r_493_hvi.4" "r_492_hvi.2a" "r_491_hvi.1" "r_490_psd.c5b" "r_489_psd.c2b" |
| "r_488_psd.c2a" "r_487_psd.c1a" "r_486_psd.11" "r_485_psd.10b" "r_484_psd.9" |
| "r_483_psd.8" "r_482_psd.7" "r_481_psd.5b" "r_480_psd.5a" "r_479_psd.2" |
| "r_478_psd.2" "r_477_psd.c1b" "r_476_psd.1" "r_475_psd.1" "r_474_nsd.c5a" |
| "r_473_nsd.c2b" "r_472_nsd.c2a" "r_471_nsd.c1a" "r_470_nsd.11" "r_469_nsd.10a" |
| "r_468_nsd.9" "r_467_nsd.8" "r_466_nsd.7" "r_465_nsd.5b" "r_464_nsd.5a" |
| "r_463_nsd.2" "r_462_nsd.2" "r_461_nsd.c1b" "r_460_nsd.1" "r_459_nsd.1" |
| "r_458_tunm.8" "r_457_tunm.7" "r_456_tunm.6a" "r_455_tunm.5" "r_454_tunm.4" |
| "r_453_tunm.3" "r_452_tunm.2" "r_451_tunm.1" "r_450_difftap.c14" "r_449_difftap.c13" |
| "r_448_difftap.c12" "r_447_difftap.c10" "r_446_difftap.c8" "r_445_difftap.c5" "r_444_difftap.c1" |
| "r_443_difftap.11" "r_442_difftap.10" "r_441_difftap.9" "r_440_difftap.8" "r_439_difftap.7" |
| "r_438_difftap.6" "r_437_difftap.5" "r_436_difftap.4" "r_435_difftap.3" "r_434_difftap.2b" |
| "r_433_difftap.2" "r_432_difftap.c1" "r_431_difftap.1" "r_430_difftap.1" "r_429_difftap.c1" |
| "r_428_difftap.1" "r_427_difftap.1" "r_426_hvtr.3" "r_425_hvtr.2" "r_424_hvtr.2" |
| "r_423_hvtr.1" "r_422_lvtn.14" "r_421_lvtn.13" "r_420_lvtn.12" "r_419_lvtn.10" |
| "r_418_lvtn.9" "r_417_lvtn.9" "r_416_lvtn.4b" "r_415_lvtn.3b" "r_414_lvtn.3a" |
| "r_413_lvtn.2" "r_412_lvtn.1a" "r_411_hvtp.c1" "r_410_hvtp.6" "r_409_hvtp.5" |
| "r_408_hvtp.4" "r_407_hvtp.3" "r_406_hvtp.2" "r_405_hvtp.1" "r_404_nwell.7" |
| "r_403_nwell.6" "r_402_nwell.5" "r_401_nwell.5" "r_400_nwell.4" "r_399_nwell.2a" |
| "r_398_nwell.1" "r_397_dnwell.7" "r_396_dnwell.5" "r_395_dnwell.4" "r_394_dnwell.3" |
| "r_393_dnwell.2" "r_392_X.28" "r_391_X.25" "r_390_X.26" "r_389_X.23c" |
| "r_388_X.23c" "r_387_X.23c" "r_386_X.23c" "r_385_X.23c" "r_384_X.23c" |
| "r_383_X.23c" "r_382_X.23c" "r_381_X.23b" "r_380_X.21" "r_379_X.19" |
| "r_378_X.16" "r_377_X.15a" "r_376_X.15a" "r_375_X.15a" "r_374_X.15a" |
| "r_373_X.15a" "r_372_X.15a" "r_371_X.15a" "r_370_X.15a" "r_369_X.15a" |
| "r_368_X.15a" "r_367_X.15a" "r_366_X.15a" "r_365_X.15a" "r_364_X.15a" |
| "r_363_X.15a" "r_362_X.15a" "r_361_X.15a" "r_360_X.15a" "r_359_X.15a" |
| "r_358_X.15a" "r_357_X.15a" "r_356_X.15a" "r_355_X.15a" "r_354_X.15a" |
| "r_353_X.15a" "r_352_X.15a" "r_351_X.15a" "r_350_X.15a" "r_349_X.15a" |
| "r_348_X.15a" "r_347_X.15a" "r_346_X.15a" "r_345_X.15a" "r_344_X.15a" |
| "r_343_X.15a" "r_342_X.15a" "r_341_X.15a" "r_340_X.15a" "r_339_X.15a" |
| "r_338_X.15a" "r_337_X.15a" "r_336_X.15a" "r_335_X.15a" "r_334_X.15a" |
| "r_333_X.15a" "r_332_X.15a" "r_331_X.15a" "r_330_X.12e" "r_329_X.12d" |
| "r_328_X.12e" "r_327_X.12d" "r_326_X.12e" "r_325_X.12d" "r_324_X.12e" |
| "r_323_X.12d" "r_322_X.12b" "r_321_X.12a" "r_320_X.12b" "r_319_X.12a" |
| "r_318_X.12b" "r_317_X.12a" "r_316_X.12b" "r_315_X.12a" "r_314_X.12b" |
| "r_313_X.12a" "r_312_X.12b" "r_311_X.12a" "r_310_X.12b" "r_309_X.12a" |
| "r_308_X.12b" "r_307_X.12a" "r_306_X.12b" "r_305_X.12a" "r_304_X.12b" |
| "r_303_X.12a" "r_302_X.12b" "r_301_X.12a" "r_300_X.12b" "r_299_X.12a" |
| "r_298_X.12b" "r_297_X.12a" "r_296_X.12b" "r_295_X.12a" "r_294_X.12b" |
| "r_293_X.12a" "r_292_X.12b" "r_291_X.12a" "r_290_X.12b" "r_289_X.12a" |
| "r_288_X.12b" "r_287_X.12a" "r_286_X.12b" "r_285_X.12a" "r_284_X.12b" |
| "r_283_X.12a" "r_282_X.12b" "r_281_X.12a" "r_280_X.12b" "r_279_X.12a" |
| "r_278_X.12b" "r_277_X.12a" "r_276_X.12b" "r_275_X.12a" "r_274_X.12b" |
| "r_273_X.12a" "r_272_X.12b" "r_271_X.12a" "r_270_X.12b" "r_269_X.12a" |
| "r_268_X.12b" "r_267_X.12a" "r_266_X.12b" "r_265_X.12a" "r_264_X.12b" |
| "r_263_X.12a" "r_262_X.12b" "r_261_X.12a" "r_260_X.10" "r_259_X.10" |
| "r_258_X.9" "r_257_X.9" "r_256_X.9" "r_255_X.9" "r_254_X.9" |
| "r_253_X.9" "r_252_X.9" "r_251_X.9" "r_250_X.9" "r_249_X.9" |
| "r_248_X.9" "r_247_X.9" "r_246_X.9" "r_245_X.9" "r_244_X.9" |
| "r_243_X.9" "r_242_X.9" "r_241_X.9" "r_240_X.5" "r_239_X.5" |
| "r_238_X.5" "r_237_X.5" "r_236_X.5" "r_235_X.5" "r_234_X.5" |
| "r_233_X.5" "r_232_X.3a" "r_231_X.3a" "r_230_X.3a" "r_229_X.3a" |
| "r_228_X.3a" "r_227_X.3a" "r_226_X.3a" "r_225_X.3a" "r_224_X.3a" |
| "r_223_X.3a" "r_222_X.3a" "r_221_X.3a" "r_220_X.3a" "r_219_X.3a" |
| "r_218_X.3a" "r_217_X.3a" "r_216_X.3a" "r_215_X.3a" "r_214_X.3a" |
| "r_213_X.3a" "r_212_X.3a" "r_211_X.3a" "r_210_X.3a" "r_209_X.3a" |
| "r_208_X.3a" "r_207_X.3a" "r_206_X.3a" "r_205_X.3a" "r_204_X.3a" |
| "r_203_X.3a" "r_202_X.3a" "r_201_X.3a" "r_200_X.3a" "r_199_X.3a" |
| "r_198_X.3a" "r_197_X.3a" "r_196_X.3a" "r_195_X.3a" "r_194_X.3a" |
| "r_193_X.3a" "r_192_X.3a" "r_191_X.3a" "r_190_X.3a" "r_189_X.3a" |
| "r_188_X.3a" "r_187_X.3a" "r_186_X.3a" "r_185_X.3a" "r_184_X.3a" |
| "r_183_X.3a" "r_182_X.3a" "r_181_X.3a" "r_180_X.3a" "r_179_X.3a" |
| "r_178_X.3a" "r_177_X.3a" "r_176_X.3a" "r_175_X.3a" "r_174_X.3a" |
| "r_173_X.3a" "r_172_X.3a" "r_171_X.3a" "r_170_X.3a" "r_169_X.3a" |
| "r_168_X.3a" "r_167_X.3a" "r_166_X.3a" "r_165_X.3a" "r_164_X.3a" |
| "r_163_X.3a" "r_162_X.3a" "r_161_X.3a" "r_160_X.3a" "r_159_X.3a" |
| "r_158_X.3a" "r_157_X.3a" "r_156_X.3a" "r_155_X.3a" "r_154_X.3a" |
| "r_153_X.3a" "r_152_X.3a" "r_151_X.3a" "r_150_X.3a" "r_149_X.3a" |
| "r_148_X.3a" "r_147_X.3a" "r_146_X.3a" "r_145_X.3a" "r_144_X.3a" |
| "r_143_X.3a" "r_142_X.3a" "r_141_X.3a" "r_140_X.3a" "r_139_X.3a" |
| "r_138_X.3a" "r_137_X.3a" "r_136_X.3a" "r_135_X.3a" "r_134_X.3a" |
| "r_133_X.3a" "r_132_X.3a" "r_131_X.3a" "r_130_X.3a" "r_129_X.3a" |
| "r_128_X.3a" "r_127_X.3a" "r_126_X.3a" "r_125_X.3a" "r_124_X.3a" |
| "r_123_X.2a" "r_122_X.2" "r_121_X.2" "r_120_X.2" "r_119_X.2" |
| "r_118_X.2" "r_117_X.2" "r_116_X.2" "r_115_X.2" "r_114_X.2" |
| "r_113_X.2" "r_112_X.1a" "r_111_X.1a" "r_110_X.1a" "r_109_X.1a" |
| "r_108_X.1a" "r_107_X.1a" "r_106_X.1a" "r_105_X.1a" "r_104_X.1a" |
| "r_103_X.1a" "r_102_X.1a" "r_101_X.1b" "r_100_X.1b" "r_99_X.1b" |
| "r_98_X.1b" "r_97_X.1b" "r_96_X.1b" "r_95_X.1b" "r_94_X.1b" |
| "r_93_X.1b" "r_92_X.1b" "r_91_X.1b" "r_90_X.1b" "r_89_X.1b" |
| "r_88_X.1b" "r_87_X.1b" "r_86_X.1b" "r_85_X.1b" "r_84_X.1b" |
| "r_83_X.1b" "r_82_X.1b" "r_81_X.1b" "r_80_X.1b" "r_79_X.1b" |
| "r_78_X.1b" "r_77_X.1b" "r_76_X.1b" "r_75_X.1b" "r_74_X.1b" |
| "r_73_X.1b" "r_72_X.1b" "r_71_X.1b" "r_70_X.1b" "r_69_X.1b" |
| "r_68_X.1b" "r_67_X.1b" "r_66_X.1b" "r_65_X.1b" "r_64_X.1b" |
| "r_63_X.1b" "r_62_X.1b" "r_61_X.1b" "r_60_X.1b" "r_59_X.1b" |
| "r_58_X.1b" "r_57_X.1b" "r_56_X.1b" "r_55_X.1b" "r_54_X.1b" |
| "r_53_X.1b" "r_52_X.1b" "r_51_X.1b" "r_50_X.1b" "r_49_X.1b" |
| "r_48_X.1b" "r_47_X.1b" "r_46_X.1b" "r_45_X.1b" "r_44_X.1b" |
| "r_43_X.1b" "r_42_X.1b" "r_41_X.1b" "r_40_X.1b" "r_39_X.1b" |
| "r_38_X.1b" "r_37_X.1b" "r_36_X.1b" "r_35_X.1b" "r_34_X.1b" |
| "r_33_X.1b" "r_32_X.1b" "r_31_X.1b" "r_30_X.1b" "r_29_X.1b" |
| "r_28_X.1b" "r_27_X.1b" "r_26_X.1b" "r_25_X.1b" "r_24_X.1b" |
| "r_23_X.1b" "r_22_X.1b" "r_21_X.1b" "r_20_X.1b" "r_19_X.1b" |
| "r_18_X.1b" "r_17_X.1b" "r_16_X.1b" "r_15_X.1b" "r_14_X.1b" |
| "r_13_X.1b" "r_12_X.1b" "r_11_X.1b" "r_10_X.1b" "r_9_X.1b" |
| "r_8_X.1b" "r_7_X.1b" "r_6_X.1b" "r_5_X.1b" "r_4_X.1b" |
| "r_3_X.1b" "r_2_X.1b" "r_1_X.1b" "r_0_X.1b" |
| "r_113_X.1a" "r_114_X.1a" "r_233_X.3a" "r_234_X.3a" |
| "r_756_cap2m.8" "r_755_cap2m.8" |
| "r_754_cap2m.7" "r_753_cap2m.6" "r_752_cap2m.5" "r_751_cap2m.4" "r_750_cap2m.3" |
| "r_749_cap2m.2b" "r_748_cap2m.2b" "r_747_cap2m.2a" "r_746_cap2m.1" "r_745_capm.9" |
| "r_744_capm.8" "r_743_capm.8" "r_742_capm.7" "r_741_capm.6" "r_740_capm.5" |
| "r_739_capm.4" "r_738_capm.3" "r_737_capm.2b" "r_736_capm.2b" "r_735_capm.2a" |
| "r_734_capm.1" "r_1000_rpmNotSupport" |
| |
| GROUP keepLayers "k_346_nvhv_valid" "k_345_nvhv_L_2_20" "k_344_nvhv_L_0_70" "k_343_pvhv_valid" |
| "k_342_pvhv_L_2_16" "k_341_pvhv_L_0_66" "k_340_s8rf_nshort_W1p65_L0p15_M2_b_valid" "k_339_s8rf_nshort_W1p65_L0p15_M2_b_L_0_15" "k_338_s8rf_nshort_W1p65_L0p15_M2_b" |
| "k_337_s8rf_nlowvt_W1p65_L0p25_M4_b_valid" "k_336_s8rf_nlowvt_W1p65_L0p25_M4_b_L_0_25" "k_335_s8rf_nlowvt_W1p65_L0p25_M4_b" "k_334_s8rf_nshort_W1p65_L0p25_M2_b_valid" "k_333_s8rf_nshort_W1p65_L0p25_M2_b_L_0_25" |
| "k_332_s8rf_nshort_W1p65_L0p25_M2_b" "k_331_nhvesd_valid" "k_330_nhvesd_L_1_00" "k_329_nhvesd_L_0_60" "k_328_nhvesd_L_0_55" |
| "k_327_s8rf_nhv_W7p0_L0p5_M4_b_valid" "k_326_s8rf_nhv_W7p0_L0p5_M4_b_L_0_50" "k_325_s8rf_nhv_W7p0_L0p5_M4_b" "k_324_s8rf_nlowvt_W5p0_L0p18_M2_b_valid" "k_323_s8rf_nlowvt_W5p0_L0p18_M2_b_L_0_18" |
| "k_322_s8rf_nlowvt_W5p0_L0p18_M2_b" "k_321_s8rf_nshort_W3p0_L0p18_M2_b_valid" "k_320_s8rf_nshort_W3p0_L0p18_M2_b_L_0_18" "k_319_s8rf_nshort_W3p0_L0p18_M2_b" "k_318_s8rf_nlowvt_W3p0_L0p15_2F_valid" |
| "k_317_s8rf_nlowvt_W3p0_L0p15_2F_L_0_15" "k_316_s8rf_nlowvt_W3p0_L0p15_2F" "k_315_s8rf_nlowvt_W5p0_L0p18_M4_b_valid" "k_314_s8rf_nlowvt_W5p0_L0p18_M4_b_L_0_18" "k_313_s8rf_nlowvt_W5p0_L0p18_M4_b" |
| "k_312_s8rf_nlowvt_W1p65_L0p18_M4_b_valid" "k_311_s8rf_nlowvt_W1p65_L0p18_M4_b_L_0_18" "k_310_s8rf_nlowvt_W1p65_L0p18_M4_b" "k_309_s8rf_nlowvt_W5p0_L0p15_M4_b_valid" "k_308_s8rf_nlowvt_W5p0_L0p15_M4_b_L_0_15" |
| "k_307_s8rf_nlowvt_W5p0_L0p15_M4_b" "k_306_s8rf_nshort_W1p65_L0p18_M2_b_valid" "k_305_s8rf_nshort_W1p65_L0p18_M2_b_L_0_18" "k_304_s8rf_nshort_W1p65_L0p18_M2_b" "k_303_nlvtpass_valid" |
| "k_302_nlvtpass_L_0_15" "k_301_s8rf_nlowvt_W1p65_L0p18_M2_b_valid" "k_300_s8rf_nlowvt_W1p65_L0p18_M2_b_L_0_18" "k_299_s8rf_nlowvt_W1p65_L0p18_M2_b" "k_298_s8rf_nhv_W3p0_L0p5_M2_b_valid" |
| "k_297_s8rf_nhv_W3p0_L0p5_M2_b_L_0_50" "k_296_s8rf_nhv_W3p0_L0p5_M2_b" "k_295_s8rf_nshort_W3p0_L0p25_M4_b_valid" "k_294_s8rf_nshort_W3p0_L0p25_M4_b_L_0_25" "k_293_s8rf_nshort_W3p0_L0p25_M4_b" |
| "k_292_s8rf_nhv_W5p0_L0p5_M10_b_valid" "k_291_s8rf_nhv_W5p0_L0p5_M10_b_L_0_50" "k_290_s8rf_nhv_W5p0_L0p5_M10_b" "k_289_s8rf_nlowvt_W1p65_L0p25_M2_b_valid" "k_288_s8rf_nlowvt_W1p65_L0p25_M2_b_L_0_25" |
| "k_287_s8rf_nlowvt_W1p65_L0p25_M2_b" "k_286_s8rf_nshort_W5p0_L0p18_M4_b_valid" "k_285_s8rf_nshort_W5p0_L0p18_M4_b_L_0_18" "k_284_s8rf_nshort_W5p0_L0p18_M4_b" "k_283_nshort_valid" |
| "k_282_nshort_L_20_0" "k_281_nshort_L_8_00" "k_280_nshort_L_4_00" "k_279_nshort_L_2_00" "k_278_nshort_L_1_00" |
| "k_277_nshort_L_0_50" "k_276_nshort_L_0_25" "k_275_nshort_L_0_18" "k_274_nshort_L_0_15" "k_273_s8rf_nshort_W3p0_L0p15_M4_b_valid" |
| "k_272_s8rf_nshort_W3p0_L0p15_M4_b_L_0_15" "k_271_s8rf_nshort_W3p0_L0p15_M4_b" "k_270_s8rf_nlowvt_W5p0_L0p25_M2_b_valid" "k_269_s8rf_nlowvt_W5p0_L0p25_M2_b_L_0_25" "k_268_s8rf_nlowvt_W5p0_L0p25_M2_b" |
| "k_267_nshortesd_valid" "k_266_nshortesd_L_0_18" "k_265_nshortesd_L_0_165" "k_264_s8rf_nlowvt_W5p0_L0p25_M4_b_valid" "k_263_s8rf_nlowvt_W5p0_L0p25_M4_b_L_0_25" |
| "k_262_s8rf_nlowvt_W5p0_L0p25_M4_b" "k_261_s8rf_nlowvt_W3p0_L0p25_M2_b_valid" "k_260_s8rf_nlowvt_W3p0_L0p25_M2_b_L_0_25" "k_259_s8rf_nlowvt_W3p0_L0p25_M2_b" "k_258_s8rf_nshort_W1p65_L0p15_M4_b_valid" |
| "k_257_s8rf_nshort_W1p65_L0p15_M4_b_L_0_15" "k_256_s8rf_nshort_W1p65_L0p15_M4_b" "k_255_s8rf_nlowvt_W0p84_L0p15_8F_valid" "k_254_s8rf_nlowvt_W0p84_L0p15_8F_L_0_15" "k_253_s8rf_nlowvt_W0p84_L0p15_8F" |
| "k_252_s8rf_nhv_W5p0_L0p5_M2_b_valid" "k_251_s8rf_nhv_W5p0_L0p5_M2_b_L_0_50" "k_250_s8rf_nhv_W5p0_L0p5_M2_b" "k_249_s8rf_nshort_W5p0_L0p15_M2_b_valid" "k_248_s8rf_nshort_W5p0_L0p15_M2_b_L_0_15" |
| "k_247_s8rf_nshort_W5p0_L0p15_M2_b" "k_246_nhv_valid" "k_245_nhv_L_20_0" "k_244_nhv_L_8_00" "k_243_nhv_L_4_00" |
| "k_242_nhv_L_2_00" "k_241_nhv_L_1_00" "k_240_nhv_L_0_80" "k_239_nhv_L_0_60" "k_238_nhv_L_0_50" |
| "k_237_s8rf_nshort_W3p0_L0p15_M2_b_valid" "k_236_s8rf_nshort_W3p0_L0p15_M2_b_L_0_15" "k_235_s8rf_nshort_W3p0_L0p15_M2_b" "k_234_s8rf_nshort_W1p65_L0p25_M4_b_valid" "k_233_s8rf_nshort_W1p65_L0p25_M4_b_L_0_25" |
| "k_232_s8rf_nshort_W1p65_L0p25_M4_b" "k_231_s8rf_nlowvt_W3p0_L0p18_M2_b_valid" "k_230_s8rf_nlowvt_W3p0_L0p18_M2_b_L_0_18" "k_229_s8rf_nlowvt_W3p0_L0p18_M2_b" "k_228_s8rf_nhv_W3p0_L0p5_M4_b_valid" |
| "k_227_s8rf_nhv_W3p0_L0p5_M4_b_L_0_50" "k_226_s8rf_nhv_W3p0_L0p5_M4_b" "k_225_s8rf_nshort_W5p0_L0p15_M4_b_valid" "k_224_s8rf_nshort_W5p0_L0p15_M4_b_L_0_15" "k_223_s8rf_nshort_W5p0_L0p15_M4_b" |
| "k_222_sonos_e_valid" "k_221_sonos_e_L_0_50" "k_220_sonos_e_L_0_22" "k_219_s8rf_nshort_W3p0_L0p25_M2_b_valid" "k_218_s8rf_nshort_W3p0_L0p25_M2_b_L_0_25" |
| "k_217_s8rf_nshort_W3p0_L0p25_M2_b" "k_216_nlowvt_valid" "k_215_nlowvt_L_8_00" "k_214_nlowvt_L_6_00" "k_213_nlowvt_L_4_00" |
| "k_212_nlowvt_L_2_00" "k_211_nlowvt_L_1_00" "k_210_nlowvt_L_0_50" "k_209_nlowvt_L_0_25" "k_208_nlowvt_L_0_18" |
| "k_207_nlowvt_L_0_15" "k_206_s8rf_nshort_W5p0_L0p25_M2_b_valid" "k_205_s8rf_nshort_W5p0_L0p25_M2_b_L_0_25" "k_204_s8rf_nshort_W5p0_L0p25_M2_b" "k_203_s8rf_nshort_W5p0_L0p18_M2_b_valid" |
| "k_202_s8rf_nshort_W5p0_L0p18_M2_b_L_0_18" "k_201_s8rf_nshort_W5p0_L0p18_M2_b" "k_200_s8rf_nshort_W3p0_L0p18_M4_b_valid" "k_199_s8rf_nshort_W3p0_L0p18_M4_b_L_0_18" "k_198_s8rf_nshort_W3p0_L0p18_M4_b" |
| "k_197_s8rf_nlowvt_W0p84_L0p15_4F_valid" "k_196_s8rf_nlowvt_W0p84_L0p15_4F_L_0_15" "k_195_s8rf_nlowvt_W0p84_L0p15_4F" "k_194_s8rf_nlowvt_W5p0_L0p15_M2_b_valid" "k_193_s8rf_nlowvt_W5p0_L0p15_M2_b_L_0_15" |
| "k_192_s8rf_nlowvt_W5p0_L0p15_M2_b" "k_191_s8rf_nlowvt_W3p0_L0p15_M2_b_valid" "k_190_s8rf_nlowvt_W3p0_L0p15_M2_b_L_0_15" "k_189_s8rf_nlowvt_W3p0_L0p15_M2_b" "k_188_s8rf_nlowvt_W3p0_L0p25_M4_b_valid" |
| "k_187_s8rf_nlowvt_W3p0_L0p25_M4_b_L_0_25" "k_186_s8rf_nlowvt_W3p0_L0p25_M4_b" "k_185_s8rf_nlowvt_W3p0_L0p15_M4_b_valid" "k_184_s8rf_nlowvt_W3p0_L0p15_M4_b_L_0_15" "k_183_s8rf_nlowvt_W3p0_L0p15_M4_b" |
| "k_182_s8rf_nlowvt_W3p0_L0p15_8F_valid" "k_181_s8rf_nlowvt_W3p0_L0p15_8F_L_0_15" "k_180_s8rf_nlowvt_W3p0_L0p15_8F" "k_179_s8rf_nlowvt_W3p0_L0p18_M4_b_valid" "k_178_s8rf_nlowvt_W3p0_L0p18_M4_b_L_0_18" |
| "k_177_s8rf_nlowvt_W3p0_L0p18_M4_b" "k_176_s8rf_nlowvt_W1p65_L0p15_M4_b_valid" "k_175_s8rf_nlowvt_W1p65_L0p15_M4_b_L_0_15" "k_174_s8rf_nlowvt_W1p65_L0p15_M4_b" "k_173_fnpass_valid" |
| "k_172_fnpass_L_0_15" "k_171_s8rf_nlowvt_W3p0_L0p15_4F_valid" "k_170_s8rf_nlowvt_W3p0_L0p15_4F_L_0_15" "k_169_s8rf_nlowvt_W3p0_L0p15_4F" "k_168_s8rf_nshort_W1p65_L0p18_M4_b_valid" |
| "k_167_s8rf_nshort_W1p65_L0p18_M4_b_L_0_18" "k_166_s8rf_nshort_W1p65_L0p18_M4_b" "k_165_s8rf_nhv_W5p0_L0p5_M4_b_valid" "k_164_s8rf_nhv_W5p0_L0p5_M4_b_L_0_50" "k_163_s8rf_nhv_W5p0_L0p5_M4_b" |
| "k_162_ntvnative_valid" "k_161_ntvnative_L_0_80" "k_160_ntvnative_L_0_60" "k_159_ntvnative_L_0_50" "k_158_npd_valid" |
| "k_157_npd_L_0_15" "k_156_nhvnativeesd_valid" "k_155_nhvnativeesd_L_4_00" "k_154_nhvnativeesd_L_2_00" "k_153_nhvnativeesd_L_0_90" |
| "k_152_sonos_p_valid" "k_151_sonos_p_L_0_50" "k_150_sonos_p_L_0_22" "k_149_s8rf_nhv_W3p0_L0p5_M10_b_valid" "k_148_s8rf_nhv_W3p0_L0p5_M10_b_L_0_50" |
| "k_147_s8rf_nhv_W3p0_L0p5_M10_b" "k_146_s8rf_nlowvt_W1p65_L0p15_M2_b_valid" "k_145_s8rf_nlowvt_W1p65_L0p15_M2_b_L_0_15" "k_144_s8rf_nlowvt_W1p65_L0p15_M2_b" "k_143_npass_valid" |
| "k_142_npass_L_0_15" "k_141_s8rf_nshort_W5p0_L0p25_M4_b_valid" "k_140_s8rf_nshort_W5p0_L0p25_M4_b_L_0_25" "k_139_s8rf_nshort_W5p0_L0p25_M4_b" "k_138_nhvnative_valid" |
| "k_137_nhvnative_L_25_00" "k_136_nhvnative_L_8_00" "k_135_nhvnative_L_4_00" "k_134_nhvnative_L_2_00" "k_133_nhvnative_L_1_00" |
| "k_132_nhvnative_L_0_90" "k_131_s8rf_nhv_W7p0_L0p5_M10_b_valid" "k_130_s8rf_nhv_W7p0_L0p5_M10_b_L_0_50" "k_129_s8rf_nhv_W7p0_L0p5_M10_b" "k_128_s8rf_nlowvt_W0p84_L0p15_2F_valid" |
| "k_127_s8rf_nlowvt_W0p84_L0p15_2F_L_0_15" "k_126_s8rf_nlowvt_W0p84_L0p15_2F" "k_125_s8rf_nlowvt_W0p42_L0p15_2F_valid" "k_124_s8rf_nlowvt_W0p42_L0p15_2F_L_0_15" "k_123_s8rf_nlowvt_W0p42_L0p15_2F" |
| "k_122_s8rf_pmedlvt_W1p68_L0p15_2F_valid" "k_121_s8rf_pmedlvt_W1p68_L0p15_2F_L_0_15" "k_120_s8rf_pmedlvt_W1p68_L0p15_2F" "k_119_s8rf_pshort_W3p0_L0p18_M2_b_valid" "k_118_s8rf_pshort_W3p0_L0p18_M2_b_L_0_18" |
| "k_117_s8rf_pshort_W3p0_L0p18_M2_b" "k_116_phighvt_valid" "k_115_phighvt_L_20_0" "k_114_phighvt_L_8_00" "k_113_phighvt_L_4_00" |
| "k_112_phighvt_L_2_00" "k_111_phighvt_L_1_00" "k_110_phighvt_L_0_50" "k_109_phighvt_L_0_25" "k_108_phighvt_L_0_18" |
| "k_107_phighvt_L_0_15" "k_106_s8rf_pshort_W1p65_L0p15_M4_b_valid" "k_105_s8rf_pshort_W1p65_L0p15_M4_b_L_0_15" "k_104_s8rf_pshort_W1p65_L0p15_M4_b" "k_103_s8rf_pshort_W1p65_L0p18_M2_b_valid" |
| "k_102_s8rf_pshort_W1p65_L0p18_M2_b_L_0_18" "k_101_s8rf_pshort_W1p65_L0p18_M2_b" "k_100_s8rf_pmedlvt_W1p68_L0p15_4F_valid" "k_99_s8rf_pmedlvt_W1p68_L0p15_4F_L_0_15" "k_98_s8rf_pmedlvt_W1p68_L0p15_4F" |
| "k_97_s8rf_pshort_W1p65_L0p18_M4_b_valid" "k_96_s8rf_pshort_W1p65_L0p18_M4_b_L_0_18" "k_95_s8rf_pshort_W1p65_L0p18_M4_b" "k_94_s8rf_pshort_W1p68_L0p15_2F_valid" "k_93_s8rf_pshort_W1p68_L0p15_2F_L_0_15" |
| "k_92_s8rf_pshort_W1p68_L0p15_2F" "k_91_ppu_valid" "k_90_ppu_L_0_15" "k_89_pshort_valid" "k_88_pshort_L_20_0" |
| "k_87_pshort_L_8_00" "k_86_pshort_L_4_00" "k_85_pshort_L_2_00" "k_84_pshort_L_1_00" "k_83_pshort_L_0_50" |
| "k_82_pshort_L_0_25" "k_81_pshort_L_0_18" "k_80_pshort_L_0_17" "k_79_pshort_L_0_15" "k_78_s8rf_pshort_W1p65_L0p15_M2_b_valid" |
| "k_77_s8rf_pshort_W1p65_L0p15_M2_b_L_0_15" "k_76_s8rf_pshort_W1p65_L0p15_M2_b" "k_75_s8rf_pshort_W3p0_L0p25_M2_b_valid" "k_74_s8rf_pshort_W3p0_L0p25_M2_b_L_0_25" "k_73_s8rf_pshort_W3p0_L0p25_M2_b" |
| "k_72_s8rf_pshort_W5p0_L0p18_M2_b_valid" "k_71_s8rf_pshort_W5p0_L0p18_M2_b_L_0_18" "k_70_s8rf_pshort_W5p0_L0p18_M2_b" "k_69_s8rf_pshort_W3p0_L0p18_M4_b_valid" "k_68_s8rf_pshort_W3p0_L0p18_M4_b_L_0_18" |
| "k_67_s8rf_pshort_W3p0_L0p18_M4_b" "k_66_s8rf_pshort_W1p68_L0p15_4F_valid" "k_65_s8rf_pshort_W1p68_L0p15_4F_L_0_15" "k_64_s8rf_pshort_W1p68_L0p15_4F" "k_63_s8rf_pshort_W5p0_L0p18_M4_b_valid" |
| "k_62_s8rf_pshort_W5p0_L0p18_M4_b_L_0_18" "k_61_s8rf_pshort_W5p0_L0p18_M4_b" "k_60_s8rf_pshort_W3p0_L0p15_2F_valid" "k_59_s8rf_pshort_W3p0_L0p15_2F_L_0_15" "k_58_s8rf_pshort_W3p0_L0p15_2F" |
| "k_57_s8rf_pshort_W5p0_L0p15_M2_b_valid" "k_56_s8rf_pshort_W5p0_L0p15_M2_b_L_0_15" "k_55_s8rf_pshort_W5p0_L0p15_M2_b" "k_54_s8rf_pshort_W5p0_L0p15_M4_b_valid" "k_53_s8rf_pshort_W5p0_L0p15_M4_b_L_0_15" |
| "k_52_s8rf_pshort_W5p0_L0p15_M4_b" "k_51_s8rf_pshort_W3p0_L0p15_M2_b_valid" "k_50_s8rf_pshort_W3p0_L0p15_M2_b_L_0_15" "k_49_s8rf_pshort_W3p0_L0p15_M2_b" "k_48_phv_valid" |
| "k_47_phv_L_20_0" "k_46_phv_L_8_00" "k_45_phv_L_4_00" "k_44_phv_L_2_00" "k_43_phv_L_1_00" |
| "k_42_phv_L_0_80" "k_41_phv_L_0_60" "k_40_phv_L_0_50" "k_39_s8rf_pshort_W1p65_L0p25_M2_b_valid" "k_38_s8rf_pshort_W1p65_L0p25_M2_b_L_0_25" |
| "k_37_s8rf_pshort_W1p65_L0p25_M2_b" "k_36_s8rf_pshort_W0p84_L0p15_2F_valid" "k_35_s8rf_pshort_W0p84_L0p15_2F_L_0_15" "k_34_s8rf_pshort_W0p84_L0p15_2F" "k_33_plowvt_valid" |
| "k_32_plowvt_L_20_0" "k_31_plowvt_L_8_00" "k_30_plowvt_L_4_00" "k_29_plowvt_L_2_00" "k_28_plowvt_L_1_50" |
| "k_27_plowvt_L_1_00" "k_26_plowvt_L_0_50" "k_25_plowvt_L_0_35" "k_24_s8rf_pshort_W5p0_L0p25_M2_b_valid" "k_23_s8rf_pshort_W5p0_L0p25_M2_b_L_0_25" |
| "k_22_s8rf_pshort_W5p0_L0p25_M2_b" "k_21_s8rf_pshort_W5p0_L0p25_M4_b_valid" "k_20_s8rf_pshort_W5p0_L0p25_M4_b_L_0_25" "k_19_s8rf_pshort_W5p0_L0p25_M4_b" "k_18_s8rf_pshort_W3p0_L0p15_M4_b_valid" |
| "k_17_s8rf_pshort_W3p0_L0p15_M4_b_L_0_15" "k_16_s8rf_pshort_W3p0_L0p15_M4_b" "k_15_phvesd_valid" "k_14_phvesd_L_0_55" "k_13_s8rf_pshort_W1p65_L0p25_M4_b_valid" |
| "k_12_s8rf_pshort_W1p65_L0p25_M4_b_L_0_25" "k_11_s8rf_pshort_W1p65_L0p25_M4_b" "k_10_s8rf_pshort_W5p0_L0p15_2F_valid" "k_9_s8rf_pshort_W5p0_L0p15_2F_L_0_15" "k_8_s8rf_pshort_W5p0_L0p15_2F" |
| "k_7_s8rf_pshort_W3p0_L0p25_M4_b_valid" "k_6_s8rf_pshort_W3p0_L0p25_M4_b_L_0_25" "k_5_s8rf_pshort_W3p0_L0p25_M4_b" "k_4_s8rf_pmedlvt_W0p84_L0p15_2F_valid" "k_3_s8rf_pmedlvt_W0p84_L0p15_2F_L_0_15" |
| "k_2_s8rf_pmedlvt_W0p84_L0p15_2F" "k_1_rfGate" "k_0_anchor" |
| GROUP addedVias "v_14_q0_via4_NOTAreaidStdCellCore_added_above" "v_13_q0_via4_NOTAreaidStdCellCore_added_below" "v_12_q0_via4_NOTAreaidStdCellCore_added_vias" "v_11_q0_via3_NOTAreaidStdCellCore_added_above" |
| "v_10_q0_via3_NOTAreaidStdCellCore_added_below" "v_9_q0_via3_NOTAreaidStdCellCore_added_vias" "v_8_q0_via2_NOTAreaidStdCellCore_added_above" "v_7_q0_via2_NOTAreaidStdCellCore_added_below" "v_6_q0_via2_NOTAreaidStdCellCore_added_vias" |
| "v_5_q0_via_NOTAreaidStdCellCore_added_above" "v_4_q0_via_NOTAreaidStdCellCore_added_below" "v_3_q0_via_NOTAreaidStdCellCore_added_vias" "v_2_q0_mcon_NOTAreaidStdCellCore_added_above" "v_1_q0_mcon_NOTAreaidStdCellCore_added_below" |
| "v_0_q0_mcon_NOTAreaidStdCellCore_added_vias" |
| GROUP drcRecommended "s_73_chipint.2" "s_72_chipint.1" "s_71_metblk.7" "s_70_metblk.7" |
| "s_69_metblk.7" "s_68_metblk.6" "s_67_m4.x.1" "s_66_m4.x.1" "s_65_m4.x.1" |
| "s_64_m4.x.1" "s_63_m4.x.1" "s_62_m4.x.1" "s_61_m3.x.1" "s_60_m3.x.1" |
| "s_59_m3.x.1" "s_58_m3.x.1" "s_57_m3.x.1" "s_56_m3.x.1" "s_55_m2.x.1" |
| "s_54_m2.x.1" "s_53_m2.x.1" "s_52_m2.x.1" "s_51_m2.x.1" "s_50_m2.x.1" |
| "s_49_m1.x.1" "s_48_m1.x.1" "s_47_m1.x.1" "s_46_m1.x.1" "s_45_m1.x.1" |
| "s_44_m1.x.1" "s_43_X.22" "s_42_X.22" "s_41_X.22" "s_40_X.22" |
| "s_39_X.22" "s_38_X.22" "s_37_X.22" "s_36_X.22" "s_35_X.22" |
| "s_34_X.22" "s_33_X.22" "s_32_X.22" "s_31_X.22" "s_30_X.22" |
| "s_29_X.22" "s_28_X.22" "s_27_X.22" "s_26_X.22" "s_25_X.22" |
| "s_24_X.22" "s_23_X.22" "s_22_X.22" "s_21_X.22" "s_20_X.22" |
| "s_19_X.22" "s_18_X.22" "s_17_X.22" "s_16_X.22" "s_15_X.22" |
| "s_14_X.22" "s_13_X.22" "s_12_X.22" "s_11_X.22" "s_10_X.22" |
| "s_9_X.22" "s_8_m2.3c" "s_7_X.27" "s_6_X.27" "s_5_X.23f" |
| "s_4_X.18" "s_3_X.18" "s_2_X.18" "s_1_X.18" "s_0_X.18" |
| |
| /// To remove this when there are no rules checked, |
| /// pass ?dontCheckUnregisteredRules t to (CALdone) |
| GROUP unRegisteredErrors "?" |
| /// To remove this when there are no rules checked, |
| /// pass ?dontCheckUnregisteredRules t to (CALdone) |
| DRC SELECT CHECK unRegisteredErrors |
| DRC SELECT CHECK drcErrors |
| DRC SELECT CHECK keepLayers |
| DRC CHECK MAP keepLayers |
| // ASCII "$cy_calbr_rundir/keepLayer.db" |
| ASCII "keepLayer.db" |
| MAXIMUM RESULTS ALL |
| DRC SELECT CHECK addedVias |
| DRC CHECK MAP addedVias |
| // ASCII "$cy_calbr_rundir/addedVias.db" |
| ASCII "addedVias.db" |
| MAXIMUM RESULTS ALL |
| DRC SELECT CHECK drcRecommended |
| DRC CHECK MAP drcRecommended |
| // ASCII "$cy_calbr_rundir/drcRecommended.db" |
| ASCII "drcRecommended.db" |
| MAXIMUM RESULTS 20000 |
