| torture_test_s8 1000 |
| s_68_metblk.6 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| metblk.6: prBoundary.boundary not allowed in layout |
| s_69_metblk.7 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| metblk.7: poly.boundary not allowed in layout |
| s_70_metblk.7 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| metblk.7: diff.boundary not allowed in layout |
| s_71_metblk.7 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| metblk.7: tap.boundary not allowed in layout |
| s_0_X.18 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| single mcon_NOTAreaidStdCellCore that can be doubled |
| s_1_X.18 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| single via_NOTAreaidStdCellCore that can be doubled |
| s_2_X.18 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| single via2_NOTAreaidStdCellCore that can be doubled |
| s_3_X.18 |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| single via3_NOTAreaidStdCellCore that can be doubled |
| s_5_X.23f |
| 0 0 2 Nov 17 08:09:13 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.23f: ptap must not straddle localSub |
| s_4_X.18 |
| 26 26 2 Nov 17 08:09:14 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| single via4_NOTAreaidStdCellCore that can be doubled |
| p 1 4 |
| CN torture_test_s8 c 1 0 0 1 0 0 0 |
| 3099700 459850 |
| 3100500 459850 |
| 3100500 460650 |
| 3099700 460650 |
| p 2 4 |
| 3099700 468850 |
| 3100500 468850 |
| 3100500 469650 |
| 3099700 469650 |
| p 3 4 |
| 3102700 388350 |
| 3103500 388350 |
| 3103500 389150 |
| 3102700 389150 |
| p 4 4 |
| 3102700 395350 |
| 3103500 395350 |
| 3103500 396150 |
| 3102700 396150 |
| p 5 4 |
| 3103700 351600 |
| 3104500 351600 |
| 3104500 352400 |
| 3103700 352400 |
| p 6 4 |
| 3103700 356100 |
| 3104500 356100 |
| 3104500 356900 |
| 3103700 356900 |
| p 7 4 |
| 3112590 459850 |
| 3113390 459850 |
| 3113390 460650 |
| 3112590 460650 |
| p 8 4 |
| 3112590 464350 |
| 3113390 464350 |
| 3113390 465150 |
| 3112590 465150 |
| p 9 4 |
| 3112590 468850 |
| 3113390 468850 |
| 3113390 469650 |
| 3112590 469650 |
| p 10 4 |
| 3118590 388350 |
| 3119390 388350 |
| 3119390 389150 |
| 3118590 389150 |
| p 11 4 |
| 3118590 395350 |
| 3119390 395350 |
| 3119390 396150 |
| 3118590 396150 |
| p 12 4 |
| 3120590 351600 |
| 3121390 351600 |
| 3121390 352400 |
| 3120590 352400 |
| p 13 4 |
| 3120590 356100 |
| 3121390 356100 |
| 3121390 356900 |
| 3120590 356900 |
| p 14 4 |
| 3134480 388350 |
| 3135280 388350 |
| 3135280 389150 |
| 3134480 389150 |
| p 15 4 |
| 3134480 395350 |
| 3135280 395350 |
| 3135280 396150 |
| 3134480 396150 |
| p 16 4 |
| 3150370 388350 |
| 3151170 388350 |
| 3151170 389150 |
| 3150370 389150 |
| p 17 4 |
| 3150370 395350 |
| 3151170 395350 |
| 3151170 396150 |
| 3150370 396150 |
| p 18 4 |
| 3189700 456375 |
| 3190500 456375 |
| 3190500 457175 |
| 3189700 457175 |
| p 19 4 |
| 3202590 456375 |
| 3203390 456375 |
| 3203390 457175 |
| 3202590 457175 |
| p 20 4 |
| 3215480 456375 |
| 3216280 456375 |
| 3216280 457175 |
| 3215480 457175 |
| p 21 4 |
| 3458700 489110 |
| 3459500 489110 |
| 3459500 489910 |
| 3458700 489910 |
| p 22 4 |
| 3458700 502610 |
| 3459500 502610 |
| 3459500 503410 |
| 3458700 503410 |
| p 23 4 |
| 3470590 489110 |
| 3471390 489110 |
| 3471390 489910 |
| 3470590 489910 |
| p 24 4 |
| 3470590 493610 |
| 3471390 493610 |
| 3471390 494410 |
| 3470590 494410 |
| p 25 4 |
| 3470590 498110 |
| 3471390 498110 |
| 3471390 498910 |
| 3470590 498910 |
| p 26 4 |
| 3470590 502610 |
| 3471390 502610 |
| 3471390 503410 |
| 3470590 503410 |
| s_8_m2.3c |
| 0 0 2 Nov 17 08:09:14 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m2.3c: Crater: spacing matches between met2 areas with via2-to-SurfaceArea ratio >=0.05 and =< 0.032 |
| s_6_X.27 |
| 0 0 2 Nov 17 08:09:14 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.27: partnum or partnum exclusion 'partnum_not_necessary' not present on chip |
| s_7_X.27 |
| 0 0 2 Nov 17 08:09:14 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.27: partnum*block pcell should be used instead of partnum* pcells |
| s_44_m1.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m1.x.1: <70% metal density when 700x700 window 100% covered by mm1.waffledrop |
| s_45_m1.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m1.x.1: <65% metal density when 700x700 window 80-100% covered by mm1.waffledrop |
| s_46_m1.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m1.x.1: <60% metal density when 700x700 window 60-80% covered by mm1.waffledrop |
| s_47_m1.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m1.x.1: <50% metal density when 700x700 window 50-60% covered by mm1.waffledrop |
| s_48_m1.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m1.x.1: <40% metal density when 700x700 window 40-50% covered by mm1.waffledrop |
| s_49_m1.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m1.x.1: <30% metal density when 700x700 window 30-40% covered by mm1.waffledrop |
| s_50_m2.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m2.x.1: <70% metal density when 700x700 window 100% covered by mm2.waffledrop |
| s_51_m2.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m2.x.1: <65% metal density when 700x700 window 80-100% covered by mm2.waffledrop |
| s_52_m2.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m2.x.1: <60% metal density when 700x700 window 60-80% covered by mm2.waffledrop |
| s_53_m2.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m2.x.1: <50% metal density when 700x700 window 50-60% covered by mm2.waffledrop |
| s_54_m2.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m2.x.1: <40% metal density when 700x700 window 40-50% covered by mm2.waffledrop |
| s_55_m2.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m2.x.1: <30% metal density when 700x700 window 30-40% covered by mm2.waffledrop |
| s_56_m3.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m3.x.1: <70% metal density when 700x700 window 100% covered by mm3.waffledrop |
| s_57_m3.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m3.x.1: <65% metal density when 700x700 window 80-100% covered by mm3.waffledrop |
| s_58_m3.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m3.x.1: <60% metal density when 700x700 window 60-80% covered by mm3.waffledrop |
| s_59_m3.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m3.x.1: <50% metal density when 700x700 window 50-60% covered by mm3.waffledrop |
| s_60_m3.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m3.x.1: <40% metal density when 700x700 window 40-50% covered by mm3.waffledrop |
| s_61_m3.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m3.x.1: <30% metal density when 700x700 window 30-40% covered by mm3.waffledrop |
| s_62_m4.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m4.x.1: <70% metal density when 700x700 window 100% covered by mm4.waffledrop |
| s_63_m4.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m4.x.1: <65% metal density when 700x700 window 80-100% covered by mm4.waffledrop |
| s_64_m4.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m4.x.1: <60% metal density when 700x700 window 60-80% covered by mm4.waffledrop |
| s_65_m4.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m4.x.1: <50% metal density when 700x700 window 50-60% covered by mm4.waffledrop |
| s_66_m4.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m4.x.1: <40% metal density when 700x700 window 40-50% covered by mm4.waffledrop |
| s_67_m4.x.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| m4.x.1: <30% metal density when 700x700 window 30-40% covered by mm4.waffledrop |
| s_9_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating poly_float or poly_tie text not over poly |
| s_10_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: poly marked with poly_float not floating |
| s_11_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Nets on poly is floating |
| s_12_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating poly marked with poly_tie at chiplevel without connecting |
| s_13_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Metal on poly is texted as both tied and floating (Chip level) |
| s_14_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating li1_float or li1_tie text not over li1 |
| s_15_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: li1 marked with li1_float not floating |
| s_18_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Metal on li1 is texted as both tied and floating (Chip level) |
| s_16_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Nets on li1 is floating |
| s_17_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating li1 marked with li1_tie at chiplevel without connecting |
| s_19_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating m1_float or m1_tie text not over met1 |
| s_20_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: met1 marked with m1_float not floating |
| s_21_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Nets on met1 is floating |
| s_22_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating met1 marked with m1_tie at chiplevel without connecting |
| s_23_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Metal on met1 is texted as both tied and floating (Chip level) |
| s_24_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating m2_float or m2_tie text not over met2 |
| s_25_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: met2 marked with m2_float not floating |
| s_26_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Nets on met2 is floating |
| s_27_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating met2 marked with m2_tie at chiplevel without connecting |
| s_28_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Metal on met2 is texted as both tied and floating (Chip level) |
| s_29_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating m3_float or m3_tie text not over met3 |
| s_30_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: met3 marked with m3_float not floating |
| s_31_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Nets on met3 is floating |
| s_32_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating met3 marked with m3_tie at chiplevel without connecting |
| s_33_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Metal on met3 is texted as both tied and floating (Chip level) |
| s_34_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating m4_float or m4_tie text not over met4 |
| s_35_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: met4 marked with m4_float not floating |
| s_36_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Nets on met4 is floating |
| s_37_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating met4 marked with m4_tie at chiplevel without connecting |
| s_38_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Metal on met4 is texted as both tied and floating (Chip level) |
| s_39_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating m5_float or m5_tie text not over met5 |
| s_40_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: met5 marked with m5_float not floating |
| s_41_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Nets on met5 is floating |
| s_42_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Floating met5 marked with m5_tie at chiplevel without connecting |
| s_43_X.22 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| X.22: Metal on met5 is texted as both tied and floating (Chip level) |
| s_72_chipint.1 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| chipint.1: areaid.ld not allowed within 50.0 um of ESDID |
| s_73_chipint.2 |
| 0 0 2 Nov 17 08:09:17 2019 |
| Rule File Pathname: /cadfiles/EfabLess/DRC/calibre_rundir/drc/_s8_drcRules_ |
| chipint.2: areaid.ij not allowed within 150.0 um of ESDID |
