| v {xschem version=2.9.8 file_version=1.2 |
| |
| * Copyright 2021 Stefan Frederik Schippers |
| * |
| * Licensed under the Apache License, Version 2.0 (the "License"); |
| * you may not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * https://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, |
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| |
| } |
| G {type=stdcell |
| vhdl_stop=true |
| verilog_stop=true |
| format="@name @pinlist @VCCPIN @VSSPIN @VCCBPIN @VSSBPIN @symname" |
| template="name=x1 VCCPIN=VCC VSSPIN=VSS VCCBPIN=VCC VSSBPIN=VSS" |
| generic_type="VCCPIN=string VSSPIN=string VCCBPIN=string VSSBPIN=string" |
| extra="VCCPIN VSSPIN VCCBPIN VSSBPIN"} |
| V {} |
| S {} |
| E {} |
| L 4 -30 -30 -15 -30 {} |
| L 4 -30 30 -15 30 {} |
| L 4 -60 -30 -30 -30 {} |
| L 4 -60 30 -30 30 {} |
| L 4 -60 10 -22.2265625 10 {} |
| L 4 -60 -10 -22.2265625 -10 {} |
| L 4 35 0 60 0 {} |
| B 5 57.5 -2.5 62.5 2.5 {name=Y dir=out verilog_type=wire} |
| B 5 -62.5 -32.5 -57.5 -27.5 {name=A dir=in} |
| B 5 -62.5 -12.5 -57.5 -7.5 {name=B dir=in} |
| B 5 -62.5 7.5 -57.5 12.5 {name=C dir=in} |
| B 5 -62.5 27.5 -57.5 32.5 {name=D dir=in} |
| A 4 -77.5 0 56.18051263561058 327.7243556854224 64.55128862915524 {} |
| A 4 -21.07142857142857 36.78571428571428 67.06112046149408 33.26691584358777 51.53865524867743 {} |
| A 4 -21.07142857142857 -36.78571428571428 67.06112046149408 275.1944289077348 51.53865524867743 {} |
| T {@name} -16.25 -5 0 0 0.2 0.2 {} |
| T {@symname} -25 -45 0 0 0.2 0.2 {} |
