| v {xschem version=2.9.8 file_version=1.2 |
| |
| * Copyright 2021 Stefan Frederik Schippers |
| * |
| * Licensed under the Apache License, Version 2.0 (the "License"); |
| * you may not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * https://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, |
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| |
| } |
| G {type=stdcell |
| vhdl_stop=true |
| verilog_stop=true |
| format="@name @pinlist @VCCPIN @VSSPIN @VCCBPIN @VSSBPIN @symname" |
| template="name=x1 VCCPIN=VCC VSSPIN=VSS VCCBPIN=VCC VSSBPIN=VSS" |
| generic_type="VCCPIN=string VSSPIN=string VCCBPIN=string VSSBPIN=string" |
| extra="VCCPIN VSSPIN VCCBPIN VSSBPIN"} |
| V {} |
| S {} |
| E {} |
| L 4 -60 -20 -40 -20 {} |
| L 4 0 50 0 60 {} |
| L 4 40 -20 60 -20 {} |
| L 4 -60 20 -50 20 {} |
| L 4 40 20 60 20 {} |
| B 5 57.5 -22.5 62.5 -17.5 {name=Q dir=out verilog_type=wire} |
| B 5 57.5 17.5 62.5 22.5 {name=QB dir=out verilog_type=wire} |
| B 5 -62.5 -22.5 -57.5 -17.5 {name=D dir=in verilog_type=wire} |
| B 5 -62.5 17.5 -57.5 22.5 {name=E dir=in verilog_type=wire} |
| B 5 -2.5 57.5 2.5 62.5 {name=R dir=in verilog_type=wire} |
| A 4 0 45 5 0 360 {} |
| A 4 -45 20 5 0 360 {} |
| P 4 5 -40 40 40 40 40 -40 -40 -40 -40 40 {} |
| T {Q} 35 -25 0 1 0.2 0.2 {} |
| T {D} -35 -25 0 0 0.2 0.2 {} |
| T {R} -5 25 0 0 0.2 0.2 {} |
| T {@name} -21.25 -5 0 0 0.2 0.2 {} |
| T {@symname} 8.75 -55 0 0 0.2 0.2 {} |
| T {QB} 35 15 0 1 0.2 0.2 {} |
| T {E} -35 15 0 0 0.2 0.2 {} |
