verilog/sky130_osu_sc_and2xl.v

// type: AND2 
`timescale 1ns/10ps
`celldefine
module sky130_osu_sc_AND2XL (Y, A, B);
	output Y;
	input A, B;

	// Function
	and (Y, A, B);

	// Timing
	specify
		(A => Y) = 0;
		(B => Y) = 0;
	endspecify
endmodule
`endcelldefine