"18 track" digital standard cells for SKY130 created by Oklahoma State University.

Clone this repo:

Branches

  1. aa2b509 NEW CELL ADDITIONS: Negative D-Latch, Positive Clock Gate, Negative Clock Gate by HunterLusk · 5 months ago main
  2. 14b5f03 Fix verilog files by Teodor-Dumitru Ene · 7 months ago
  3. 83f5245 Add latch cells to library by Teo Ene · 11 months ago
  4. 7ce4bd4 Updated files from spring 2021 by Hunter Lusk · 1 year, 1 month ago
  5. c27ce50 Update to MMMC timing files by Teo Ene · 1 year, 7 months ago

OSU_130_PDK

System on Chip Design Flow including standard cells for SkyWater 130nm process

VLSI Computer Architecture Research Group

  • James E. Stine, Jr.
  • Teo Ene
  • Landon Burleson
  • Ryan Swann
  • Ryan Ridley
  • Brett Mathis
  • Alex Underwood
  • S. Ross Thompson
  • Peter Tikalsky
  • Brandon Ong
  • Hunter Lusk

Thanks to the following for help, guidance and support!

License

This repository is released under the Apache 2.0 license. The full license text can be found in the LICENSE file.

Copyright 2020  Board of Regents for the Oklahoma Agricultural and Mechanical Colleges

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License