1. aa2b509 NEW CELL ADDITIONS: Negative D-Latch, Positive Clock Gate, Negative Clock Gate by HunterLusk · 1 year, 10 months ago main
  2. 14b5f03 Fix verilog files by Teodor-Dumitru Ene · 2 years ago
  3. 83f5245 Add latch cells to library by Teo Ene · 2 years, 4 months ago
  4. 7ce4bd4 Updated files from spring 2021 by Hunter Lusk · 2 years, 7 months ago
  5. c27ce50 Update to MMMC timing files by Teo Ene · 3 years ago
  6. 6c20402 MMMC timing files by Teo Ene · 3 years, 3 months ago
  7. 0f4cda8 Fixed rail via bug by Teo Ene · 3 years, 3 months ago
  8. 913eab1 Adding ANT cells to the lib; doing the 18T_hs in a rush now. by Teo Ene · 3 years, 3 months ago
  9. 2ea8779 Added .tlef file by Teo Ene · 3 years, 4 months ago
  10. 8a22e85 TT 1P8 25C characterization results by Teo Ene · 3 years, 4 months ago
  11. 900ad34 Revised files; characterization pending due to license starvation by Teo Ene · 3 years, 4 months ago
  12. 58dcb3f Initial Commit by Teo Ene · 3 years, 5 months ago