tree: e0167aa9a5c33af4f9c3e4a0ad4d2a64f13fff52 [path history] [tgz]
  1. README.md
  2. cla64.do
  3. cla64.v
  4. tb.sv
flow/CLA64/README.md

This one of my first tests written in Verilog of a highly combinational traditional 64-bit Weinberger-Smith Carry-Lookahead Adeer that can add or subtract based on op.

Again, this is a purely combinational device and could be modified to have a sequential inputs/outputs.