| commit | fd4c4436958103d29fe1d12a5001a2cebfbbc582 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 1868e77958d50c4e298ba9c9be5bc8dc11b84d77 | |
| parent | fe214d2aa221ec93ca3edefec68464cb51c406c6 [diff] | |
| parent | 8530db93614fd4feda9e46aef13d5427b9e56a4d [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>