verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
tree: 1868e77958d50c4e298ba9c9be5bc8dc11b84d77
  1. .gitignore
  2. LICENSE
  3. README.rst
  4. cells/
  5. models/
  6. tech/
  7. timing/