tree 1868e77958d50c4e298ba9c9be5bc8dc11b84d77
parent fe214d2aa221ec93ca3edefec68464cb51c406c6
parent 8530db93614fd4feda9e46aef13d5427b9e56a4d
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>