{ | |
"area": 55.944, | |
"cell_footprint": "sky130_fd_sc_ls__sedfxtp", | |
"cell_leakage_power": 513.0838, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 372.0672055, | |
"when": "!D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 360.7538588, | |
"when": "D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 569.3679554, | |
"when": "D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 382.1077144, | |
"when": "D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 405.844105, | |
"when": "D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 637.7381965, | |
"when": "!D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 579.5375841, | |
"when": "!D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 571.2200277, | |
"when": "!D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 742.5638842, | |
"when": "!D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 583.2150123, | |
"when": "!D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 746.4812484, | |
"when": "D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 587.1517601, | |
"when": "D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 345.7568027, | |
"when": "D&!SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 397.0277191, | |
"when": "!D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 351.8458129, | |
"when": "D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 576.6614777, | |
"when": "!D&!SCE&SCD&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.002817, | |
"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002732, | |
"internal_power": { | |
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0.13172, | |
0.19757, | |
0.29634, | |
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0.6667, | |
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1.5 | |
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"values": [ | |
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"rise_power,hidden_pwr_template13": { | |
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"values": [ | |
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0.048929, | |
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"max_transition": 1.5, | |
"min_pulse_width_high": 0.196171, | |
"min_pulse_width_low": 0.164314, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002902 | |
}, | |
"pin,D": { | |
"capacitance": 0.002107, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.002025, | |
"internal_power": { | |
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0.0208824, | |
0.0240407, | |
0.0289146, | |
0.0363629 | |
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"values": [ | |
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0.0163541, | |
0.019552, | |
0.0245114, | |
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"max_transition": 1.5, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002189, | |
"timing": [ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.3987285, | |
0.4491842, | |
0.4959779, | |
0.5378887 | |
] | |
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"related_pin": "CLK", | |
"rise_constraint,vio_10_10_1": { | |
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0.377765 | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.3376934, | |
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[ | |
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0.3193828, | |
0.3466452, | |
0.367804, | |
0.3840801 | |
] | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
{ | |
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0.25, | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.125, | |
0.25, | |
0.5, | |
0.75, | |
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1.5 | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "hold_rising", | |
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