{ | |
"area": 54.3456, | |
"cell_footprint": "sky130_fd_sc_ls__sedfxtp", | |
"cell_leakage_power": 264.337, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 200.7852515, | |
"when": "!D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 192.9685283, | |
"when": "D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 310.6106874, | |
"when": "D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 206.7431666, | |
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}, | |
{ | |
"value": 219.7475482, | |
"when": "D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 318.280712, | |
"when": "!D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 286.7039086, | |
"when": "!D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 281.4446987, | |
"when": "!D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 377.5404878, | |
"when": "!D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 287.6102485, | |
"when": "!D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 379.8729153, | |
"when": "D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 289.9522258, | |
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}, | |
{ | |
"value": 187.993777, | |
"when": "D&!SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 214.7229452, | |
"when": "!D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 189.6759869, | |
"when": "D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 284.7389737, | |
"when": "!D&!SCE&SCD&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
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"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.00259, | |
"internal_power": { | |
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"rise_power,hidden_pwr_template13": { | |
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"min_pulse_width_low": 0.603719, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.00276 | |
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"pin,D": { | |
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"clock": "false", | |
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"internal_power": { | |
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0.011266, | |
0.0113126 | |
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0.0082878, | |
0.0081096, | |
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"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.001927, | |
"timing": [ | |
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1.1063294, | |
1.1958477 | |
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"related_pin": "CLK", | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
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