{ | |
"area": 54.3456, | |
"cell_footprint": "sky130_fd_sc_ls__sedfxtp", | |
"cell_leakage_power": 25.98322, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 20.9409734, | |
"when": "!D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 18.9379126, | |
"when": "D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 29.7712752, | |
"when": "D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 20.1061638, | |
"when": "D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 21.1124007, | |
"when": "D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 31.0879926, | |
"when": "!D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 28.8025408, | |
"when": "!D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 27.9322823, | |
"when": "!D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 36.8740913, | |
"when": "!D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 28.8576434, | |
"when": "!D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 37.2454316, | |
"when": "D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 29.2291524, | |
"when": "D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 18.3668725, | |
"when": "D&!SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 20.0834069, | |
"when": "!D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 17.9165429, | |
"when": "D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 28.4668911, | |
"when": "!D&!SCE&SCD&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.002586, | |
"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002477, | |
"internal_power": { | |
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0.08782, | |
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0.6667, | |
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1.5 | |
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0.0219287, | |
0.0219402, | |
0.0219658 | |
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"rise_power,hidden_pwr_template13": { | |
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0.0181103, | |
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"min_pulse_width_low": 0.63997, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002695 | |
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"pin,D": { | |
"capacitance": 0.001825, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.001745, | |
"internal_power": { | |
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0.0123755, | |
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0.012472, | |
0.01257 | |
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0.0097134, | |
0.0096275, | |
0.0095067 | |
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"max_transition": 1.5, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.001904, | |
"timing": [ | |
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[ | |
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0.9785625, | |
1.0851706, | |
1.1905579, | |
1.2935039 | |
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"related_pin": "CLK", | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
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