{ | |
"area": 51.1488, | |
"cell_footprint": "sky130_fd_sc_ls__sedfxtp", | |
"cell_leakage_power": 0.0009290548, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 0.0005825, | |
"when": "!D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 0.0007959, | |
"when": "D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 0.0011302, | |
"when": "D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 0.0009063, | |
"when": "D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 0.0010128, | |
"when": "D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 0.0009543, | |
"when": "!D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 0.0008427, | |
"when": "!D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 0.0007868, | |
"when": "!D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 0.0010573, | |
"when": "!D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 0.0008326, | |
"when": "!D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 0.0010807, | |
"when": "D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 0.000856, | |
"when": "D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 0.0010124, | |
"when": "D&!SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 0.0010291, | |
"when": "!D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 0.001167, | |
"when": "D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 0.0008183, | |
"when": "!D&!SCE&SCD&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.002316, | |
"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002202, | |
"internal_power": { | |
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}, | |
"max_transition": 5.0, | |
"min_pulse_width_high": 0.788345, | |
"min_pulse_width_low": 1.347541, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002431 | |
}, | |
"pin,D": { | |
"capacitance": 0.001648, | |
"clock": "false", | |
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"fall_capacitance": 0.001555, | |
"internal_power": { | |
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"max_transition": 5.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.001742, | |
"timing": [ | |
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2.3601272, | |
2.8461025, | |
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"related_pin": "CLK", | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
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