{ | |
"area": 51.1488, | |
"cell_footprint": "sky130_fd_sc_ls__sedfxtp", | |
"cell_leakage_power": 27.072, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 21.5013802, | |
"when": "!D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 19.5077536, | |
"when": "D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 30.6761656, | |
"when": "D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 20.6422985, | |
"when": "D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 21.5623075, | |
"when": "D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 32.8393668, | |
"when": "!D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 30.4310639, | |
"when": "!D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 29.473421, | |
"when": "!D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 38.8483272, | |
"when": "!D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 30.4130019, | |
"when": "!D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 39.2339636, | |
"when": "D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 30.7988159, | |
"when": "D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 18.6249096, | |
"when": "D&!SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 20.4124291, | |
"when": "!D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 18.1864142, | |
"when": "D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 30.0003222, | |
"when": "!D&!SCE&SCD&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.002596, | |
"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002508, | |
"internal_power": { | |
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0.13172, | |
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0.0217463, | |
0.0217731, | |
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"rise_power,hidden_pwr_template13": { | |
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"values": [ | |
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0.0178905, | |
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"min_pulse_width_low": 0.631181, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002684 | |
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"pin,D": { | |
"capacitance": 0.001746, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.001666, | |
"internal_power": { | |
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0.0121704, | |
0.0122421, | |
0.012357 | |
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0.0096243, | |
0.0095414, | |
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"max_transition": 1.5, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.001825, | |
"timing": [ | |
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0.857306, | |
0.9639141, | |
1.0705222, | |
1.1759095, | |
1.2776348 | |
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"related_pin": "CLK", | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
{ | |
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[ | |
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