{ | |
"area": 57.5424, | |
"cell_footprint": "sky130_fd_sc_ls__sedfxbp", | |
"cell_leakage_power": 71.31548, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 47.2813788, | |
"when": "!D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 44.0383552, | |
"when": "D&!SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 64.5441744, | |
"when": "D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 46.4893617, | |
"when": "D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 48.9889693, | |
"when": "D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 60.5626269, | |
"when": "!D&SCE&!SCD&CLK" | |
}, | |
{ | |
"value": 56.0395534, | |
"when": "!D&!SCE&SCD&CLK" | |
}, | |
{ | |
"value": 54.4265397, | |
"when": "!D&!SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 70.6539609, | |
"when": "!D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 55.6977504, | |
"when": "!D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 71.3154833, | |
"when": "D&SCE&SCD&CLK" | |
}, | |
{ | |
"value": 56.3601574, | |
"when": "D&SCE&!SCD&!CLK" | |
}, | |
{ | |
"value": 43.4356018, | |
"when": "D&!SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 46.5861127, | |
"when": "!D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 42.3025277, | |
"when": "D&SCE&SCD&!CLK" | |
}, | |
{ | |
"value": 55.3514283, | |
"when": "!D&!SCE&SCD&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.002719, | |
"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002627, | |
"internal_power": { | |
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0.08782, | |
0.13172, | |
0.19757, | |
0.29634, | |
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"values": [ | |
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0.0619714, | |
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"rise_power,hidden_pwr_template13": { | |
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"values": [ | |
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"max_transition": 1.0, | |
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"min_pulse_width_low": 0.16761, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002812 | |
}, | |
"pin,D": { | |
"capacitance": 0.002078, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.001987, | |
"internal_power": { | |
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0.0212488, | |
0.0238949, | |
0.027879, | |
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"values": [ | |
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0.0175663, | |
0.0201264, | |
0.0239827, | |
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"max_transition": 1.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.00217, | |
"timing": [ | |
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[ | |
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[ | |
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[ | |
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0.458543, | |
0.5126608, | |
0.5618959, | |
0.6111309 | |
] | |
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"related_pin": "CLK", | |
"rise_constraint,vio_10_10_1": { | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.3714662, | |
0.3840801 | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
{ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "hold_rising", | |
"violation_delay_degrade_pct": 10 | |
} | |
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