{ | |
"area": 44.7552, | |
"cell_footprint": "sky130_fd_sc_ls__sdfxbp", | |
"cell_leakage_power": 408.5721, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 372.8927709, | |
"when": "D&SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 427.6698462, | |
"when": "!D&SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 405.7276044, | |
"when": "D&SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 450.116687, | |
"when": "D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 382.1603798, | |
"when": "!D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 349.4730834, | |
"when": "!D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 410.0146214, | |
"when": "!D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 354.1989315, | |
"when": "!D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 400.167977, | |
"when": "D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 329.0564905, | |
"when": "D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 402.1690643, | |
"when": "D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 475.6477949, | |
"when": "!D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 450.3705497, | |
"when": "!D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 453.7190534, | |
"when": "D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 456.0643845, | |
"when": "D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 417.7046264, | |
"when": "!D&SCD&!SCE&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.0029, | |
"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002804, | |
"internal_power": { | |
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0.03903, | |
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0.13172, | |
0.19757, | |
0.29634, | |
0.44449, | |
0.6667, | |
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1.5 | |
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"values": [ | |
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0.0530217, | |
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"rise_power,hidden_pwr_template13": { | |
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"values": [ | |
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"max_transition": 1.5, | |
"min_pulse_width_high": 0.09401, | |
"min_pulse_width_low": 0.163216, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002995 | |
}, | |
"pin,D": { | |
"capacitance": 0.001983, | |
"clock": "false", | |
"direction": "input", | |
"fall_capacitance": 0.001919, | |
"internal_power": { | |
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0.0112091, | |
0.0122621, | |
0.0144588, | |
0.0178729, | |
0.023113, | |
0.0310932 | |
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0.13172, | |
0.19757, | |
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0.6667, | |
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"values": [ | |
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0.0013881, | |
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0.0029567, | |
0.0051643, | |
0.0085945, | |
0.0138588, | |
0.0218752 | |
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"max_transition": 1.5, | |
"nextstate_type": "data", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002047, | |
"timing": [ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.3193828, | |
0.3735007, | |
0.4239564, | |
0.4731914 | |
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"related_pin": "CLK", | |
"rise_constraint,vio_10_10_1": { | |
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0.25, | |
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1.5 | |
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[ | |
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[ | |
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0.1761536 | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.1960918, | |
0.2013815, | |
0.2030091, | |
0.2021953 | |
] | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
{ | |
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0.125, | |
0.25, | |
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0.75, | |
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[ | |
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[ | |
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[ | |
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[ | |
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0.5, | |
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1.5 | |
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[ | |
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[ | |
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[ | |
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[ | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "hold_rising", | |
"violation_delay_degrade_pct": 10 | |
} | |
] | |
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