|  | { | 
|  | "description": "4-input AND, first two inputs inverted.", | 
|  | "file_prefix": "sky130_fd_sc_ls__and4bb", | 
|  | "library": "sky130_fd_sc_ls", | 
|  | "name": "and4bb", | 
|  | "parameters": [], | 
|  | "ports": [ | 
|  | [ | 
|  | "signal", | 
|  | "X", | 
|  | "output", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "A_N", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "B_N", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "C", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "signal", | 
|  | "D", | 
|  | "input", | 
|  | "" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VPWR", | 
|  | "input", | 
|  | "supply1" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VGND", | 
|  | "input", | 
|  | "supply0" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VPB", | 
|  | "input", | 
|  | "supply1" | 
|  | ], | 
|  | [ | 
|  | "power", | 
|  | "VNB", | 
|  | "input", | 
|  | "supply0" | 
|  | ] | 
|  | ], | 
|  | "type": "cell", | 
|  | "verilog_name": "sky130_fd_sc_ls__and4bb" | 
|  | } |