verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>

models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.blackbox.v

diff --git a/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.blackbox.v b/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.blackbox.v
index 2ca2a0e..64f3c22 100644
--- a/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.blackbox.v
+++ b/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.blackbox.v
@@ -32,16 +32,16 @@
 
 (* blackbox *)
 module sky130_fd_sc_ls__udp_mux_2to1_N (
+    Y ,
     A0,
     A1,
-    S ,
-    Y
+    S
 );
 
+    output Y ;
     input  A0;
     input  A1;
     input  S ;
-    output Y ;
 endmodule
 
 `default_nettype wire

models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v

diff --git a/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v b/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v
index f1ea2cd..4061389 100644
--- a/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v
+++ b/models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v
@@ -34,16 +34,16 @@
 `include "./sky130_fd_sc_ls__udp_mux_2to1_n.blackbox.v"
 `else
 primitive sky130_fd_sc_ls__udp_mux_2to1_N (
+    Y ,
     A0,
     A1,
-    S ,
-    Y
+    S
 );
 
+    output Y ;
     input  A0;
     input  A1;
     input  S ;
-    output Y ;
 
     table
      //  A0  A1  S  :  Y

models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.blackbox.v

diff --git a/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.blackbox.v b/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.blackbox.v
index 9d08497..c84bf10 100644
--- a/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.blackbox.v
+++ b/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.blackbox.v
@@ -32,22 +32,22 @@
 
 (* blackbox *)
 module sky130_fd_sc_ls__udp_mux_4to2 (
+    X ,
     A0,
     A1,
     A2,
     A3,
     S0,
-    S1,
-    X
+    S1
 );
 
+    output X ;
     input  A0;
     input  A1;
     input  A2;
     input  A3;
     input  S0;
     input  S1;
-    output X ;
 endmodule
 
 `default_nettype wire

models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v

diff --git a/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v b/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v
index 83a3db0..eb5a4f0 100644
--- a/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v
+++ b/models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v
@@ -34,22 +34,22 @@
 `include "./sky130_fd_sc_ls__udp_mux_4to2.blackbox.v"
 `else
 primitive sky130_fd_sc_ls__udp_mux_4to2 (
+    X ,
     A0,
     A1,
     A2,
     A3,
     S0,
-    S1,
-    X
+    S1
 );
 
+    output X ;
     input  A0;
     input  A1;
     input  A2;
     input  A3;
     input  S0;
     input  S1;
-    output X ;
 
     table
      //  A0  A1  A2  A3  S0  S1 :  X