| { | |
| "area": 49.5504, | |
| "cell_footprint": "sky130_fd_sc_ls__sdfrbp", | |
| "cell_leakage_power": 21.56171, | |
| "driver_waveform_fall": "ramp", | |
| "driver_waveform_rise": "ramp", | |
| "ff,IQ,IQ_N": { | |
| "clear": "!RESET_B", | |
| "clocked_on": "CLK", | |
| "next_state": "(D&!SCE) | (SCD&SCE)" | |
| }, | |
| "leakage_power": [ | |
| { | |
| "value": 26.967971, | |
| "when": "D&!SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 21.2682316, | |
| "when": "!D&!SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 20.150086, | |
| "when": "!D&SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 19.7593746, | |
| "when": "!D&!SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 17.4324253, | |
| "when": "!D&!SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 24.6704506, | |
| "when": "!D&!SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 26.9911933, | |
| "when": "D&!SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 23.9207658, | |
| "when": "D&SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 24.6429455, | |
| "when": "D&!SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 17.8559176, | |
| "when": "D&!SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 28.3656298, | |
| "when": "!D&SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 21.6456773, | |
| "when": "!D&!SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 19.4969001, | |
| "when": "!D&!SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 27.6665943, | |
| "when": "D&SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 22.0805116, | |
| "when": "D&!SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 19.5051104, | |
| "when": "D&!SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 20.5278816, | |
| "when": "!D&SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 17.4373991, | |
| "when": "!D&SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 23.5575257, | |
| "when": "D&SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 17.8590334, | |
| "when": "D&SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 26.0403645, | |
| "when": "!D&SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 19.9217833, | |
| "when": "!D&SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 25.3412278, | |
| "when": "D&SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 19.9257464, | |
| "when": "D&SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 18.3711109, | |
| "when": "!D&!SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 18.3760847, | |
| "when": "!D&SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 20.4355892, | |
| "when": "!D&!SCD&SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 20.8605098, | |
| "when": "!D&SCD&SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 18.7946423, | |
| "when": "D&!SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 18.797758, | |
| "when": "D&SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 20.4438013, | |
| "when": "D&!SCD&SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 20.8644728, | |
| "when": "D&SCD&SCE&!RESET_B&!CLK" | |
| } | |
| ], | |
| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin,CLK": { | |
| "capacitance": 0.002582, | |
| "clock": "true", | |
| "direction": "input", | |
| "fall_capacitance": 0.002462, | |
| "internal_power": { | |
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| 0.01735, | |
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| "rise_power,hidden_pwr_template13": { | |
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| "values": [ | |
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| 0.0168686, | |
| 0.0168213, | |
| 0.0167565 | |
| ] | |
| } | |
| }, | |
| "max_transition": 1.5, | |
| "min_pulse_width_high": 0.4697, | |
| "min_pulse_width_low": 0.612507, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002702 | |
| }, | |
| "pin,D": { | |
| "capacitance": 0.001711, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001638, | |
| "internal_power": { | |
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| "values": [ | |
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| 0.0077966, | |
| 0.0077718, | |
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| 0.0077012 | |
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| }, | |
| "rise_power,hidden_pwr_template13": { | |
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| 0.0031746, | |
| 0.0030596 | |
| ] | |
| } | |
| }, | |
| "max_transition": 1.5, | |
| "nextstate_type": "data", | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.001785, | |
| "timing": [ | |
| { | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| }, | |
| "related_pin": "CLK", | |
| "rise_constraint,vio_10_10_1": { | |
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| "values": [ | |
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| [ | |
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| }, | |
| "sim_opt": "runlvl=5 accurate=1", | |
| "timing_type": "setup_rising", | |
| "violation_delay_degrade_pct": 10 | |
| }, | |
| { | |
| "fall_constraint,vio_10_10_1": { | |
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