| commit | 26dc994264fd69e07b17c7fbd06a6db57c5e6ff2 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | c051f1d9677403c7eabaccddd5d1f4cb22c2c75c | |
| parent | fd4c4436958103d29fe1d12a5001a2cebfbbc582 [diff] | |
| parent | d8c2717829bd09cbf64eec3778dd90fc2a2fafcd [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>