)]}'
{
  "commit": "26dc994264fd69e07b17c7fbd06a6db57c5e6ff2",
  "tree": "c051f1d9677403c7eabaccddd5d1f4cb22c2c75c",
  "parents": [
    "fd4c4436958103d29fe1d12a5001a2cebfbbc582",
    "d8c2717829bd09cbf64eec3778dd90fc2a2fafcd"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}