blob: 7b7c6a458c5c426f372b480fc5cad0197e9892dd [file] [log] [blame]
Kevin Kelleye35e6002020-05-06 11:00:01 +07001{
2 "description": "Clock gate.",
3 "file_prefix": "sky130_fd_sc_lp__dlclkp",
4 "library": "sky130_fd_sc_lp",
5 "name": "dlclkp",
6 "parameters": [],
7 "ports": [
8 [
9 "signal",
10 "GCLK",
11 "output",
12 ""
13 ],
14 [
15 "signal",
16 "GATE",
17 "input",
18 ""
19 ],
20 [
21 "signal",
22 "CLK",
23 "input",
24 ""
25 ],
26 [
27 "power",
28 "VPWR",
29 "input",
30 "supply1"
31 ],
32 [
33 "power",
34 "VGND",
35 "input",
36 "supply0"
37 ],
38 [
39 "power",
40 "VPB",
41 "input",
42 "supply1"
43 ],
44 [
45 "power",
46 "VNB",
47 "input",
48 "supply0"
49 ]
50 ],
51 "type": "cell",
52 "verilog_name": "sky130_fd_sc_lp__dlclkp"
53}