Updates to spice, PEX and PXI files as well as the addition of lvs reports
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.lvs.report new file mode 100644 index 0000000..a230e8c --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_0.sp ('sky130_fd_sc_lp__a2111o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice ('sky130_fd_sc_lp__a2111o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:04 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111o_0 sky130_fd_sc_lp__a2111o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice index 280addd..c467f93 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_0.pex.spice -* Created: Fri Aug 28 09:45:42 2020 +* Created: Wed Sep 2 09:16:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice index f876d2c..1f71730 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_0.pxi.spice -* Created: Fri Aug 28 09:45:42 2020 +* Created: Wed Sep 2 09:16:07 2020 * x_PM_SKY130_FD_SC_LP__A2111O_0%A_80_159# N_A_80_159#_M1001_d N_A_80_159#_M1004_d + N_A_80_159#_M1002_s N_A_80_159#_c_91_n N_A_80_159#_M1005_g N_A_80_159#_M1008_g
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice index 44f5ca5..f263071 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_0.spice -* Created: Fri Aug 28 09:45:42 2020 +* Created: Wed Sep 2 09:16:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.lvs.report new file mode 100644 index 0000000..856024a --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_1.sp ('sky130_fd_sc_lp__a2111o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice ('sky130_fd_sc_lp__a2111o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:10 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111o_1 sky130_fd_sc_lp__a2111o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice index ada3cb7..69438ba 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_1.pex.spice -* Created: Fri Aug 28 09:45:49 2020 +* Created: Wed Sep 2 09:16:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice index 3d67aea..f80dc05 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_1.pxi.spice -* Created: Fri Aug 28 09:45:49 2020 +* Created: Wed Sep 2 09:16:13 2020 * x_PM_SKY130_FD_SC_LP__A2111O_1%A_105_239# N_A_105_239#_M1011_d + N_A_105_239#_M1003_d N_A_105_239#_M1009_s N_A_105_239#_M1008_g
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice index fc9ff88..6b600f4 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_1.spice -* Created: Fri Aug 28 09:45:49 2020 +* Created: Wed Sep 2 09:16:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.lvs.report new file mode 100644 index 0000000..d12ce91 --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_2.sp ('sky130_fd_sc_lp__a2111o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice ('sky130_fd_sc_lp__a2111o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:16 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111o_2 sky130_fd_sc_lp__a2111o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice index abfcee8..f8fa10d 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_2.pex.spice -* Created: Fri Aug 28 09:45:57 2020 +* Created: Wed Sep 2 09:16:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice index 1ca03ae..e36a20b 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_2.pxi.spice -* Created: Fri Aug 28 09:45:57 2020 +* Created: Wed Sep 2 09:16:19 2020 * x_PM_SKY130_FD_SC_LP__A2111O_2%A_86_275# N_A_86_275#_M1004_d N_A_86_275#_M1000_d + N_A_86_275#_M1008_s N_A_86_275#_M1005_g N_A_86_275#_c_75_n N_A_86_275#_M1003_g
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice index 7b9be4e..019a11c 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_2.spice -* Created: Fri Aug 28 09:45:57 2020 +* Created: Wed Sep 2 09:16:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.lvs.report new file mode 100644 index 0000000..e70d48a --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_4.sp ('sky130_fd_sc_lp__a2111o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice ('sky130_fd_sc_lp__a2111o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111o_4 sky130_fd_sc_lp__a2111o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice index 0bb936e..6cd5993 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_4.pex.spice -* Created: Fri Aug 28 09:46:04 2020 +* Created: Wed Sep 2 09:16:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice index 7faa317..f05d32d 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_4.pxi.spice -* Created: Fri Aug 28 09:46:04 2020 +* Created: Wed Sep 2 09:16:25 2020 * x_PM_SKY130_FD_SC_LP__A2111O_4%D1 N_D1_M1006_g N_D1_M1004_g N_D1_c_144_n + N_D1_M1018_g N_D1_M1022_g N_D1_c_147_n N_D1_c_148_n N_D1_c_149_n D1
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice index 5d4e246..55ba8c1 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_4.spice -* Created: Fri Aug 28 09:46:04 2020 +* Created: Wed Sep 2 09:16:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.lvs.report new file mode 100644 index 0000000..391ddeb --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_lp.sp ('sky130_fd_sc_lp__a2111o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice ('sky130_fd_sc_lp__a2111o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111o_lp sky130_fd_sc_lp__a2111o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 10 10 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MP (4 pins) + 5 5 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 5 5 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice index 63d6c14..ec8ed31 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_lp.pex.spice -* Created: Fri Aug 28 09:46:11 2020 +* Created: Wed Sep 2 09:16:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice index 7421f62..b527171 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_lp.pxi.spice -* Created: Fri Aug 28 09:46:11 2020 +* Created: Wed Sep 2 09:16:31 2020 * x_PM_SKY130_FD_SC_LP__A2111O_LP%D1 N_D1_M1001_g N_D1_M1000_g N_D1_c_106_n + N_D1_M1014_g N_D1_c_108_n N_D1_c_109_n D1 D1 N_D1_c_110_n N_D1_c_111_n
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice index b1d3800..b27f0f0 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_lp.spice -* Created: Fri Aug 28 09:46:11 2020 +* Created: Wed Sep 2 09:16:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.lvs.report new file mode 100644 index 0000000..de89644 --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_m.sp ('sky130_fd_sc_lp__a2111o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice ('sky130_fd_sc_lp__a2111o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111o_m sky130_fd_sc_lp__a2111o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice index b254502..ea5746a 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_m.pex.spice -* Created: Fri Aug 28 09:46:18 2020 +* Created: Wed Sep 2 09:16:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice index 5ec81f4..e6aa4c3 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_m.pxi.spice -* Created: Fri Aug 28 09:46:18 2020 +* Created: Wed Sep 2 09:16:37 2020 * x_PM_SKY130_FD_SC_LP__A2111O_M%A_85_21# N_A_85_21#_M1001_d N_A_85_21#_M1009_d + N_A_85_21#_M1011_s N_A_85_21#_M1010_g N_A_85_21#_M1007_g N_A_85_21#_c_85_n
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice index da9ffea..6dd6a14 100644 --- a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice +++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111o_m.spice -* Created: Fri Aug 28 09:46:18 2020 +* Created: Wed Sep 2 09:16:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.lvs.report new file mode 100644 index 0000000..c71c075 --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_0.sp ('sky130_fd_sc_lp__a2111oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice ('sky130_fd_sc_lp__a2111oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111oi_0 sky130_fd_sc_lp__a2111oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice index 51c4daa..7149f12 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_0.pex.spice -* Created: Fri Aug 28 09:46:26 2020 +* Created: Wed Sep 2 09:16:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice index 6dc07f9..8463d07 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_0.pxi.spice -* Created: Fri Aug 28 09:46:26 2020 +* Created: Wed Sep 2 09:16:43 2020 * x_PM_SKY130_FD_SC_LP__A2111OI_0%D1 N_D1_c_79_n N_D1_c_80_n N_D1_c_81_n + N_D1_c_87_n N_D1_c_88_n N_D1_M1002_g N_D1_c_89_n N_D1_M1003_g N_D1_c_83_n D1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice index 9733d69..2b2cedb 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_0.spice -* Created: Fri Aug 28 09:46:26 2020 +* Created: Wed Sep 2 09:16:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.lvs.report new file mode 100644 index 0000000..b4571a7 --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_1.sp ('sky130_fd_sc_lp__a2111oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice ('sky130_fd_sc_lp__a2111oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111oi_1 sky130_fd_sc_lp__a2111oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice index 0d76f95..0caa1d3 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_1.pex.spice -* Created: Fri Aug 28 09:46:33 2020 +* Created: Wed Sep 2 09:16:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice index 1e5209d..2cef549 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_1.pxi.spice -* Created: Fri Aug 28 09:46:33 2020 +* Created: Wed Sep 2 09:16:49 2020 * x_PM_SKY130_FD_SC_LP__A2111OI_1%D1 N_D1_M1002_g N_D1_M1005_g D1 D1 D1 D1 + N_D1_c_50_n N_D1_c_51_n PM_SKY130_FD_SC_LP__A2111OI_1%D1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice index 576c37a..f87553a 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_1.spice -* Created: Fri Aug 28 09:46:33 2020 +* Created: Wed Sep 2 09:16:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.lvs.report new file mode 100644 index 0000000..8017042 --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_2.sp ('sky130_fd_sc_lp__a2111oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice ('sky130_fd_sc_lp__a2111oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111oi_2 sky130_fd_sc_lp__a2111oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 D1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice index 8869209..2428060 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_2.pex.spice -* Created: Fri Aug 28 09:46:49 2020 +* Created: Wed Sep 2 09:16:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice index 68a0244..556e51e 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_2.pxi.spice -* Created: Fri Aug 28 09:46:49 2020 +* Created: Wed Sep 2 09:16:56 2020 * x_PM_SKY130_FD_SC_LP__A2111OI_2%C1 N_C1_M1012_g N_C1_M1005_g N_C1_M1008_g + N_C1_M1017_g N_C1_c_104_n N_C1_c_105_n C1 N_C1_c_106_n N_C1_c_107_n
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice index fb767b5..4896f2c 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_2.spice -* Created: Fri Aug 28 09:46:49 2020 +* Created: Wed Sep 2 09:16:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.lvs.report new file mode 100644 index 0000000..cba9c4a --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_4.sp ('sky130_fd_sc_lp__a2111oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice ('sky130_fd_sc_lp__a2111oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:16:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111oi_4 sky130_fd_sc_lp__a2111oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice index 137420f..ce9671b 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_4.pex.spice -* Created: Fri Aug 28 09:46:57 2020 +* Created: Wed Sep 2 09:17:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice index 0fe93a7..7564827 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_4.pxi.spice -* Created: Fri Aug 28 09:46:57 2020 +* Created: Wed Sep 2 09:17:02 2020 * x_PM_SKY130_FD_SC_LP__A2111OI_4%D1 N_D1_c_153_n N_D1_M1014_g N_D1_M1000_g + N_D1_c_155_n N_D1_M1022_g N_D1_M1016_g N_D1_c_157_n N_D1_M1023_g N_D1_M1027_g
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice index 109385f..683780c 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_4.spice -* Created: Fri Aug 28 09:46:57 2020 +* Created: Wed Sep 2 09:17:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.lvs.report new file mode 100644 index 0000000..cebf00f --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_lp.sp ('sky130_fd_sc_lp__a2111oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice ('sky130_fd_sc_lp__a2111oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111oi_lp sky130_fd_sc_lp__a2111oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 14 13 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 4 4 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 4 4 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 D1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice index ee9e26a..9a9887c 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_lp.pex.spice -* Created: Fri Aug 28 09:47:04 2020 +* Created: Wed Sep 2 09:17:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice index ecb6b28..76033e6 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_lp.pxi.spice -* Created: Fri Aug 28 09:47:04 2020 +* Created: Wed Sep 2 09:17:08 2020 * x_PM_SKY130_FD_SC_LP__A2111OI_LP%A1 N_A1_M1006_g N_A1_M1008_g N_A1_c_89_n + N_A1_c_94_n A1 A1 N_A1_c_91_n PM_SKY130_FD_SC_LP__A2111OI_LP%A1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice index a64cb51..1cc85c0 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_lp.spice -* Created: Fri Aug 28 09:47:04 2020 +* Created: Wed Sep 2 09:17:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.lvs.report new file mode 100644 index 0000000..0c3a473 --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_m.sp ('sky130_fd_sc_lp__a2111oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice ('sky130_fd_sc_lp__a2111oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:11 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2111oi_m sky130_fd_sc_lp__a2111oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice index a1b65c4..6611614 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_m.pex.spice -* Created: Fri Aug 28 09:47:11 2020 +* Created: Wed Sep 2 09:17:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice index 32d8a88..1bdc184 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_m.pxi.spice -* Created: Fri Aug 28 09:47:11 2020 +* Created: Wed Sep 2 09:17:14 2020 * x_PM_SKY130_FD_SC_LP__A2111OI_M%D1 N_D1_M1009_g N_D1_M1000_g N_D1_c_71_n + N_D1_c_76_n D1 D1 D1 D1 D1 N_D1_c_73_n PM_SKY130_FD_SC_LP__A2111OI_M%D1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice index 1d4d597..6245294 100644 --- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice +++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2111oi_m.spice -* Created: Fri Aug 28 09:47:11 2020 +* Created: Wed Sep 2 09:17:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_0.lvs.report new file mode 100644 index 0000000..9aff253 --- /dev/null +++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_0.sp ('sky130_fd_sc_lp__a211o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_0.spice ('sky130_fd_sc_lp__a211o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211o_0 sky130_fd_sc_lp__a211o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a211o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice index f651e13..576c430 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_0.pex.spice -* Created: Fri Aug 28 09:47:18 2020 +* Created: Wed Sep 2 09:17:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice index 0915280..5aafaca 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_0.pxi.spice -* Created: Fri Aug 28 09:47:18 2020 +* Created: Wed Sep 2 09:17:21 2020 * x_PM_SKY130_FD_SC_LP__A211O_0%A_80_172# N_A_80_172#_M1002_d N_A_80_172#_M1000_d + N_A_80_172#_M1005_d N_A_80_172#_c_78_n N_A_80_172#_M1009_g N_A_80_172#_M1007_g
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.spice b/cells/a211o/sky130_fd_sc_lp__a211o_0.spice index db2354f..1480e73 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_0.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_0.spice -* Created: Fri Aug 28 09:47:18 2020 +* Created: Wed Sep 2 09:17:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_1.lvs.report new file mode 100644 index 0000000..40a77a9 --- /dev/null +++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_1.sp ('sky130_fd_sc_lp__a211o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_1.spice ('sky130_fd_sc_lp__a211o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:24 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211o_1 sky130_fd_sc_lp__a211o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a211o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice index fc28250..7a3ca24 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_1.pex.spice -* Created: Fri Aug 28 09:47:25 2020 +* Created: Wed Sep 2 09:17:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice index f8e4b5a..7f5efd6 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_1.pxi.spice -* Created: Fri Aug 28 09:47:25 2020 +* Created: Wed Sep 2 09:17:27 2020 * x_PM_SKY130_FD_SC_LP__A211O_1%A_80_237# N_A_80_237#_M1001_d N_A_80_237#_M1007_d + N_A_80_237#_M1000_d N_A_80_237#_M1008_g N_A_80_237#_c_53_n N_A_80_237#_M1009_g
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.spice b/cells/a211o/sky130_fd_sc_lp__a211o_1.spice index 3e7c9fa..c1b75a9 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_1.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_1.spice -* Created: Fri Aug 28 09:47:25 2020 +* Created: Wed Sep 2 09:17:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_2.lvs.report new file mode 100644 index 0000000..3b043ea --- /dev/null +++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_2.sp ('sky130_fd_sc_lp__a211o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_2.spice ('sky130_fd_sc_lp__a211o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:30 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211o_2 sky130_fd_sc_lp__a211o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a211o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice index 5a398a5..4657dfd 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_2.pex.spice -* Created: Fri Aug 28 09:47:32 2020 +* Created: Wed Sep 2 09:17:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice index 2f3e0ed..7263702 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_2.pxi.spice -* Created: Fri Aug 28 09:47:32 2020 +* Created: Wed Sep 2 09:17:33 2020 * x_PM_SKY130_FD_SC_LP__A211O_2%A_80_21# N_A_80_21#_M1007_d N_A_80_21#_M1001_d + N_A_80_21#_M1006_d N_A_80_21#_M1002_g N_A_80_21#_M1003_g N_A_80_21#_M1004_g
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.spice b/cells/a211o/sky130_fd_sc_lp__a211o_2.spice index dce0f8c..9793815 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_2.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_2.spice -* Created: Fri Aug 28 09:47:32 2020 +* Created: Wed Sep 2 09:17:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_4.lvs.report new file mode 100644 index 0000000..6e7d3f6 --- /dev/null +++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_4.sp ('sky130_fd_sc_lp__a211o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_4.spice ('sky130_fd_sc_lp__a211o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211o_4 sky130_fd_sc_lp__a211o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a211o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 C1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice index 959fa7d..bbbae42 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_4.pex.spice -* Created: Fri Aug 28 09:47:39 2020 +* Created: Wed Sep 2 09:17:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice index c3fd52a..48641b4 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_4.pxi.spice -* Created: Fri Aug 28 09:47:39 2020 +* Created: Wed Sep 2 09:17:39 2020 * x_PM_SKY130_FD_SC_LP__A211O_4%A_103_263# N_A_103_263#_M1002_s + N_A_103_263#_M1019_s N_A_103_263#_M1009_s N_A_103_263#_M1000_s
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.spice b/cells/a211o/sky130_fd_sc_lp__a211o_4.spice index cc601e8..f939240 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_4.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_4.spice -* Created: Fri Aug 28 09:47:39 2020 +* Created: Wed Sep 2 09:17:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_lp.lvs.report new file mode 100644 index 0000000..81e1fcd --- /dev/null +++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_lp.sp ('sky130_fd_sc_lp__a211o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice ('sky130_fd_sc_lp__a211o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:42 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211o_lp sky130_fd_sc_lp__a211o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a211o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 16 16 + + Instances: 8 8 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 14 13 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 4 4 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 4 4 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice index 3103609..6c54253 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_lp.pex.spice -* Created: Fri Aug 28 09:47:55 2020 +* Created: Wed Sep 2 09:17:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice index 2e9257c..7f2760f 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_lp.pxi.spice -* Created: Fri Aug 28 09:47:55 2020 +* Created: Wed Sep 2 09:17:45 2020 * x_PM_SKY130_FD_SC_LP__A211O_LP%A1 N_A1_c_70_n N_A1_M1000_g N_A1_M1001_g A1 A1 + N_A1_c_72_n PM_SKY130_FD_SC_LP__A211O_LP%A1
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice b/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice index ec8a61e..4e9e02a 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_lp.spice -* Created: Fri Aug 28 09:47:55 2020 +* Created: Wed Sep 2 09:17:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_m.lvs.report new file mode 100644 index 0000000..592b5cb --- /dev/null +++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_m.sp ('sky130_fd_sc_lp__a211o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_m.spice ('sky130_fd_sc_lp__a211o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211o_m sky130_fd_sc_lp__a211o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a211o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice index ed94b31..eb4d405 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_m.pex.spice -* Created: Fri Aug 28 09:48:02 2020 +* Created: Wed Sep 2 09:17:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice index fed2e99..598b592 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_m.pxi.spice -* Created: Fri Aug 28 09:48:02 2020 +* Created: Wed Sep 2 09:17:51 2020 * x_PM_SKY130_FD_SC_LP__A211O_M%A2 N_A2_M1002_g N_A2_M1001_g A2 N_A2_c_65_n + N_A2_c_66_n PM_SKY130_FD_SC_LP__A211O_M%A2
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.spice b/cells/a211o/sky130_fd_sc_lp__a211o_m.spice index a158432..040f72b 100644 --- a/cells/a211o/sky130_fd_sc_lp__a211o_m.spice +++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211o_m.spice -* Created: Fri Aug 28 09:48:02 2020 +* Created: Wed Sep 2 09:17:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.lvs.report new file mode 100644 index 0000000..66e8224 --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_0.sp ('sky130_fd_sc_lp__a211oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice ('sky130_fd_sc_lp__a211oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:17:55 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211oi_0 sky130_fd_sc_lp__a211oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice index 7b8568e..462f484 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_0.pex.spice -* Created: Fri Aug 28 09:48:09 2020 +* Created: Wed Sep 2 09:17:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice index d9bca78..8cd69e5 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_0.pxi.spice -* Created: Fri Aug 28 09:48:09 2020 +* Created: Wed Sep 2 09:17:57 2020 * x_PM_SKY130_FD_SC_LP__A211OI_0%A2 N_A2_c_65_n N_A2_c_66_n N_A2_c_67_n + N_A2_M1003_g N_A2_M1000_g N_A2_c_69_n N_A2_c_74_n A2 A2 A2 N_A2_c_71_n
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice index d5d7524..df29f29 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_0.spice -* Created: Fri Aug 28 09:48:09 2020 +* Created: Wed Sep 2 09:17:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.lvs.report new file mode 100644 index 0000000..7da964a --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_1.sp ('sky130_fd_sc_lp__a211oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice ('sky130_fd_sc_lp__a211oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211oi_1 sky130_fd_sc_lp__a211oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice index e474c87..4e39484 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_1.pex.spice -* Created: Fri Aug 28 09:48:16 2020 +* Created: Wed Sep 2 09:18:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice index a756d78..4583949 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_1.pxi.spice -* Created: Fri Aug 28 09:48:16 2020 +* Created: Wed Sep 2 09:18:04 2020 * x_PM_SKY130_FD_SC_LP__A211OI_1%A2 N_A2_c_48_n N_A2_M1002_g N_A2_M1006_g A2 A2 + N_A2_c_51_n PM_SKY130_FD_SC_LP__A211OI_1%A2
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice index 5c2e938..71dec83 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_1.spice -* Created: Fri Aug 28 09:48:16 2020 +* Created: Wed Sep 2 09:18:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.lvs.report new file mode 100644 index 0000000..541549e --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_2.sp ('sky130_fd_sc_lp__a211oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice ('sky130_fd_sc_lp__a211oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211oi_2 sky130_fd_sc_lp__a211oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice index 75fa200..c444351 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_2.pex.spice -* Created: Fri Aug 28 09:48:24 2020 +* Created: Wed Sep 2 09:18:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice index 25bb241..e97fc1f 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_2.pxi.spice -* Created: Fri Aug 28 09:48:24 2020 +* Created: Wed Sep 2 09:18:10 2020 * x_PM_SKY130_FD_SC_LP__A211OI_2%C1 N_C1_c_76_n N_C1_M1012_g N_C1_M1008_g + N_C1_c_78_n N_C1_M1013_g N_C1_M1014_g C1 C1 N_C1_c_81_n
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice index 8016af1..ce6a2de 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_2.spice -* Created: Fri Aug 28 09:48:24 2020 +* Created: Wed Sep 2 09:18:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.lvs.report new file mode 100644 index 0000000..f24248f --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_4.sp ('sky130_fd_sc_lp__a211oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice ('sky130_fd_sc_lp__a211oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211oi_4 sky130_fd_sc_lp__a211oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice index 68730e4..29a83e2 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_4.pex.spice -* Created: Fri Aug 28 09:48:31 2020 +* Created: Wed Sep 2 09:18:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice index 0b94f0d..5d98ac7 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_4.pxi.spice -* Created: Fri Aug 28 09:48:31 2020 +* Created: Wed Sep 2 09:18:16 2020 * x_PM_SKY130_FD_SC_LP__A211OI_4%A2 N_A2_M1006_g N_A2_c_126_n N_A2_M1004_g + N_A2_M1008_g N_A2_c_127_n N_A2_M1009_g N_A2_M1023_g N_A2_c_128_n N_A2_M1012_g
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice index 9b97d01..9e6f2f2 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_4.spice -* Created: Fri Aug 28 09:48:31 2020 +* Created: Wed Sep 2 09:18:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.lvs.report new file mode 100644 index 0000000..1e70444 --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_lp.sp ('sky130_fd_sc_lp__a211oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice ('sky130_fd_sc_lp__a211oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211oi_lp sky130_fd_sc_lp__a211oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 3 3 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice index 3a4bd50..fb0aadc 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_lp.pex.spice -* Created: Fri Aug 28 09:48:38 2020 +* Created: Wed Sep 2 09:18:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice index dd37806..823ebef 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_lp.pxi.spice -* Created: Fri Aug 28 09:48:38 2020 +* Created: Wed Sep 2 09:18:22 2020 * x_PM_SKY130_FD_SC_LP__A211OI_LP%C1 N_C1_c_62_n N_C1_M1008_g N_C1_c_63_n + N_C1_M1004_g N_C1_c_64_n N_C1_c_65_n N_C1_M1005_g N_C1_c_66_n N_C1_c_72_n C1
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice index a76076e..9bca1bb 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_lp.spice -* Created: Fri Aug 28 09:48:38 2020 +* Created: Wed Sep 2 09:18:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.lvs.report new file mode 100644 index 0000000..ada9440 --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a211oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_m.sp ('sky130_fd_sc_lp__a211oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice ('sky130_fd_sc_lp__a211oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a211oi_m sky130_fd_sc_lp__a211oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice index aceb4c4..29c8fcd 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_m.pex.spice -* Created: Fri Aug 28 09:48:45 2020 +* Created: Wed Sep 2 09:18:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice index 69f73c4..8551cfd 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_m.pxi.spice -* Created: Fri Aug 28 09:48:45 2020 +* Created: Wed Sep 2 09:18:28 2020 * x_PM_SKY130_FD_SC_LP__A211OI_M%A2 N_A2_M1005_g N_A2_M1004_g N_A2_c_48_n + N_A2_c_49_n N_A2_c_50_n A2 A2 N_A2_c_51_n PM_SKY130_FD_SC_LP__A211OI_M%A2
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice index 99e3d7b..e32c3ed 100644 --- a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice +++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a211oi_m.spice -* Created: Fri Aug 28 09:48:45 2020 +* Created: Wed Sep 2 09:18:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.lvs.report new file mode 100644 index 0000000..e9693c0 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21bo_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_0.sp ('sky130_fd_sc_lp__a21bo_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice ('sky130_fd_sc_lp__a21bo_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:32 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21bo_0 sky130_fd_sc_lp__a21bo_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 2 2 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice index 784fdca..727ace4 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_0.pex.spice -* Created: Fri Aug 28 09:49:02 2020 +* Created: Wed Sep 2 09:18:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice index 291bc3e..b7faa0c 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_0.pxi.spice -* Created: Fri Aug 28 09:49:02 2020 +* Created: Wed Sep 2 09:18:35 2020 * x_PM_SKY130_FD_SC_LP__A21BO_0%A_72_212# N_A_72_212#_M1004_d N_A_72_212#_M1001_s + N_A_72_212#_M1002_g N_A_72_212#_M1007_g N_A_72_212#_c_82_n N_A_72_212#_c_83_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice index 0b8ff52..51042d0 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_0.spice -* Created: Fri Aug 28 09:49:02 2020 +* Created: Wed Sep 2 09:18:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.lvs.report new file mode 100644 index 0000000..ce46e3a --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21bo_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_1.sp ('sky130_fd_sc_lp__a21bo_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice ('sky130_fd_sc_lp__a21bo_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21bo_1 sky130_fd_sc_lp__a21bo_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 2 2 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice index 367af1c..3d12ea9 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_1.pex.spice -* Created: Fri Aug 28 09:49:09 2020 +* Created: Wed Sep 2 09:18:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice index 74b83b5..dd5610d 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_1.pxi.spice -* Created: Fri Aug 28 09:49:09 2020 +* Created: Wed Sep 2 09:18:41 2020 * x_PM_SKY130_FD_SC_LP__A21BO_1%A_80_43# N_A_80_43#_M1007_d N_A_80_43#_M1001_s + N_A_80_43#_M1005_g N_A_80_43#_M1009_g N_A_80_43#_c_76_n N_A_80_43#_c_70_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice index 3ba16e6..2b4b7bc 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_1.spice -* Created: Fri Aug 28 09:49:09 2020 +* Created: Wed Sep 2 09:18:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.lvs.report new file mode 100644 index 0000000..5d29cf5 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21bo_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_2.sp ('sky130_fd_sc_lp__a21bo_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice ('sky130_fd_sc_lp__a21bo_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:44 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21bo_2 sky130_fd_sc_lp__a21bo_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 2 2 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice index 7e37a3d..d8ca4c1 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_2.pex.spice -* Created: Fri Aug 28 09:49:16 2020 +* Created: Wed Sep 2 09:18:47 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice index b6469e1..14a4374 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_2.pxi.spice -* Created: Fri Aug 28 09:49:16 2020 +* Created: Wed Sep 2 09:18:47 2020 * x_PM_SKY130_FD_SC_LP__A21BO_2%A_22_259# N_A_22_259#_M1006_d N_A_22_259#_M1010_s + N_A_22_259#_c_73_n N_A_22_259#_M1000_g N_A_22_259#_M1001_g N_A_22_259#_c_75_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice index e4bdb17..ef123a8 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_2.spice -* Created: Fri Aug 28 09:49:16 2020 +* Created: Wed Sep 2 09:18:47 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.lvs.report new file mode 100644 index 0000000..313d636 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21bo_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_4.sp ('sky130_fd_sc_lp__a21bo_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice ('sky130_fd_sc_lp__a21bo_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:50 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21bo_4 sky130_fd_sc_lp__a21bo_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 2 2 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice index f43e40b..f450101 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_4.pex.spice -* Created: Fri Aug 28 09:49:23 2020 +* Created: Wed Sep 2 09:18:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice index 4ade7ff..09ebbd9 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_4.pxi.spice -* Created: Fri Aug 28 09:49:23 2020 +* Created: Wed Sep 2 09:18:53 2020 * x_PM_SKY130_FD_SC_LP__A21BO_4%B1_N N_B1_N_M1013_g N_B1_N_M1021_g B1_N B1_N + N_B1_N_c_116_n PM_SKY130_FD_SC_LP__A21BO_4%B1_N
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice index 71f8488..f7538bc 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_4.spice -* Created: Fri Aug 28 09:49:23 2020 +* Created: Wed Sep 2 09:18:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.lvs.report new file mode 100644 index 0000000..24d7a08 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21bo_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_lp.sp ('sky130_fd_sc_lp__a21bo_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice ('sky130_fd_sc_lp__a21bo_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:18:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21bo_lp sky130_fd_sc_lp__a21bo_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 8 8 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 14 13 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MP (4 pins) + 4 4 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MP(PHIGHVT) + 4 4 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1_N X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice index cc43515..a3d404b 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_lp.pex.spice -* Created: Fri Aug 28 09:49:30 2020 +* Created: Wed Sep 2 09:18:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice index 22461bc..12f344b 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_lp.pxi.spice -* Created: Fri Aug 28 09:49:30 2020 +* Created: Wed Sep 2 09:18:59 2020 * x_PM_SKY130_FD_SC_LP__A21BO_LP%A_84_29# N_A_84_29#_M1009_d N_A_84_29#_M1006_d + N_A_84_29#_M1007_g N_A_84_29#_c_82_n N_A_84_29#_M1004_g N_A_84_29#_M1001_g
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice index 8348461..44cc91d 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_lp.spice -* Created: Fri Aug 28 09:49:30 2020 +* Created: Wed Sep 2 09:18:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.lvs.report new file mode 100644 index 0000000..26ba299 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21bo_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_m.sp ('sky130_fd_sc_lp__a21bo_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice ('sky130_fd_sc_lp__a21bo_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21bo_m sky130_fd_sc_lp__a21bo_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_m +SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 2 2 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice index 8e1dc6b..c860f10 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_m.pex.spice -* Created: Fri Aug 28 09:49:38 2020 +* Created: Wed Sep 2 09:19:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice index aed3e6c..f6e473c 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_m.pxi.spice -* Created: Fri Aug 28 09:49:38 2020 +* Created: Wed Sep 2 09:19:05 2020 * x_PM_SKY130_FD_SC_LP__A21BO_M%A_80_72# N_A_80_72#_M1000_d N_A_80_72#_M1003_s + N_A_80_72#_M1002_g N_A_80_72#_c_87_n N_A_80_72#_M1008_g N_A_80_72#_c_89_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice index 5ca0bde..9b2f6bb 100644 --- a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice +++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21bo_m.spice -* Created: Fri Aug 28 09:49:38 2020 +* Created: Wed Sep 2 09:19:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.lvs.report new file mode 100644 index 0000000..ae27d32 --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21boi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_0.sp ('sky130_fd_sc_lp__a21boi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice ('sky130_fd_sc_lp__a21boi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:09 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21boi_0 sky130_fd_sc_lp__a21boi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice index ff8cefc..6e41b6d 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_0.pex.spice -* Created: Fri Aug 28 09:49:45 2020 +* Created: Wed Sep 2 09:19:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice index fd67708..b3cd822 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_0.pxi.spice -* Created: Fri Aug 28 09:49:45 2020 +* Created: Wed Sep 2 09:19:12 2020 * x_PM_SKY130_FD_SC_LP__A21BOI_0%B1_N N_B1_N_M1002_g N_B1_N_c_62_n N_B1_N_M1004_g + N_B1_N_c_64_n B1_N B1_N B1_N N_B1_N_c_66_n PM_SKY130_FD_SC_LP__A21BOI_0%B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice index eb001e0..b3c927b 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_0.spice -* Created: Fri Aug 28 09:49:45 2020 +* Created: Wed Sep 2 09:19:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.lvs.report new file mode 100644 index 0000000..a13705a --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21boi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_1.sp ('sky130_fd_sc_lp__a21boi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice ('sky130_fd_sc_lp__a21boi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21boi_1 sky130_fd_sc_lp__a21boi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice index c0aa130..3d0236d 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_1.pex.spice -* Created: Fri Aug 28 09:49:52 2020 +* Created: Wed Sep 2 09:19:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice index 06b098e..8e7bdee 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_1.pxi.spice -* Created: Fri Aug 28 09:49:52 2020 +* Created: Wed Sep 2 09:19:18 2020 * x_PM_SKY130_FD_SC_LP__A21BOI_1%B1_N N_B1_N_c_60_n N_B1_N_M1001_g N_B1_N_c_61_n + N_B1_N_c_62_n N_B1_N_M1002_g N_B1_N_c_64_n N_B1_N_c_69_n B1_N B1_N B1_N B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice index 251ec10..2d21cc0 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_1.spice -* Created: Fri Aug 28 09:49:52 2020 +* Created: Wed Sep 2 09:19:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.lvs.report new file mode 100644 index 0000000..14095c8 --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21boi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_2.sp ('sky130_fd_sc_lp__a21boi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice ('sky130_fd_sc_lp__a21boi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21boi_2 sky130_fd_sc_lp__a21boi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice index 3732d5d..2f87c3c 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_2.pex.spice -* Created: Fri Aug 28 09:50:08 2020 +* Created: Wed Sep 2 09:19:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice index afc995c..e981e7b 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_2.pxi.spice -* Created: Fri Aug 28 09:50:08 2020 +* Created: Wed Sep 2 09:19:24 2020 * x_PM_SKY130_FD_SC_LP__A21BOI_2%B1_N N_B1_N_M1011_g N_B1_N_c_83_n N_B1_N_c_84_n + N_B1_N_c_85_n N_B1_N_M1012_g N_B1_N_c_86_n B1_N B1_N B1_N B1_N B1_N B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice index 4f5452b..5cb305f 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_2.spice -* Created: Fri Aug 28 09:50:08 2020 +* Created: Wed Sep 2 09:19:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.lvs.report new file mode 100644 index 0000000..d489cff --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21boi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_4.sp ('sky130_fd_sc_lp__a21boi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice ('sky130_fd_sc_lp__a21boi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21boi_4 sky130_fd_sc_lp__a21boi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 6. + 18 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 6. + 18 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice index f00c0e7..330331c 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_4.pex.spice -* Created: Fri Aug 28 09:50:15 2020 +* Created: Wed Sep 2 09:19:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice index f5dbe36..0e42916 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_4.pxi.spice -* Created: Fri Aug 28 09:50:15 2020 +* Created: Wed Sep 2 09:19:30 2020 * x_PM_SKY130_FD_SC_LP__A21BOI_4%B1_N N_B1_N_M1007_g N_B1_N_c_103_n N_B1_N_M1014_g + B1_N B1_N N_B1_N_c_105_n PM_SKY130_FD_SC_LP__A21BOI_4%B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice index 984ea13..af017fe 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_4.spice -* Created: Fri Aug 28 09:50:15 2020 +* Created: Wed Sep 2 09:19:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.lvs.report new file mode 100644 index 0000000..4e78f08 --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21boi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_lp.sp ('sky130_fd_sc_lp__a21boi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice ('sky130_fd_sc_lp__a21boi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21boi_lp sky130_fd_sc_lp__a21boi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice index 351337d..6701413 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_lp.pex.spice -* Created: Fri Aug 28 09:50:22 2020 +* Created: Wed Sep 2 09:19:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice index c9c7c49..81f8e1c 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_lp.pxi.spice -* Created: Fri Aug 28 09:50:22 2020 +* Created: Wed Sep 2 09:19:36 2020 * x_PM_SKY130_FD_SC_LP__A21BOI_LP%A2 N_A2_M1002_g N_A2_M1003_g A2 A2 N_A2_c_64_n + PM_SKY130_FD_SC_LP__A21BOI_LP%A2
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice index 01c8f50..30c79bc 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_lp.spice -* Created: Fri Aug 28 09:50:22 2020 +* Created: Wed Sep 2 09:19:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.lvs.report new file mode 100644 index 0000000..5382737 --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21boi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_m.sp ('sky130_fd_sc_lp__a21boi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice ('sky130_fd_sc_lp__a21boi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21boi_m sky130_fd_sc_lp__a21boi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice index 40866b8..e720f1e 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_m.pex.spice -* Created: Fri Aug 28 09:50:29 2020 +* Created: Wed Sep 2 09:19:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice index cc4feab..24aba70 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_m.pxi.spice -* Created: Fri Aug 28 09:50:29 2020 +* Created: Wed Sep 2 09:19:43 2020 * x_PM_SKY130_FD_SC_LP__A21BOI_M%B1_N N_B1_N_M1005_g N_B1_N_M1002_g N_B1_N_c_64_n + N_B1_N_c_65_n B1_N B1_N B1_N B1_N N_B1_N_c_67_n
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice index 78bd9a1..5c607fc 100644 --- a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice +++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21boi_m.spice -* Created: Fri Aug 28 09:50:29 2020 +* Created: Wed Sep 2 09:19:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_0.lvs.report new file mode 100644 index 0000000..1e635d9 --- /dev/null +++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_0.sp ('sky130_fd_sc_lp__a21o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_0.spice ('sky130_fd_sc_lp__a21o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21o_0 sky130_fd_sc_lp__a21o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a21o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice index c1f61e4..02e6140 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_0.pex.spice -* Created: Fri Aug 28 09:50:36 2020 +* Created: Wed Sep 2 09:19:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice index aeb3f7d..0de57cb 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_0.pxi.spice -* Created: Fri Aug 28 09:50:36 2020 +* Created: Wed Sep 2 09:19:49 2020 * x_PM_SKY130_FD_SC_LP__A21O_0%A_80_275# N_A_80_275#_M1002_d N_A_80_275#_M1000_s + N_A_80_275#_M1003_g N_A_80_275#_c_68_n N_A_80_275#_c_69_n N_A_80_275#_M1007_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.spice b/cells/a21o/sky130_fd_sc_lp__a21o_0.spice index c93b8a4..72b8806 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_0.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_0.spice -* Created: Fri Aug 28 09:50:36 2020 +* Created: Wed Sep 2 09:19:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_1.lvs.report new file mode 100644 index 0000000..6a753a0 --- /dev/null +++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_1.sp ('sky130_fd_sc_lp__a21o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_1.spice ('sky130_fd_sc_lp__a21o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21o_1 sky130_fd_sc_lp__a21o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a21o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice index fd7a15c..787f6a5 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_1.pex.spice -* Created: Fri Aug 28 09:50:43 2020 +* Created: Wed Sep 2 09:19:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice index b6833d1..ee48e83 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_1.pxi.spice -* Created: Fri Aug 28 09:50:43 2020 +* Created: Wed Sep 2 09:19:55 2020 * x_PM_SKY130_FD_SC_LP__A21O_1%A_80_237# N_A_80_237#_M1003_d N_A_80_237#_M1001_s + N_A_80_237#_M1007_g N_A_80_237#_c_50_n N_A_80_237#_M1000_g N_A_80_237#_c_51_n
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.spice b/cells/a21o/sky130_fd_sc_lp__a21o_1.spice index 39173a3..b8a0294 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_1.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_1.spice -* Created: Fri Aug 28 09:50:43 2020 +* Created: Wed Sep 2 09:19:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_2.lvs.report new file mode 100644 index 0000000..2843f4e --- /dev/null +++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_2.sp ('sky130_fd_sc_lp__a21o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_2.spice ('sky130_fd_sc_lp__a21o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:19:58 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21o_2 sky130_fd_sc_lp__a21o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a21o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice index 2f3a588..0c61b66 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_2.pex.spice -* Created: Fri Aug 28 09:50:54 2020 +* Created: Wed Sep 2 09:20:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice index 32de5a9..1389152 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_2.pxi.spice -* Created: Fri Aug 28 09:50:54 2020 +* Created: Wed Sep 2 09:20:01 2020 * x_PM_SKY130_FD_SC_LP__A21O_2%A_86_269# N_A_86_269#_M1003_d N_A_86_269#_M1000_s + N_A_86_269#_M1002_g N_A_86_269#_M1001_g N_A_86_269#_M1006_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.spice b/cells/a21o/sky130_fd_sc_lp__a21o_2.spice index 20b31ce..a795a22 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_2.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_2.spice -* Created: Fri Aug 28 09:50:54 2020 +* Created: Wed Sep 2 09:20:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_4.lvs.report new file mode 100644 index 0000000..22a2490 --- /dev/null +++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_4.sp ('sky130_fd_sc_lp__a21o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_4.spice ('sky130_fd_sc_lp__a21o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21o_4 sky130_fd_sc_lp__a21o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a21o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice index f96d6fd..a1a4593 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_4.pex.spice -* Created: Fri Aug 28 09:51:10 2020 +* Created: Wed Sep 2 09:20:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice index 1be4b57..abcfb35 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_4.pxi.spice -* Created: Fri Aug 28 09:51:10 2020 +* Created: Wed Sep 2 09:20:07 2020 * x_PM_SKY130_FD_SC_LP__A21O_4%A_134_269# N_A_134_269#_M1009_s + N_A_134_269#_M1000_s N_A_134_269#_M1005_s N_A_134_269#_M1001_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.spice b/cells/a21o/sky130_fd_sc_lp__a21o_4.spice index 1d9dfe0..e725114 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_4.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_4.spice -* Created: Fri Aug 28 09:51:10 2020 +* Created: Wed Sep 2 09:20:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_lp.lvs.report new file mode 100644 index 0000000..e7aa554 --- /dev/null +++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_lp.sp ('sky130_fd_sc_lp__a21o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice ('sky130_fd_sc_lp__a21o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:11 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21o_lp sky130_fd_sc_lp__a21o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a21o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice index 2449dcb..c34a179 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_lp.pex.spice -* Created: Fri Aug 28 09:51:17 2020 +* Created: Wed Sep 2 09:20:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice index 20e265f..f553c4d 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_lp.pxi.spice -* Created: Fri Aug 28 09:51:17 2020 +* Created: Wed Sep 2 09:20:14 2020 * x_PM_SKY130_FD_SC_LP__A21O_LP%A2 N_A2_M1003_g N_A2_M1006_g A2 A2 N_A2_c_61_n + N_A2_c_62_n PM_SKY130_FD_SC_LP__A21O_LP%A2
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice b/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice index 101a55f..63a7eb2 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_lp.spice -* Created: Fri Aug 28 09:51:17 2020 +* Created: Wed Sep 2 09:20:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_m.lvs.report new file mode 100644 index 0000000..775d5a6 --- /dev/null +++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_m.sp ('sky130_fd_sc_lp__a21o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_m.spice ('sky130_fd_sc_lp__a21o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:17 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21o_m sky130_fd_sc_lp__a21o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a21o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice index 61a3158..e4e27a6 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_m.pex.spice -* Created: Fri Aug 28 09:51:23 2020 +* Created: Wed Sep 2 09:20:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice index 233f6f2..c50f308 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_m.pxi.spice -* Created: Fri Aug 28 09:51:23 2020 +* Created: Wed Sep 2 09:20:20 2020 * x_PM_SKY130_FD_SC_LP__A21O_M%A_80_153# N_A_80_153#_M1001_d N_A_80_153#_M1005_s + N_A_80_153#_c_68_n N_A_80_153#_M1004_g N_A_80_153#_c_62_n N_A_80_153#_M1007_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.spice b/cells/a21o/sky130_fd_sc_lp__a21o_m.spice index d462f1b..5ce3167 100644 --- a/cells/a21o/sky130_fd_sc_lp__a21o_m.spice +++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21o_m.spice -* Created: Fri Aug 28 09:51:23 2020 +* Created: Wed Sep 2 09:20:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.lvs.report new file mode 100644 index 0000000..771730b --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_0.sp ('sky130_fd_sc_lp__a21oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice ('sky130_fd_sc_lp__a21oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:23 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21oi_0 sky130_fd_sc_lp__a21oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice index f2bb457..84c69a9 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_0.pex.spice -* Created: Fri Aug 28 09:51:30 2020 +* Created: Wed Sep 2 09:20:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice index a89ba44..9be8ff8 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_0.pxi.spice -* Created: Fri Aug 28 09:51:30 2020 +* Created: Wed Sep 2 09:20:26 2020 * x_PM_SKY130_FD_SC_LP__A21OI_0%A2 N_A2_c_47_n N_A2_M1005_g N_A2_c_48_n + N_A2_M1000_g N_A2_c_49_n N_A2_c_50_n N_A2_c_55_n A2 A2 A2 N_A2_c_52_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice index 7457415..764732a 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_0.spice -* Created: Fri Aug 28 09:51:30 2020 +* Created: Wed Sep 2 09:20:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.lvs.report new file mode 100644 index 0000000..b50f97e --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_1.sp ('sky130_fd_sc_lp__a21oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice ('sky130_fd_sc_lp__a21oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21oi_1 sky130_fd_sc_lp__a21oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice index a67f9cf..244811b 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_1.pex.spice -* Created: Fri Aug 28 09:51:37 2020 +* Created: Wed Sep 2 09:20:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice index 154c752..c76129e 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_1.pxi.spice -* Created: Fri Aug 28 09:51:37 2020 +* Created: Wed Sep 2 09:20:32 2020 * x_PM_SKY130_FD_SC_LP__A21OI_1%A2 N_A2_M1002_g N_A2_M1005_g A2 A2 N_A2_c_41_n + N_A2_c_42_n PM_SKY130_FD_SC_LP__A21OI_1%A2
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice index f81502a..fad3808 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_1.spice -* Created: Fri Aug 28 09:51:37 2020 +* Created: Wed Sep 2 09:20:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.lvs.report new file mode 100644 index 0000000..f6ae86f --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_2.sp ('sky130_fd_sc_lp__a21oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice ('sky130_fd_sc_lp__a21oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21oi_2 sky130_fd_sc_lp__a21oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice index d180955..6b07479 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_2.pex.spice -* Created: Fri Aug 28 09:51:44 2020 +* Created: Wed Sep 2 09:20:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice index a6e112b..e8bb899 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_2.pxi.spice -* Created: Fri Aug 28 09:51:44 2020 +* Created: Wed Sep 2 09:20:38 2020 * x_PM_SKY130_FD_SC_LP__A21OI_2%A2 N_A2_M1003_g N_A2_M1009_g N_A2_M1006_g + N_A2_M1010_g N_A2_c_62_n N_A2_c_63_n A2 N_A2_c_65_n N_A2_c_66_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice index 694307b..78f2c34 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_2.spice -* Created: Fri Aug 28 09:51:44 2020 +* Created: Wed Sep 2 09:20:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.lvs.report new file mode 100644 index 0000000..a08e47c --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_4.sp ('sky130_fd_sc_lp__a21oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice ('sky130_fd_sc_lp__a21oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:42 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21oi_4 sky130_fd_sc_lp__a21oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 6. + 18 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 6. + 18 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice index 24986d1..abaf82a 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_4.pex.spice -* Created: Fri Aug 28 09:51:51 2020 +* Created: Wed Sep 2 09:20:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice index 97ce357..b564b0f 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_4.pxi.spice -* Created: Fri Aug 28 09:51:51 2020 +* Created: Wed Sep 2 09:20:45 2020 * x_PM_SKY130_FD_SC_LP__A21OI_4%A2 N_A2_M1000_g N_A2_M1008_g N_A2_M1007_g + N_A2_M1018_g N_A2_M1012_g N_A2_M1020_g N_A2_M1016_g N_A2_M1022_g N_A2_c_99_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice index e5929f2..e9035ba 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_4.spice -* Created: Fri Aug 28 09:51:51 2020 +* Created: Wed Sep 2 09:20:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.lvs.report new file mode 100644 index 0000000..dc0962e --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_lp.sp ('sky130_fd_sc_lp__a21oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice ('sky130_fd_sc_lp__a21oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21oi_lp sky130_fd_sc_lp__a21oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 8 7 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice index a506496..0c8355d 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_lp.pex.spice -* Created: Fri Aug 28 09:51:58 2020 +* Created: Wed Sep 2 09:20:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice index 47fc74f..5e4588d 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_lp.pxi.spice -* Created: Fri Aug 28 09:51:58 2020 +* Created: Wed Sep 2 09:20:51 2020 * x_PM_SKY130_FD_SC_LP__A21OI_LP%A2 N_A2_c_48_n N_A2_c_54_n N_A2_M1005_g + N_A2_M1002_g N_A2_c_50_n N_A2_c_51_n A2 N_A2_c_52_n N_A2_c_53_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice index 1bcc208..ff05db3 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_lp.spice -* Created: Fri Aug 28 09:51:58 2020 +* Created: Wed Sep 2 09:20:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.lvs.report new file mode 100644 index 0000000..2c01e13 --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a21oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_m.sp ('sky130_fd_sc_lp__a21oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice ('sky130_fd_sc_lp__a21oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:20:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a21oi_m sky130_fd_sc_lp__a21oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice index 8c40bf3..bd0b27d 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_m.pex.spice -* Created: Fri Aug 28 09:52:14 2020 +* Created: Wed Sep 2 09:20:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice index 622f2fd..e0d5359 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_m.pxi.spice -* Created: Fri Aug 28 09:52:14 2020 +* Created: Wed Sep 2 09:20:57 2020 * x_PM_SKY130_FD_SC_LP__A21OI_M%A2 N_A2_c_49_n N_A2_M1001_g N_A2_M1005_g + N_A2_c_51_n N_A2_c_52_n N_A2_c_57_n A2 A2 A2 A2 N_A2_c_54_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice index c9fd2ad..9e66f34 100644 --- a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice +++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a21oi_m.spice -* Created: Fri Aug 28 09:52:14 2020 +* Created: Wed Sep 2 09:20:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_0.lvs.report new file mode 100644 index 0000000..64f28b5 --- /dev/null +++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_0.sp ('sky130_fd_sc_lp__a221o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_0.spice ('sky130_fd_sc_lp__a221o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221o_0 sky130_fd_sc_lp__a221o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a221o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice index 1343cb9..da61c83 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_0.pex.spice -* Created: Fri Aug 28 09:52:21 2020 +* Created: Wed Sep 2 09:21:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice index 3087407..ade8dea 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_0.pxi.spice -* Created: Fri Aug 28 09:52:21 2020 +* Created: Wed Sep 2 09:21:04 2020 * x_PM_SKY130_FD_SC_LP__A221O_0%A_72_312# N_A_72_312#_M1005_d N_A_72_312#_M1010_d + N_A_72_312#_M1011_d N_A_72_312#_M1000_g N_A_72_312#_M1003_g N_A_72_312#_c_96_n
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.spice b/cells/a221o/sky130_fd_sc_lp__a221o_0.spice index 2417086..ab63f2c 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_0.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_0.spice -* Created: Fri Aug 28 09:52:21 2020 +* Created: Wed Sep 2 09:21:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_1.lvs.report new file mode 100644 index 0000000..f073665 --- /dev/null +++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_1.sp ('sky130_fd_sc_lp__a221o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_1.spice ('sky130_fd_sc_lp__a221o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221o_1 sky130_fd_sc_lp__a221o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a221o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice index 5b0139f..e848235 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_1.pex.spice -* Created: Fri Aug 28 09:52:27 2020 +* Created: Wed Sep 2 09:21:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice index 247810a..3fa30c0 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_1.pxi.spice -* Created: Fri Aug 28 09:52:27 2020 +* Created: Wed Sep 2 09:21:10 2020 * x_PM_SKY130_FD_SC_LP__A221O_1%A_80_21# N_A_80_21#_M1009_d N_A_80_21#_M1003_d + N_A_80_21#_M1000_d N_A_80_21#_M1001_g N_A_80_21#_M1011_g N_A_80_21#_c_67_n
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.spice b/cells/a221o/sky130_fd_sc_lp__a221o_1.spice index ac4c4ae..1c53e54 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_1.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_1.spice -* Created: Fri Aug 28 09:52:27 2020 +* Created: Wed Sep 2 09:21:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_2.lvs.report new file mode 100644 index 0000000..317b104 --- /dev/null +++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_2.sp ('sky130_fd_sc_lp__a221o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_2.spice ('sky130_fd_sc_lp__a221o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221o_2 sky130_fd_sc_lp__a221o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a221o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 C1 B1 B2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice index acd2386..272d9be 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_2.pex.spice -* Created: Fri Aug 28 09:52:34 2020 +* Created: Wed Sep 2 09:21:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice index b93b962..4b72201 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_2.pxi.spice -* Created: Fri Aug 28 09:52:34 2020 +* Created: Wed Sep 2 09:21:16 2020 * x_PM_SKY130_FD_SC_LP__A221O_2%A_86_27# N_A_86_27#_M1003_d N_A_86_27#_M1013_d + N_A_86_27#_M1010_s N_A_86_27#_c_73_n N_A_86_27#_M1011_g N_A_86_27#_M1004_g
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.spice b/cells/a221o/sky130_fd_sc_lp__a221o_2.spice index e47e546..f4a558c 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_2.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_2.spice -* Created: Fri Aug 28 09:52:34 2020 +* Created: Wed Sep 2 09:21:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_4.lvs.report new file mode 100644 index 0000000..4cecb6b --- /dev/null +++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_4.sp ('sky130_fd_sc_lp__a221o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_4.spice ('sky130_fd_sc_lp__a221o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221o_4 sky130_fd_sc_lp__a221o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a221o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 C1 B1 B2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice index aa0180b..b94b255 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_4.pex.spice -* Created: Fri Aug 28 09:52:41 2020 +* Created: Wed Sep 2 09:21:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice index 49f6596..953f1cf 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_4.pxi.spice -* Created: Fri Aug 28 09:52:41 2020 +* Created: Wed Sep 2 09:21:22 2020 * x_PM_SKY130_FD_SC_LP__A221O_4%A_83_21# N_A_83_21#_M1013_s N_A_83_21#_M1020_s + N_A_83_21#_M1011_s N_A_83_21#_M1024_d N_A_83_21#_M1016_s N_A_83_21#_M1003_g
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.spice b/cells/a221o/sky130_fd_sc_lp__a221o_4.spice index c26036c..090d4fa 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_4.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_4.spice -* Created: Fri Aug 28 09:52:41 2020 +* Created: Wed Sep 2 09:21:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_lp.lvs.report new file mode 100644 index 0000000..bebaddd --- /dev/null +++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_lp.sp ('sky130_fd_sc_lp__a221o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice ('sky130_fd_sc_lp__a221o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221o_lp sky130_fd_sc_lp__a221o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a221o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MP (4 pins) + 4 4 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 4 4 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice index 44d1b5b..20f05c8 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_lp.pex.spice -* Created: Fri Aug 28 09:52:48 2020 +* Created: Wed Sep 2 09:21:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice index 77cc9bf..0f70a37 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_lp.pxi.spice -* Created: Fri Aug 28 09:52:48 2020 +* Created: Wed Sep 2 09:21:29 2020 * x_PM_SKY130_FD_SC_LP__A221O_LP%A_96_183# N_A_96_183#_M1011_d N_A_96_183#_M1008_d + N_A_96_183#_M1002_d N_A_96_183#_M1003_g N_A_96_183#_M1010_g N_A_96_183#_c_94_n
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice b/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice index f5250c6..a06f01e 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_lp.spice -* Created: Fri Aug 28 09:52:48 2020 +* Created: Wed Sep 2 09:21:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_m.lvs.report new file mode 100644 index 0000000..d118c4b --- /dev/null +++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_m.sp ('sky130_fd_sc_lp__a221o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_m.spice ('sky130_fd_sc_lp__a221o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221o_m sky130_fd_sc_lp__a221o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a221o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice index c925fc5..c4aff2d 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_m.pex.spice -* Created: Fri Aug 28 09:52:55 2020 +* Created: Wed Sep 2 09:21:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice index 9cb1ee9..000c818 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_m.pxi.spice -* Created: Fri Aug 28 09:52:55 2020 +* Created: Wed Sep 2 09:21:36 2020 * x_PM_SKY130_FD_SC_LP__A221O_M%A_33_153# N_A_33_153#_M1008_d N_A_33_153#_M1011_d + N_A_33_153#_M1009_d N_A_33_153#_c_79_n N_A_33_153#_M1004_g N_A_33_153#_M1002_g
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.spice b/cells/a221o/sky130_fd_sc_lp__a221o_m.spice index 5f6e52a..390be9c 100644 --- a/cells/a221o/sky130_fd_sc_lp__a221o_m.spice +++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221o_m.spice -* Created: Fri Aug 28 09:52:55 2020 +* Created: Wed Sep 2 09:21:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.lvs.report new file mode 100644 index 0000000..0a01667 --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_0.sp ('sky130_fd_sc_lp__a221oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice ('sky130_fd_sc_lp__a221oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221oi_0 sky130_fd_sc_lp__a221oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice index 2b429ea..87fbcd8 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_0.pex.spice -* Created: Fri Aug 28 09:53:02 2020 +* Created: Wed Sep 2 09:21:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice index 7eb719d..b30f9fd 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_0.pxi.spice -* Created: Fri Aug 28 09:53:02 2020 +* Created: Wed Sep 2 09:21:42 2020 * x_PM_SKY130_FD_SC_LP__A221OI_0%C1 N_C1_M1009_g N_C1_c_75_n N_C1_M1007_g + N_C1_c_80_n C1 C1 C1 N_C1_c_77_n PM_SKY130_FD_SC_LP__A221OI_0%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice index ecc2358..590f42f 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_0.spice -* Created: Fri Aug 28 09:53:02 2020 +* Created: Wed Sep 2 09:21:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.lvs.report new file mode 100644 index 0000000..aa1273b --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_1.sp ('sky130_fd_sc_lp__a221oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice ('sky130_fd_sc_lp__a221oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221oi_1 sky130_fd_sc_lp__a221oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice index c480c22..97af2aa 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_1.pex.spice -* Created: Fri Aug 28 09:53:18 2020 +* Created: Wed Sep 2 09:21:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice index 4186bd4..e34485e 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_1.pxi.spice -* Created: Fri Aug 28 09:53:18 2020 +* Created: Wed Sep 2 09:21:49 2020 * x_PM_SKY130_FD_SC_LP__A221OI_1%C1 N_C1_M1009_g N_C1_M1007_g C1 C1 N_C1_c_55_n + PM_SKY130_FD_SC_LP__A221OI_1%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice index 1199786..3e0776e 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_1.spice -* Created: Fri Aug 28 09:53:18 2020 +* Created: Wed Sep 2 09:21:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.lvs.report new file mode 100644 index 0000000..0b3ba7e --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_2.sp ('sky130_fd_sc_lp__a221oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice ('sky130_fd_sc_lp__a221oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221oi_2 sky130_fd_sc_lp__a221oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B2 B1 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice index 5e713f3..0965479 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_2.pex.spice -* Created: Fri Aug 28 09:53:25 2020 +* Created: Wed Sep 2 09:21:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice index 223a31b..38fb4c4 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_2.pxi.spice -* Created: Fri Aug 28 09:53:25 2020 +* Created: Wed Sep 2 09:21:55 2020 * x_PM_SKY130_FD_SC_LP__A221OI_2%C1 N_C1_M1005_g N_C1_M1003_g N_C1_M1018_g + N_C1_M1007_g C1 C1 N_C1_c_95_n PM_SKY130_FD_SC_LP__A221OI_2%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice index 903a145..68d6283 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_2.spice -* Created: Fri Aug 28 09:53:25 2020 +* Created: Wed Sep 2 09:21:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.lvs.report new file mode 100644 index 0000000..d5d5a8d --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_4.sp ('sky130_fd_sc_lp__a221oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice ('sky130_fd_sc_lp__a221oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:21:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221oi_4 sky130_fd_sc_lp__a221oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B2 B1 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice index c7641e6..78320d6 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_4.pex.spice -* Created: Fri Aug 28 09:53:32 2020 +* Created: Wed Sep 2 09:22:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice index d290151..3aa4eac 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_4.pxi.spice -* Created: Fri Aug 28 09:53:32 2020 +* Created: Wed Sep 2 09:22:01 2020 * x_PM_SKY130_FD_SC_LP__A221OI_4%C1 N_C1_M1016_g N_C1_c_144_n N_C1_M1007_g + N_C1_M1022_g N_C1_c_146_n N_C1_M1025_g N_C1_M1031_g N_C1_c_148_n N_C1_M1028_g
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice index 24cde74..c62b113 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_4.spice -* Created: Fri Aug 28 09:53:32 2020 +* Created: Wed Sep 2 09:22:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.lvs.report new file mode 100644 index 0000000..9e250b3 --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_lp.sp ('sky130_fd_sc_lp__a221oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice ('sky130_fd_sc_lp__a221oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221oi_lp sky130_fd_sc_lp__a221oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 12 11 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice index 91bc2db..a906dba 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_lp.pex.spice -* Created: Fri Aug 28 09:53:39 2020 +* Created: Wed Sep 2 09:22:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice index f5c0ffa..09e4731 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_lp.pxi.spice -* Created: Fri Aug 28 09:53:39 2020 +* Created: Wed Sep 2 09:22:08 2020 * x_PM_SKY130_FD_SC_LP__A221OI_LP%B2 N_B2_M1010_g N_B2_M1008_g N_B2_c_68_n + N_B2_c_69_n B2 B2 N_B2_c_71_n PM_SKY130_FD_SC_LP__A221OI_LP%B2
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice index 7a79adc..e800beb 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_lp.spice -* Created: Fri Aug 28 09:53:39 2020 +* Created: Wed Sep 2 09:22:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.lvs.report new file mode 100644 index 0000000..750a410 --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a221oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_m.sp ('sky130_fd_sc_lp__a221oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice ('sky130_fd_sc_lp__a221oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:11 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a221oi_m sky130_fd_sc_lp__a221oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice index 5966505..6c08934 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_m.pex.spice -* Created: Fri Aug 28 09:53:46 2020 +* Created: Wed Sep 2 09:22:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice index d6ec7cf..8330096 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_m.pxi.spice -* Created: Fri Aug 28 09:53:46 2020 +* Created: Wed Sep 2 09:22:14 2020 * x_PM_SKY130_FD_SC_LP__A221OI_M%C1 N_C1_M1009_g N_C1_c_74_n N_C1_M1007_g + N_C1_c_71_n C1 C1 C1 N_C1_c_73_n PM_SKY130_FD_SC_LP__A221OI_M%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice index 624be03..5a90593 100644 --- a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice +++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a221oi_m.spice -* Created: Fri Aug 28 09:53:46 2020 +* Created: Wed Sep 2 09:22:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_0.lvs.report new file mode 100644 index 0000000..c63c866 --- /dev/null +++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_0.sp ('sky130_fd_sc_lp__a22o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_0.spice ('sky130_fd_sc_lp__a22o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22o_0 sky130_fd_sc_lp__a22o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a22o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice index 3949ffd..e322b98 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_0.pex.spice -* Created: Fri Aug 28 09:53:53 2020 +* Created: Wed Sep 2 09:22:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice index a622fea..a9d1f97 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_0.pxi.spice -* Created: Fri Aug 28 09:53:53 2020 +* Created: Wed Sep 2 09:22:21 2020 * x_PM_SKY130_FD_SC_LP__A22O_0%A_85_155# N_A_85_155#_M1009_d N_A_85_155#_M1000_d + N_A_85_155#_M1008_g N_A_85_155#_M1005_g N_A_85_155#_c_67_n N_A_85_155#_c_68_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.spice b/cells/a22o/sky130_fd_sc_lp__a22o_0.spice index 2948e34..4030b84 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_0.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_0.spice -* Created: Fri Aug 28 09:53:53 2020 +* Created: Wed Sep 2 09:22:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_1.lvs.report new file mode 100644 index 0000000..84e41b1 --- /dev/null +++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_1.sp ('sky130_fd_sc_lp__a22o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_1.spice ('sky130_fd_sc_lp__a22o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22o_1 sky130_fd_sc_lp__a22o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a22o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice index 0e2ed40..dfb0b8d 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_1.pex.spice -* Created: Fri Aug 28 09:54:00 2020 +* Created: Wed Sep 2 09:22:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice index 5299c6b..b164eef 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_1.pxi.spice -* Created: Fri Aug 28 09:54:00 2020 +* Created: Wed Sep 2 09:22:27 2020 * x_PM_SKY130_FD_SC_LP__A22O_1%A_80_246# N_A_80_246#_M1004_d N_A_80_246#_M1002_d + N_A_80_246#_M1009_g N_A_80_246#_c_57_n N_A_80_246#_M1006_g N_A_80_246#_c_58_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.spice b/cells/a22o/sky130_fd_sc_lp__a22o_1.spice index 43bc195..0e96c89 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_1.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_1.spice -* Created: Fri Aug 28 09:54:00 2020 +* Created: Wed Sep 2 09:22:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_2.lvs.report new file mode 100644 index 0000000..6062377 --- /dev/null +++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_2.sp ('sky130_fd_sc_lp__a22o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_2.spice ('sky130_fd_sc_lp__a22o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22o_2 sky130_fd_sc_lp__a22o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a22o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B2 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice index 047649d..49e8854 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_2.pex.spice -* Created: Fri Aug 28 09:54:07 2020 +* Created: Wed Sep 2 09:22:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice index 4e674ff..dee55e8 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_2.pxi.spice -* Created: Fri Aug 28 09:54:07 2020 +* Created: Wed Sep 2 09:22:33 2020 * x_PM_SKY130_FD_SC_LP__A22O_2%A_94_249# N_A_94_249#_M1000_d N_A_94_249#_M1007_d + N_A_94_249#_M1010_s N_A_94_249#_M1004_d N_A_94_249#_M1008_g
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.spice b/cells/a22o/sky130_fd_sc_lp__a22o_2.spice index fb558ee..d515753 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_2.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_2.spice -* Created: Fri Aug 28 09:54:07 2020 +* Created: Wed Sep 2 09:22:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_4.lvs.report new file mode 100644 index 0000000..519d5f8 --- /dev/null +++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_4.sp ('sky130_fd_sc_lp__a22o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_4.spice ('sky130_fd_sc_lp__a22o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:37 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22o_4 sky130_fd_sc_lp__a22o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a22o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice index cd8df62..ac5830a 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_4.pex.spice -* Created: Fri Aug 28 09:54:23 2020 +* Created: Wed Sep 2 09:22:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice index 70eedd9..a4c17d0 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_4.pxi.spice -* Created: Fri Aug 28 09:54:23 2020 +* Created: Wed Sep 2 09:22:40 2020 * x_PM_SKY130_FD_SC_LP__A22O_4%A_103_263# N_A_103_263#_M1001_d + N_A_103_263#_M1007_s N_A_103_263#_M1005_s N_A_103_263#_M1019_s
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.spice b/cells/a22o/sky130_fd_sc_lp__a22o_4.spice index f340909..5b38ab8 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_4.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_4.spice -* Created: Fri Aug 28 09:54:23 2020 +* Created: Wed Sep 2 09:22:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_lp.lvs.report new file mode 100644 index 0000000..7eb9a6e --- /dev/null +++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_lp.sp ('sky130_fd_sc_lp__a22o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice ('sky130_fd_sc_lp__a22o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22o_lp sky130_fd_sc_lp__a22o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a22o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 12 11 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 B2 B1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice index 537e98c..43a4a83 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_lp.pex.spice -* Created: Fri Aug 28 09:54:30 2020 +* Created: Wed Sep 2 09:22:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice index 7b6dce4..a7a88d4 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_lp.pxi.spice -* Created: Fri Aug 28 09:54:30 2020 +* Created: Wed Sep 2 09:22:46 2020 * x_PM_SKY130_FD_SC_LP__A22O_LP%A1 N_A1_M1009_g N_A1_M1008_g N_A1_c_73_n + N_A1_c_74_n N_A1_c_75_n N_A1_c_76_n A1 A1 N_A1_c_78_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice b/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice index 382ee37..4cd73fa 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_lp.spice -* Created: Fri Aug 28 09:54:30 2020 +* Created: Wed Sep 2 09:22:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_m.lvs.report new file mode 100644 index 0000000..a2c1c47 --- /dev/null +++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_m.sp ('sky130_fd_sc_lp__a22o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_m.spice ('sky130_fd_sc_lp__a22o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22o_m sky130_fd_sc_lp__a22o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a22o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice index 34bd822..1684a50 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_m.pex.spice -* Created: Fri Aug 28 09:54:37 2020 +* Created: Wed Sep 2 09:22:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice index 8fbcdb5..9bf1675 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_m.pxi.spice -* Created: Fri Aug 28 09:54:37 2020 +* Created: Wed Sep 2 09:22:52 2020 * x_PM_SKY130_FD_SC_LP__A22O_M%A_85_317# N_A_85_317#_M1004_d N_A_85_317#_M1000_d + N_A_85_317#_M1002_g N_A_85_317#_M1001_g N_A_85_317#_c_66_n N_A_85_317#_c_72_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.spice b/cells/a22o/sky130_fd_sc_lp__a22o_m.spice index ec67cb2..06de83c 100644 --- a/cells/a22o/sky130_fd_sc_lp__a22o_m.spice +++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22o_m.spice -* Created: Fri Aug 28 09:54:37 2020 +* Created: Wed Sep 2 09:22:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.lvs.report new file mode 100644 index 0000000..4607b92 --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_0.sp ('sky130_fd_sc_lp__a22oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice ('sky130_fd_sc_lp__a22oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:22:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22oi_0 sky130_fd_sc_lp__a22oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice index a73ce95..1583ae3 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_0.pex.spice -* Created: Fri Aug 28 09:54:45 2020 +* Created: Wed Sep 2 09:22:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice index ea30dff..99aca25 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_0.pxi.spice -* Created: Fri Aug 28 09:54:45 2020 +* Created: Wed Sep 2 09:22:58 2020 * x_PM_SKY130_FD_SC_LP__A22OI_0%B2 N_B2_M1006_g N_B2_M1004_g N_B2_c_54_n + N_B2_c_59_n B2 B2 B2 N_B2_c_56_n PM_SKY130_FD_SC_LP__A22OI_0%B2
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice index 35ddc02..d45cd79 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_0.spice -* Created: Fri Aug 28 09:54:45 2020 +* Created: Wed Sep 2 09:22:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.lvs.report new file mode 100644 index 0000000..f963b73 --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_1.sp ('sky130_fd_sc_lp__a22oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice ('sky130_fd_sc_lp__a22oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22oi_1 sky130_fd_sc_lp__a22oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice index e96dc1b..272c5aa 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_1.pex.spice -* Created: Fri Aug 28 09:54:52 2020 +* Created: Wed Sep 2 09:23:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice index 7d60ec3..3c4f147 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_1.pxi.spice -* Created: Fri Aug 28 09:54:52 2020 +* Created: Wed Sep 2 09:23:05 2020 * x_PM_SKY130_FD_SC_LP__A22OI_1%B2 N_B2_c_47_n N_B2_M1004_g N_B2_M1002_g B2 B2 + N_B2_c_50_n PM_SKY130_FD_SC_LP__A22OI_1%B2
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice index a2ddb1f..78184d8 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_1.spice -* Created: Fri Aug 28 09:54:52 2020 +* Created: Wed Sep 2 09:23:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.lvs.report new file mode 100644 index 0000000..2e3b25b --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_2.sp ('sky130_fd_sc_lp__a22oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice ('sky130_fd_sc_lp__a22oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22oi_2 sky130_fd_sc_lp__a22oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 B2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice index fa4631f..0be0488 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_2.pex.spice -* Created: Fri Aug 28 09:54:59 2020 +* Created: Wed Sep 2 09:23:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice index 26afc70..5cceee4 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_2.pxi.spice -* Created: Fri Aug 28 09:54:59 2020 +* Created: Wed Sep 2 09:23:11 2020 * x_PM_SKY130_FD_SC_LP__A22OI_2%A1 N_A1_M1004_g N_A1_M1002_g N_A1_M1003_g + N_A1_M1014_g A1 A1 A1 A1 N_A1_c_75_n N_A1_c_76_n N_A1_c_77_n N_A1_c_78_n
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice index 862eb84..aa3ab8e 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_2.spice -* Created: Fri Aug 28 09:54:59 2020 +* Created: Wed Sep 2 09:23:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.lvs.report new file mode 100644 index 0000000..84f73f5 --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_4.sp ('sky130_fd_sc_lp__a22oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice ('sky130_fd_sc_lp__a22oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22oi_4 sky130_fd_sc_lp__a22oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice index a2c0aa6..dc638ee 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_4.pex.spice -* Created: Fri Aug 28 09:55:07 2020 +* Created: Wed Sep 2 09:23:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice index ae62326..a881ebf 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_4.pxi.spice -* Created: Fri Aug 28 09:55:07 2020 +* Created: Wed Sep 2 09:23:17 2020 * x_PM_SKY130_FD_SC_LP__A22OI_4%B2 N_B2_c_114_n N_B2_M1009_g N_B2_M1006_g + N_B2_c_116_n N_B2_M1010_g N_B2_M1015_g N_B2_c_118_n N_B2_M1018_g N_B2_M1023_g
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice index c1cea86..3b316a7 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_4.spice -* Created: Fri Aug 28 09:55:07 2020 +* Created: Wed Sep 2 09:23:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.lvs.report new file mode 100644 index 0000000..38e868e --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_lp.sp ('sky130_fd_sc_lp__a22oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice ('sky130_fd_sc_lp__a22oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22oi_lp sky130_fd_sc_lp__a22oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice index 71dc7b7..c6e0e6a 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_lp.pex.spice -* Created: Fri Aug 28 09:55:19 2020 +* Created: Wed Sep 2 09:23:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice index 877d164..76f0c0b 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_lp.pxi.spice -* Created: Fri Aug 28 09:55:19 2020 +* Created: Wed Sep 2 09:23:23 2020 * x_PM_SKY130_FD_SC_LP__A22OI_LP%B2 N_B2_M1004_g N_B2_M1005_g N_B2_c_58_n + N_B2_c_59_n B2 N_B2_c_61_n PM_SKY130_FD_SC_LP__A22OI_LP%B2
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice index 0326687..d98dcc6 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_lp.spice -* Created: Fri Aug 28 09:55:19 2020 +* Created: Wed Sep 2 09:23:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.lvs.report new file mode 100644 index 0000000..a1fd077 --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a22oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_m.sp ('sky130_fd_sc_lp__a22oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice ('sky130_fd_sc_lp__a22oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a22oi_m sky130_fd_sc_lp__a22oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice index dd6e05b..145779c 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_m.pex.spice -* Created: Fri Aug 28 09:55:31 2020 +* Created: Wed Sep 2 09:23:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice index eb28b5a..b553ac4 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_m.pxi.spice -* Created: Fri Aug 28 09:55:31 2020 +* Created: Wed Sep 2 09:23:29 2020 * x_PM_SKY130_FD_SC_LP__A22OI_M%B2 N_B2_c_56_n N_B2_M1007_g N_B2_M1005_g + N_B2_c_58_n N_B2_c_59_n N_B2_c_64_n B2 B2 B2 B2 B2 N_B2_c_61_n
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice index be405a5..26b821a 100644 --- a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice +++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a22oi_m.spice -* Created: Fri Aug 28 09:55:31 2020 +* Created: Wed Sep 2 09:23:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.lvs.report new file mode 100644 index 0000000..11bee3b --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_0.sp ('sky130_fd_sc_lp__a2bb2o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice ('sky130_fd_sc_lp__a2bb2o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2o_0 sky130_fd_sc_lp__a2bb2o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice index 727e943..6b42819 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_0.pex.spice -* Created: Fri Aug 28 09:55:38 2020 +* Created: Wed Sep 2 09:23:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice index 0ec8364..393c1fa 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_0.pxi.spice -* Created: Fri Aug 28 09:55:38 2020 +* Created: Wed Sep 2 09:23:36 2020 * x_PM_SKY130_FD_SC_LP__A2BB2O_0%A_59_194# N_A_59_194#_M1006_d N_A_59_194#_M1011_s + N_A_59_194#_c_95_n N_A_59_194#_M1003_g N_A_59_194#_c_96_n N_A_59_194#_c_97_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice index 065870e..e8f59ee 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_0.spice -* Created: Fri Aug 28 09:55:38 2020 +* Created: Wed Sep 2 09:23:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.lvs.report new file mode 100644 index 0000000..625a84d --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_1.sp ('sky130_fd_sc_lp__a2bb2o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice ('sky130_fd_sc_lp__a2bb2o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2o_1 sky130_fd_sc_lp__a2bb2o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice index 7236112..f72732a 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_1.pex.spice -* Created: Fri Aug 28 09:55:45 2020 +* Created: Wed Sep 2 09:23:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice index 529ce74..9c93c02 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_1.pxi.spice -* Created: Fri Aug 28 09:55:45 2020 +* Created: Wed Sep 2 09:23:43 2020 * x_PM_SKY130_FD_SC_LP__A2BB2O_1%A_91_269# N_A_91_269#_M1008_d N_A_91_269#_M1010_s + N_A_91_269#_M1011_g N_A_91_269#_M1009_g N_A_91_269#_c_92_n N_A_91_269#_c_99_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice index 4af4a8e..a6351da 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_1.spice -* Created: Fri Aug 28 09:55:45 2020 +* Created: Wed Sep 2 09:23:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.lvs.report new file mode 100644 index 0000000..9640b2b --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_2.sp ('sky130_fd_sc_lp__a2bb2o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice ('sky130_fd_sc_lp__a2bb2o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2o_2 sky130_fd_sc_lp__a2bb2o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice index 9709120..266c727 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_2.pex.spice -* Created: Fri Aug 28 09:55:52 2020 +* Created: Wed Sep 2 09:23:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice index a4875f7..1776aba 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_2.pxi.spice -* Created: Fri Aug 28 09:55:52 2020 +* Created: Wed Sep 2 09:23:49 2020 * x_PM_SKY130_FD_SC_LP__A2BB2O_2%B1 N_B1_M1001_g N_B1_c_79_n N_B1_M1013_g B1 B1 B1 + N_B1_c_81_n PM_SKY130_FD_SC_LP__A2BB2O_2%B1
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice index ca46a48..a0f192a 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_2.spice -* Created: Fri Aug 28 09:55:52 2020 +* Created: Wed Sep 2 09:23:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.lvs.report new file mode 100644 index 0000000..e23aa62 --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_4.sp ('sky130_fd_sc_lp__a2bb2o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice ('sky130_fd_sc_lp__a2bb2o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:23:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2o_4 sky130_fd_sc_lp__a2bb2o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A1_N A2_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice index 77354e8..9077895 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_4.pex.spice -* Created: Fri Aug 28 09:56:00 2020 +* Created: Wed Sep 2 09:23:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice index 4ed5ce1..b0b8fba 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_4.pxi.spice -* Created: Fri Aug 28 09:56:00 2020 +* Created: Wed Sep 2 09:23:56 2020 * x_PM_SKY130_FD_SC_LP__A2BB2O_4%B1 N_B1_M1002_g N_B1_M1011_g N_B1_M1007_g + N_B1_M1017_g N_B1_c_130_n N_B1_c_131_n N_B1_c_138_n N_B1_c_132_n N_B1_c_133_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice index c71d8b3..2ef0ee3 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_4.spice -* Created: Fri Aug 28 09:56:00 2020 +* Created: Wed Sep 2 09:23:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.lvs.report new file mode 100644 index 0000000..629cba6 --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_lp.sp ('sky130_fd_sc_lp__a2bb2o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice ('sky130_fd_sc_lp__a2bb2o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2o_lp sky130_fd_sc_lp__a2bb2o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 18 18 + + Instances: 10 10 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 1 1 MP (4 pins) + 5 5 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 5 5 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1_N A2_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice index b56187d..5a877e6 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_lp.pex.spice -* Created: Fri Aug 28 09:56:07 2020 +* Created: Wed Sep 2 09:24:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice index dcd6ca4..98c7eae 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_lp.pxi.spice -* Created: Fri Aug 28 09:56:07 2020 +* Created: Wed Sep 2 09:24:03 2020 * x_PM_SKY130_FD_SC_LP__A2BB2O_LP%B2 N_B2_M1008_g N_B2_M1009_g N_B2_c_100_n + N_B2_c_105_n B2 B2 N_B2_c_102_n PM_SKY130_FD_SC_LP__A2BB2O_LP%B2
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice index 8e7bced..18b2e92 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_lp.spice -* Created: Fri Aug 28 09:56:07 2020 +* Created: Wed Sep 2 09:24:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.lvs.report new file mode 100644 index 0000000..2487953 --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_m.sp ('sky130_fd_sc_lp__a2bb2o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice ('sky130_fd_sc_lp__a2bb2o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2o_m sky130_fd_sc_lp__a2bb2o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice index ab10cf8..3026d61 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_m.pex.spice -* Created: Fri Aug 28 09:56:20 2020 +* Created: Wed Sep 2 09:24:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice index 4d5c6e2..da1ceab 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_m.pxi.spice -* Created: Fri Aug 28 09:56:20 2020 +* Created: Wed Sep 2 09:24:10 2020 * x_PM_SKY130_FD_SC_LP__A2BB2O_M%A_85_345# N_A_85_345#_M1002_d N_A_85_345#_M1011_s + N_A_85_345#_M1006_g N_A_85_345#_M1000_g N_A_85_345#_c_81_n N_A_85_345#_c_82_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice index e170e5c..eba7eb1 100644 --- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice +++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2o_m.spice -* Created: Fri Aug 28 09:56:20 2020 +* Created: Wed Sep 2 09:24:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.lvs.report new file mode 100644 index 0000000..1ae2f36 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_0.sp ('sky130_fd_sc_lp__a2bb2oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice ('sky130_fd_sc_lp__a2bb2oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2oi_0 sky130_fd_sc_lp__a2bb2oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice index 0efb93a..a735e5e 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_0.pex.spice -* Created: Fri Aug 28 09:56:30 2020 +* Created: Wed Sep 2 09:24:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice index 7540d00..59a4259 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_0.pxi.spice -* Created: Fri Aug 28 09:56:30 2020 +* Created: Wed Sep 2 09:24:16 2020 * x_PM_SKY130_FD_SC_LP__A2BB2OI_0%A1_N N_A1_N_c_64_n N_A1_N_M1003_g N_A1_N_M1007_g + N_A1_N_c_67_n A1_N A1_N A1_N N_A1_N_c_69_n PM_SKY130_FD_SC_LP__A2BB2OI_0%A1_N
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice index 49150f5..9b78f99 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_0.spice -* Created: Fri Aug 28 09:56:30 2020 +* Created: Wed Sep 2 09:24:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.lvs.report new file mode 100644 index 0000000..131d774 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_1.sp ('sky130_fd_sc_lp__a2bb2oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice ('sky130_fd_sc_lp__a2bb2oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2oi_1 sky130_fd_sc_lp__a2bb2oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice index 25594b9..429405a 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_1.pex.spice -* Created: Fri Aug 28 09:56:38 2020 +* Created: Wed Sep 2 09:24:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice index dd963da..e106adc 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_1.pxi.spice -* Created: Fri Aug 28 09:56:38 2020 +* Created: Wed Sep 2 09:24:22 2020 * x_PM_SKY130_FD_SC_LP__A2BB2OI_1%A1_N N_A1_N_M1003_g N_A1_N_M1005_g A1_N A1_N + N_A1_N_c_58_n N_A1_N_c_59_n PM_SKY130_FD_SC_LP__A2BB2OI_1%A1_N
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice index 2d04e0e..b72a7f0 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_1.spice -* Created: Fri Aug 28 09:56:38 2020 +* Created: Wed Sep 2 09:24:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.lvs.report new file mode 100644 index 0000000..58fc338 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_2.sp ('sky130_fd_sc_lp__a2bb2oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice ('sky130_fd_sc_lp__a2bb2oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2oi_2 sky130_fd_sc_lp__a2bb2oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A1_N A2_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice index 6aba998..90eb176 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_2.pex.spice -* Created: Fri Aug 28 09:56:45 2020 +* Created: Wed Sep 2 09:24:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice index fe4e198..9cf4f35 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_2.pxi.spice -* Created: Fri Aug 28 09:56:45 2020 +* Created: Wed Sep 2 09:24:29 2020 * x_PM_SKY130_FD_SC_LP__A2BB2OI_2%B1 N_B1_M1015_g N_B1_M1002_g N_B1_M1018_g + N_B1_M1011_g N_B1_c_108_n N_B1_c_109_n N_B1_c_114_n N_B1_c_115_n N_B1_c_110_n
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice index 11dc4be..3397d88 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_2.spice -* Created: Fri Aug 28 09:56:45 2020 +* Created: Wed Sep 2 09:24:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.lvs.report new file mode 100644 index 0000000..65760e1 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_4.sp ('sky130_fd_sc_lp__a2bb2oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice ('sky130_fd_sc_lp__a2bb2oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:32 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2oi_4 sky130_fd_sc_lp__a2bb2oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A1_N A2_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice index 53a9fd2..d165cbe 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_4.pex.spice -* Created: Fri Aug 28 09:56:52 2020 +* Created: Wed Sep 2 09:24:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice index d2aabbc..f40e590 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_4.pxi.spice -* Created: Fri Aug 28 09:56:52 2020 +* Created: Wed Sep 2 09:24:36 2020 * x_PM_SKY130_FD_SC_LP__A2BB2OI_4%B1 N_B1_M1002_g N_B1_M1003_g N_B1_M1005_g + N_B1_M1013_g N_B1_M1014_g N_B1_M1025_g N_B1_M1035_g N_B1_c_164_n N_B1_M1018_g
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice index 7570a90..b1d5533 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_4.spice -* Created: Fri Aug 28 09:56:52 2020 +* Created: Wed Sep 2 09:24:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.lvs.report new file mode 100644 index 0000000..b3af354 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_lp.sp ('sky130_fd_sc_lp__a2bb2oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice ('sky130_fd_sc_lp__a2bb2oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2oi_lp sky130_fd_sc_lp__a2bb2oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 16 16 + + Instances: 8 8 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 14 13 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 4 4 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 4 4 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2_N A1_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice index f505438..b13e8fc 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_lp.pex.spice -* Created: Fri Aug 28 09:57:00 2020 +* Created: Wed Sep 2 09:24:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice index e1eb4e6..55ae567 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice -* Created: Fri Aug 28 09:57:00 2020 +* Created: Wed Sep 2 09:24:42 2020 * x_PM_SKY130_FD_SC_LP__A2BB2OI_LP%B1 N_B1_M1003_g N_B1_M1010_g B1 B1 N_B1_c_82_n + PM_SKY130_FD_SC_LP__A2BB2OI_LP%B1
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice index 33af1a7..272e8c8 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_lp.spice -* Created: Fri Aug 28 09:57:00 2020 +* Created: Wed Sep 2 09:24:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.lvs.report new file mode 100644 index 0000000..0da4f8b --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_m.sp ('sky130_fd_sc_lp__a2bb2oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice ('sky130_fd_sc_lp__a2bb2oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a2bb2oi_m sky130_fd_sc_lp__a2bb2oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice index f67651a..3d6df83 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_m.pex.spice -* Created: Fri Aug 28 09:57:08 2020 +* Created: Wed Sep 2 09:24:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice index d801f3c..fedcff2 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_m.pxi.spice -* Created: Fri Aug 28 09:57:08 2020 +* Created: Wed Sep 2 09:24:49 2020 * x_PM_SKY130_FD_SC_LP__A2BB2OI_M%A1_N N_A1_N_c_76_n N_A1_N_c_84_n N_A1_N_c_85_n + N_A1_N_c_77_n N_A1_N_c_78_n N_A1_N_M1007_g N_A1_N_c_79_n N_A1_N_M1005_g
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice index 7f0af50..411967c 100644 --- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice +++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a2bb2oi_m.spice -* Created: Fri Aug 28 09:57:08 2020 +* Created: Wed Sep 2 09:24:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_0.lvs.report new file mode 100644 index 0000000..900de11 --- /dev/null +++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_0.sp ('sky130_fd_sc_lp__a311o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_0.spice ('sky130_fd_sc_lp__a311o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311o_0 sky130_fd_sc_lp__a311o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a311o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice index 3d9bcc5..ee02969 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_0.pex.spice -* Created: Fri Aug 28 09:57:20 2020 +* Created: Wed Sep 2 09:24:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice index 53c2c35..725cedb 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_0.pxi.spice -* Created: Fri Aug 28 09:57:20 2020 +* Created: Wed Sep 2 09:24:56 2020 * x_PM_SKY130_FD_SC_LP__A311O_0%A_72_312# N_A_72_312#_M1001_d N_A_72_312#_M1003_d + N_A_72_312#_M1000_d N_A_72_312#_M1006_g N_A_72_312#_M1004_g N_A_72_312#_c_96_n
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.spice b/cells/a311o/sky130_fd_sc_lp__a311o_0.spice index 1200c5c..f40d956 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_0.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_0.spice -* Created: Fri Aug 28 09:57:20 2020 +* Created: Wed Sep 2 09:24:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_1.lvs.report new file mode 100644 index 0000000..3af052f --- /dev/null +++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_1.sp ('sky130_fd_sc_lp__a311o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_1.spice ('sky130_fd_sc_lp__a311o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:24:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311o_1 sky130_fd_sc_lp__a311o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a311o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice index e07253e..6e689f0 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_1.pex.spice -* Created: Fri Aug 28 09:57:31 2020 +* Created: Wed Sep 2 09:25:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice index 264bdb8..26eeccb 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_1.pxi.spice -* Created: Fri Aug 28 09:57:31 2020 +* Created: Wed Sep 2 09:25:02 2020 * x_PM_SKY130_FD_SC_LP__A311O_1%A_80_21# N_A_80_21#_M1002_d N_A_80_21#_M1008_d + N_A_80_21#_M1010_d N_A_80_21#_c_58_n N_A_80_21#_M1004_g N_A_80_21#_M1003_g
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.spice b/cells/a311o/sky130_fd_sc_lp__a311o_1.spice index cf7391c..5813fcf 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_1.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_1.spice -* Created: Fri Aug 28 09:57:31 2020 +* Created: Wed Sep 2 09:25:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_2.lvs.report new file mode 100644 index 0000000..4d0ffa8 --- /dev/null +++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_2.sp ('sky130_fd_sc_lp__a311o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_2.spice ('sky130_fd_sc_lp__a311o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311o_2 sky130_fd_sc_lp__a311o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a311o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice index 777c6f7..897588f 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_2.pex.spice -* Created: Fri Aug 28 09:57:38 2020 +* Created: Wed Sep 2 09:25:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice index 0442230..82655af 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_2.pxi.spice -* Created: Fri Aug 28 09:57:38 2020 +* Created: Wed Sep 2 09:25:08 2020 * x_PM_SKY130_FD_SC_LP__A311O_2%A_85_21# N_A_85_21#_M1000_d N_A_85_21#_M1008_d + N_A_85_21#_M1002_d N_A_85_21#_c_67_n N_A_85_21#_M1012_g N_A_85_21#_M1001_g
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.spice b/cells/a311o/sky130_fd_sc_lp__a311o_2.spice index c572934..33cd6b9 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_2.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_2.spice -* Created: Fri Aug 28 09:57:38 2020 +* Created: Wed Sep 2 09:25:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_4.lvs.report new file mode 100644 index 0000000..13ce9ac --- /dev/null +++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_4.sp ('sky130_fd_sc_lp__a311o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_4.spice ('sky130_fd_sc_lp__a311o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:11 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311o_4 sky130_fd_sc_lp__a311o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a311o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A3 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice index 68e5a1f..486ae7f 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_4.pex.spice -* Created: Fri Aug 28 09:57:45 2020 +* Created: Wed Sep 2 09:25:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice index f1b45ea..ac8c6fe 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_4.pxi.spice -* Created: Fri Aug 28 09:57:45 2020 +* Created: Wed Sep 2 09:25:14 2020 * x_PM_SKY130_FD_SC_LP__A311O_4%C1 N_C1_M1002_g N_C1_M1013_g N_C1_M1010_g + N_C1_M1026_g C1 C1 N_C1_c_138_n PM_SKY130_FD_SC_LP__A311O_4%C1
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.spice b/cells/a311o/sky130_fd_sc_lp__a311o_4.spice index e705274..a794ef1 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_4.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_4.spice -* Created: Fri Aug 28 09:57:45 2020 +* Created: Wed Sep 2 09:25:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_lp.lvs.report new file mode 100644 index 0000000..ca7da62 --- /dev/null +++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_lp.sp ('sky130_fd_sc_lp__a311o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice ('sky130_fd_sc_lp__a311o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311o_lp sky130_fd_sc_lp__a311o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a311o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 18 18 + + Instances: 9 9 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 16 15 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice index 85c1f3d..2ec71dd 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_lp.pex.spice -* Created: Fri Aug 28 09:57:52 2020 +* Created: Wed Sep 2 09:25:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice index a342e77..90fb810 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_lp.pxi.spice -* Created: Fri Aug 28 09:57:52 2020 +* Created: Wed Sep 2 09:25:20 2020 * x_PM_SKY130_FD_SC_LP__A311O_LP%A_85_21# N_A_85_21#_M1002_d N_A_85_21#_M1013_d + N_A_85_21#_M1009_d N_A_85_21#_M1014_g N_A_85_21#_c_107_n N_A_85_21#_M1006_g
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice b/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice index 4473012..a01cafa 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_lp.spice -* Created: Fri Aug 28 09:57:52 2020 +* Created: Wed Sep 2 09:25:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_m.lvs.report new file mode 100644 index 0000000..66c916d --- /dev/null +++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_m.sp ('sky130_fd_sc_lp__a311o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_m.spice ('sky130_fd_sc_lp__a311o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:24 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311o_m sky130_fd_sc_lp__a311o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a311o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice index d9b617c..94c645f 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_m.pex.spice -* Created: Fri Aug 28 09:57:59 2020 +* Created: Wed Sep 2 09:25:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice index 030a429..d7869de 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_m.pxi.spice -* Created: Fri Aug 28 09:57:59 2020 +* Created: Wed Sep 2 09:25:27 2020 * x_PM_SKY130_FD_SC_LP__A311O_M%A3 N_A3_M1011_g N_A3_c_78_n N_A3_M1006_g + N_A3_c_79_n A3 A3 A3 N_A3_c_81_n N_A3_c_82_n PM_SKY130_FD_SC_LP__A311O_M%A3
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.spice b/cells/a311o/sky130_fd_sc_lp__a311o_m.spice index c4f287a..d3b9f5e 100644 --- a/cells/a311o/sky130_fd_sc_lp__a311o_m.spice +++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311o_m.spice -* Created: Fri Aug 28 09:57:59 2020 +* Created: Wed Sep 2 09:25:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.lvs.report new file mode 100644 index 0000000..1e7d7f7 --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_0.sp ('sky130_fd_sc_lp__a311oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice ('sky130_fd_sc_lp__a311oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311oi_0 sky130_fd_sc_lp__a311oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice index 2dd8fe4..291c74e 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_0.pex.spice -* Created: Fri Aug 28 09:58:07 2020 +* Created: Wed Sep 2 09:25:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice index afdbe6e..979ba3b 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_0.pxi.spice -* Created: Fri Aug 28 09:58:07 2020 +* Created: Wed Sep 2 09:25:33 2020 * x_PM_SKY130_FD_SC_LP__A311OI_0%A3 N_A3_c_80_n N_A3_M1000_g N_A3_c_73_n + N_A3_M1006_g N_A3_c_74_n N_A3_c_75_n N_A3_c_76_n N_A3_c_77_n N_A3_c_83_n A3 A3
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice index c649c1f..ab979fa 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_0.spice -* Created: Fri Aug 28 09:58:07 2020 +* Created: Wed Sep 2 09:25:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.lvs.report new file mode 100644 index 0000000..cf91268 --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_1.sp ('sky130_fd_sc_lp__a311oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice ('sky130_fd_sc_lp__a311oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:37 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311oi_1 sky130_fd_sc_lp__a311oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice index 242f81c..c7199ba 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_1.pex.spice -* Created: Fri Aug 28 09:58:14 2020 +* Created: Wed Sep 2 09:25:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice index 9f03695..fb8c26f 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_1.pxi.spice -* Created: Fri Aug 28 09:58:14 2020 +* Created: Wed Sep 2 09:25:40 2020 * x_PM_SKY130_FD_SC_LP__A311OI_1%A3 N_A3_M1003_g N_A3_M1009_g A3 A3 N_A3_c_53_n + N_A3_c_54_n PM_SKY130_FD_SC_LP__A311OI_1%A3
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice index 5baa005..b36f9da 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_1.spice -* Created: Fri Aug 28 09:58:14 2020 +* Created: Wed Sep 2 09:25:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.lvs.report new file mode 100644 index 0000000..08be8a9 --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_2.sp ('sky130_fd_sc_lp__a311oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice ('sky130_fd_sc_lp__a311oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311oi_2 sky130_fd_sc_lp__a311oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice index 5cf3643..5d871af 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_2.pex.spice -* Created: Fri Aug 28 09:58:26 2020 +* Created: Wed Sep 2 09:25:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice index 93eb85c..78dacd0 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_2.pxi.spice -* Created: Fri Aug 28 09:58:26 2020 +* Created: Wed Sep 2 09:25:46 2020 * x_PM_SKY130_FD_SC_LP__A311OI_2%A3 N_A3_M1014_g N_A3_M1013_g N_A3_M1015_g + N_A3_M1018_g N_A3_c_102_n A3 N_A3_c_103_n N_A3_c_104_n
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice index ad35922..50d9d91 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_2.spice -* Created: Fri Aug 28 09:58:26 2020 +* Created: Wed Sep 2 09:25:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.lvs.report new file mode 100644 index 0000000..47a17da --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_4.sp ('sky130_fd_sc_lp__a311oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice ('sky130_fd_sc_lp__a311oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311oi_4 sky130_fd_sc_lp__a311oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice index c68540c..a8cc74d 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_4.pex.spice -* Created: Fri Aug 28 09:58:36 2020 +* Created: Wed Sep 2 09:25:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice index 4c4403a..4012a6c 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_4.pxi.spice -* Created: Fri Aug 28 09:58:36 2020 +* Created: Wed Sep 2 09:25:52 2020 * x_PM_SKY130_FD_SC_LP__A311OI_4%A3 N_A3_c_151_n N_A3_M1012_g N_A3_M1008_g + N_A3_c_153_n N_A3_M1022_g N_A3_M1023_g N_A3_c_155_n N_A3_M1024_g N_A3_M1026_g
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice index 59409bb..d2dedef 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_4.spice -* Created: Fri Aug 28 09:58:36 2020 +* Created: Wed Sep 2 09:25:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.lvs.report new file mode 100644 index 0000000..9919d18 --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_lp.sp ('sky130_fd_sc_lp__a311oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice ('sky130_fd_sc_lp__a311oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:25:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311oi_lp sky130_fd_sc_lp__a311oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice index a71057c..a106147 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_lp.pex.spice -* Created: Fri Aug 28 09:58:44 2020 +* Created: Wed Sep 2 09:25:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice index 11a2a88..4b01f0d 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_lp.pxi.spice -* Created: Fri Aug 28 09:58:44 2020 +* Created: Wed Sep 2 09:25:59 2020 * x_PM_SKY130_FD_SC_LP__A311OI_LP%A1 N_A1_c_78_n N_A1_M1001_g N_A1_M1006_g + N_A1_c_75_n A1 N_A1_c_76_n N_A1_c_77_n PM_SKY130_FD_SC_LP__A311OI_LP%A1
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice index c1c8906..e01b969 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_lp.spice -* Created: Fri Aug 28 09:58:44 2020 +* Created: Wed Sep 2 09:25:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.lvs.report new file mode 100644 index 0000000..57c608d --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a311oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_m.sp ('sky130_fd_sc_lp__a311oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice ('sky130_fd_sc_lp__a311oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a311oi_m sky130_fd_sc_lp__a311oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice index a2fbe28..a3dceca 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_m.pex.spice -* Created: Fri Aug 28 09:58:51 2020 +* Created: Wed Sep 2 09:26:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice index bcf46a3..acd5e47 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_m.pxi.spice -* Created: Fri Aug 28 09:58:51 2020 +* Created: Wed Sep 2 09:26:05 2020 * x_PM_SKY130_FD_SC_LP__A311OI_M%A3 N_A3_c_77_n N_A3_c_84_n N_A3_c_85_n + N_A3_M1006_g N_A3_c_78_n N_A3_M1001_g N_A3_c_79_n N_A3_c_80_n A3 A3 A3 A3 A3
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice index ca58b46..3be5c00 100644 --- a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice +++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a311oi_m.spice -* Created: Fri Aug 28 09:58:51 2020 +* Created: Wed Sep 2 09:26:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_0.lvs.report new file mode 100644 index 0000000..a115a58 --- /dev/null +++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_0.sp ('sky130_fd_sc_lp__a31o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_0.spice ('sky130_fd_sc_lp__a31o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:09 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31o_0 sky130_fd_sc_lp__a31o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a31o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice index 1e0fbf7..f920011 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_0.pex.spice -* Created: Fri Aug 28 09:58:58 2020 +* Created: Wed Sep 2 09:26:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice index 7429ce6..a55fc19 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_0.pxi.spice -* Created: Fri Aug 28 09:58:58 2020 +* Created: Wed Sep 2 09:26:12 2020 * x_PM_SKY130_FD_SC_LP__A31O_0%A_86_241# N_A_86_241#_M1009_d N_A_86_241#_M1007_d + N_A_86_241#_M1005_g N_A_86_241#_M1004_g N_A_86_241#_c_70_n N_A_86_241#_c_78_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.spice b/cells/a31o/sky130_fd_sc_lp__a31o_0.spice index 90ea4b9..5cf3422 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_0.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_0.spice -* Created: Fri Aug 28 09:58:58 2020 +* Created: Wed Sep 2 09:26:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_1.lvs.report new file mode 100644 index 0000000..4d5062b --- /dev/null +++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_1.sp ('sky130_fd_sc_lp__a31o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_1.spice ('sky130_fd_sc_lp__a31o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31o_1 sky130_fd_sc_lp__a31o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a31o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice index 86efb77..20747e0 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_1.pex.spice -* Created: Fri Aug 28 09:59:05 2020 +* Created: Wed Sep 2 09:26:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice index 4aaf966..0fa53dc 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_1.pxi.spice -* Created: Fri Aug 28 09:59:05 2020 +* Created: Wed Sep 2 09:26:18 2020 * x_PM_SKY130_FD_SC_LP__A31O_1%A_80_21# N_A_80_21#_M1007_d N_A_80_21#_M1006_d + N_A_80_21#_M1004_g N_A_80_21#_M1001_g N_A_80_21#_c_54_n N_A_80_21#_c_55_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.spice b/cells/a31o/sky130_fd_sc_lp__a31o_1.spice index 8f3a866..a74a798 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_1.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_1.spice -* Created: Fri Aug 28 09:59:05 2020 +* Created: Wed Sep 2 09:26:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_2.lvs.report new file mode 100644 index 0000000..9767701 --- /dev/null +++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_2.sp ('sky130_fd_sc_lp__a31o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_2.spice ('sky130_fd_sc_lp__a31o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31o_2 sky130_fd_sc_lp__a31o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a31o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice index fb6fae8..49b3489 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_2.pex.spice -* Created: Fri Aug 28 09:59:12 2020 +* Created: Wed Sep 2 09:26:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice index 8d7615b..fa831d0 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_2.pxi.spice -* Created: Fri Aug 28 09:59:12 2020 +* Created: Wed Sep 2 09:26:24 2020 * x_PM_SKY130_FD_SC_LP__A31O_2%A_85_23# N_A_85_23#_M1011_d N_A_85_23#_M1010_d + N_A_85_23#_M1008_g N_A_85_23#_M1002_g N_A_85_23#_c_60_n N_A_85_23#_M1009_g
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.spice b/cells/a31o/sky130_fd_sc_lp__a31o_2.spice index c4c9ab1..98231a0 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_2.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_2.spice -* Created: Fri Aug 28 09:59:12 2020 +* Created: Wed Sep 2 09:26:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_4.lvs.report new file mode 100644 index 0000000..8d82e1c --- /dev/null +++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_4.sp ('sky130_fd_sc_lp__a31o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_4.spice ('sky130_fd_sc_lp__a31o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31o_4 sky130_fd_sc_lp__a31o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a31o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A3 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice index b4ce02a..c633a04 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_4.pex.spice -* Created: Fri Aug 28 09:59:19 2020 +* Created: Wed Sep 2 09:26:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice index 800ecb3..9cf9375 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_4.pxi.spice -* Created: Fri Aug 28 09:59:19 2020 +* Created: Wed Sep 2 09:26:31 2020 * x_PM_SKY130_FD_SC_LP__A31O_4%B1 N_B1_M1009_g N_B1_M1011_g N_B1_c_115_n + N_B1_M1016_g N_B1_M1022_g N_B1_c_118_n B1 B1 N_B1_c_120_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.spice b/cells/a31o/sky130_fd_sc_lp__a31o_4.spice index c2da5dc..b90c4f6 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_4.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_4.spice -* Created: Fri Aug 28 09:59:19 2020 +* Created: Wed Sep 2 09:26:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_lp.lvs.report new file mode 100644 index 0000000..15823c0 --- /dev/null +++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_lp.sp ('sky130_fd_sc_lp__a31o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice ('sky130_fd_sc_lp__a31o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31o_lp sky130_fd_sc_lp__a31o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a31o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice index a021451..c206d04 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_lp.pex.spice -* Created: Fri Aug 28 09:59:32 2020 +* Created: Wed Sep 2 09:26:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice index 424a0f7..86769cf 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_lp.pxi.spice -* Created: Fri Aug 28 09:59:32 2020 +* Created: Wed Sep 2 09:26:37 2020 * x_PM_SKY130_FD_SC_LP__A31O_LP%B1 N_B1_c_73_n N_B1_M1007_g N_B1_c_74_n + N_B1_M1003_g N_B1_M1005_g N_B1_c_76_n B1 N_B1_c_78_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice b/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice index 9c9804e..4ef587d 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_lp.spice -* Created: Fri Aug 28 09:59:32 2020 +* Created: Wed Sep 2 09:26:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_m.lvs.report new file mode 100644 index 0000000..9fff71d --- /dev/null +++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_m.sp ('sky130_fd_sc_lp__a31o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_m.spice ('sky130_fd_sc_lp__a31o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31o_m sky130_fd_sc_lp__a31o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a31o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice index 7bdc7bb..72004c1 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_m.pex.spice -* Created: Fri Aug 28 09:59:43 2020 +* Created: Wed Sep 2 09:26:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice index 354d95e..10ab630 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_m.pxi.spice -* Created: Fri Aug 28 09:59:43 2020 +* Created: Wed Sep 2 09:26:43 2020 * x_PM_SKY130_FD_SC_LP__A31O_M%A_86_172# N_A_86_172#_M1001_d N_A_86_172#_M1007_d + N_A_86_172#_c_86_n N_A_86_172#_c_98_n N_A_86_172#_c_99_n N_A_86_172#_M1005_g
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.spice b/cells/a31o/sky130_fd_sc_lp__a31o_m.spice index 7c298c3..0c47407 100644 --- a/cells/a31o/sky130_fd_sc_lp__a31o_m.spice +++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31o_m.spice -* Created: Fri Aug 28 09:59:43 2020 +* Created: Wed Sep 2 09:26:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.lvs.report new file mode 100644 index 0000000..c10e229 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_0.sp ('sky130_fd_sc_lp__a31oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice ('sky130_fd_sc_lp__a31oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31oi_0 sky130_fd_sc_lp__a31oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice index 4bc7c1c..b0352f7 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_0.pex.spice -* Created: Fri Aug 28 09:59:51 2020 +* Created: Wed Sep 2 09:26:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice index a80937e..a942584 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_0.pxi.spice -* Created: Fri Aug 28 09:59:51 2020 +* Created: Wed Sep 2 09:26:50 2020 * x_PM_SKY130_FD_SC_LP__A31OI_0%A3 N_A3_c_55_n N_A3_M1005_g N_A3_c_56_n + N_A3_M1002_g N_A3_c_57_n N_A3_c_58_n N_A3_c_63_n A3 A3 A3 N_A3_c_60_n
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice index 943cab1..064b41c 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_0.spice -* Created: Fri Aug 28 09:59:51 2020 +* Created: Wed Sep 2 09:26:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.lvs.report new file mode 100644 index 0000000..0e09e10 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_1.sp ('sky130_fd_sc_lp__a31oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice ('sky130_fd_sc_lp__a31oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31oi_1 sky130_fd_sc_lp__a31oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice index 3a8b1b8..7e5c9f5 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_1.pex.spice -* Created: Fri Aug 28 09:59:58 2020 +* Created: Wed Sep 2 09:26:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice index 93cbd4f..376496a 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_1.pxi.spice -* Created: Fri Aug 28 09:59:58 2020 +* Created: Wed Sep 2 09:26:56 2020 * x_PM_SKY130_FD_SC_LP__A31OI_1%A3 N_A3_M1003_g N_A3_M1000_g A3 A3 N_A3_c_47_n + PM_SKY130_FD_SC_LP__A31OI_1%A3
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice index c8c69e5..dd02abf 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_1.spice -* Created: Fri Aug 28 09:59:58 2020 +* Created: Wed Sep 2 09:26:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.lvs.report new file mode 100644 index 0000000..9588e61 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_2.sp ('sky130_fd_sc_lp__a31oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice ('sky130_fd_sc_lp__a31oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:26:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31oi_2 sky130_fd_sc_lp__a31oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice index 11e181d..184932f 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_2.pex.spice -* Created: Fri Aug 28 10:00:05 2020 +* Created: Wed Sep 2 09:27:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice index 8da6964..ddac9ad 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_2.pxi.spice -* Created: Fri Aug 28 10:00:05 2020 +* Created: Wed Sep 2 09:27:02 2020 * x_PM_SKY130_FD_SC_LP__A31OI_2%A3 N_A3_c_81_n N_A3_M1009_g N_A3_M1005_g + N_A3_c_83_n N_A3_c_84_n N_A3_M1012_g N_A3_M1014_g N_A3_c_86_n A3 N_A3_c_88_n
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice index f5b0160..b77750d 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_2.spice -* Created: Fri Aug 28 10:00:05 2020 +* Created: Wed Sep 2 09:27:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.lvs.report new file mode 100644 index 0000000..0aa3ef4 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_4.sp ('sky130_fd_sc_lp__a31oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice ('sky130_fd_sc_lp__a31oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31oi_4 sky130_fd_sc_lp__a31oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice index 61f3b56..cbffec7 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_4.pex.spice -* Created: Fri Aug 28 10:00:13 2020 +* Created: Wed Sep 2 09:27:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice index 2ab50f5..04a9429 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_4.pxi.spice -* Created: Fri Aug 28 10:00:13 2020 +* Created: Wed Sep 2 09:27:09 2020 * x_PM_SKY130_FD_SC_LP__A31OI_4%A3 N_A3_M1011_g N_A3_M1010_g N_A3_M1023_g + N_A3_M1021_g N_A3_M1027_g N_A3_M1022_g N_A3_M1029_g N_A3_M1030_g A3 A3 A3 A3
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice index dcd5fc2..102fdf6 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_4.spice -* Created: Fri Aug 28 10:00:13 2020 +* Created: Wed Sep 2 09:27:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.lvs.report new file mode 100644 index 0000000..99d9e43 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_lp.sp ('sky130_fd_sc_lp__a31oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice ('sky130_fd_sc_lp__a31oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31oi_lp sky130_fd_sc_lp__a31oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 10 9 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice index 351b9fc..afcee2c 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_lp.pex.spice -* Created: Fri Aug 28 10:00:20 2020 +* Created: Wed Sep 2 09:27:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice index 6fa0c9d..df42985 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_lp.pxi.spice -* Created: Fri Aug 28 10:00:20 2020 +* Created: Wed Sep 2 09:27:15 2020 * x_PM_SKY130_FD_SC_LP__A31OI_LP%A3 N_A3_M1007_g N_A3_c_63_n N_A3_M1002_g + N_A3_c_64_n N_A3_c_65_n N_A3_c_66_n N_A3_c_67_n A3 A3 N_A3_c_68_n N_A3_c_69_n
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice index 66cb2d5..3813cc8 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_lp.spice -* Created: Fri Aug 28 10:00:20 2020 +* Created: Wed Sep 2 09:27:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.lvs.report new file mode 100644 index 0000000..104e491 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a31oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_m.sp ('sky130_fd_sc_lp__a31oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice ('sky130_fd_sc_lp__a31oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a31oi_m sky130_fd_sc_lp__a31oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice index 2e180bb..7d5cbaf 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_m.pex.spice -* Created: Fri Aug 28 10:00:34 2020 +* Created: Wed Sep 2 09:27:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice index 1bd6e28..f21bd56 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_m.pxi.spice -* Created: Fri Aug 28 10:00:34 2020 +* Created: Wed Sep 2 09:27:21 2020 * x_PM_SKY130_FD_SC_LP__A31OI_M%A3 N_A3_c_63_n N_A3_c_64_n N_A3_c_65_n N_A3_c_71_n + N_A3_c_72_n N_A3_c_73_n N_A3_M1007_g N_A3_c_66_n N_A3_M1006_g N_A3_c_67_n A3
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice index 836a46c..acc5888 100644 --- a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice +++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a31oi_m.spice -* Created: Fri Aug 28 10:00:34 2020 +* Created: Wed Sep 2 09:27:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_0.lvs.report new file mode 100644 index 0000000..0a2a7b5 --- /dev/null +++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_0.sp ('sky130_fd_sc_lp__a32o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_0.spice ('sky130_fd_sc_lp__a32o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32o_0 sky130_fd_sc_lp__a32o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a32o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice index 9d8b5c8..9fc3635 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_0.pex.spice -* Created: Fri Aug 28 10:00:47 2020 +* Created: Wed Sep 2 09:27:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice index bca2b76..d0d6568 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_0.pxi.spice -* Created: Fri Aug 28 10:00:47 2020 +* Created: Wed Sep 2 09:27:28 2020 * x_PM_SKY130_FD_SC_LP__A32O_0%A_80_21# N_A_80_21#_M1007_d N_A_80_21#_M1001_d + N_A_80_21#_M1005_g N_A_80_21#_M1009_g N_A_80_21#_c_79_n N_A_80_21#_c_88_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.spice b/cells/a32o/sky130_fd_sc_lp__a32o_0.spice index b3c5ac9..be6453e 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_0.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_0.spice -* Created: Fri Aug 28 10:00:47 2020 +* Created: Wed Sep 2 09:27:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_1.lvs.report new file mode 100644 index 0000000..a8e7294 --- /dev/null +++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_1.sp ('sky130_fd_sc_lp__a32o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_1.spice ('sky130_fd_sc_lp__a32o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32o_1 sky130_fd_sc_lp__a32o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a32o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice index 4c32106..f297580 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_1.pex.spice -* Created: Fri Aug 28 10:00:55 2020 +* Created: Wed Sep 2 09:27:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice index 8c27af8..7dd468c 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_1.pxi.spice -* Created: Fri Aug 28 10:00:55 2020 +* Created: Wed Sep 2 09:27:34 2020 * x_PM_SKY130_FD_SC_LP__A32O_1%A_80_21# N_A_80_21#_M1004_d N_A_80_21#_M1003_d + N_A_80_21#_c_55_n N_A_80_21#_M1006_g N_A_80_21#_M1005_g N_A_80_21#_c_57_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.spice b/cells/a32o/sky130_fd_sc_lp__a32o_1.spice index 6c2bfab..d317f16 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_1.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_1.spice -* Created: Fri Aug 28 10:00:55 2020 +* Created: Wed Sep 2 09:27:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_2.lvs.report new file mode 100644 index 0000000..9fa1a26 --- /dev/null +++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_2.sp ('sky130_fd_sc_lp__a32o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_2.spice ('sky130_fd_sc_lp__a32o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32o_2 sky130_fd_sc_lp__a32o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a32o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice index 8625ad6..370627b 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_2.pex.spice -* Created: Fri Aug 28 10:01:02 2020 +* Created: Wed Sep 2 09:27:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice index 4fe68b4..a74d474 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_2.pxi.spice -* Created: Fri Aug 28 10:01:02 2020 +* Created: Wed Sep 2 09:27:41 2020 * x_PM_SKY130_FD_SC_LP__A32O_2%A_108_267# N_A_108_267#_M1010_d + N_A_108_267#_M1008_d N_A_108_267#_M1005_g N_A_108_267#_M1001_g
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.spice b/cells/a32o/sky130_fd_sc_lp__a32o_2.spice index b2d9087..31acaa4 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_2.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_2.spice -* Created: Fri Aug 28 10:01:02 2020 +* Created: Wed Sep 2 09:27:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_4.lvs.report new file mode 100644 index 0000000..2b66d9b --- /dev/null +++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_4.sp ('sky130_fd_sc_lp__a32o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_4.spice ('sky130_fd_sc_lp__a32o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:45 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32o_4 sky130_fd_sc_lp__a32o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a32o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 B2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice index 81cd51a..106f11d 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_4.pex.spice -* Created: Fri Aug 28 10:01:09 2020 +* Created: Wed Sep 2 09:27:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice index 5fa5c54..819c632 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_4.pxi.spice -* Created: Fri Aug 28 10:01:09 2020 +* Created: Wed Sep 2 09:27:48 2020 * x_PM_SKY130_FD_SC_LP__A32O_4%A_101_21# N_A_101_21#_M1015_d N_A_101_21#_M1009_d + N_A_101_21#_M1024_d N_A_101_21#_M1003_s N_A_101_21#_M1004_g
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.spice b/cells/a32o/sky130_fd_sc_lp__a32o_4.spice index 52f8779..c410e50 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_4.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_4.spice -* Created: Fri Aug 28 10:01:09 2020 +* Created: Wed Sep 2 09:27:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_lp.lvs.report new file mode 100644 index 0000000..ec77a33 --- /dev/null +++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_lp.sp ('sky130_fd_sc_lp__a32o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice ('sky130_fd_sc_lp__a32o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32o_lp sky130_fd_sc_lp__a32o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a32o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 14 13 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice index a641692..da571a2 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_lp.pex.spice -* Created: Fri Aug 28 10:01:16 2020 +* Created: Wed Sep 2 09:27:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice index 76a3a24..976ec49 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_lp.pxi.spice -* Created: Fri Aug 28 10:01:16 2020 +* Created: Wed Sep 2 09:27:55 2020 * x_PM_SKY130_FD_SC_LP__A32O_LP%B2 N_B2_M1006_g N_B2_M1001_g N_B2_c_76_n + N_B2_c_77_n N_B2_c_82_n B2 N_B2_c_78_n N_B2_c_79_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice b/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice index f556eff..7dd8db3 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_lp.spice -* Created: Fri Aug 28 10:01:16 2020 +* Created: Wed Sep 2 09:27:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_m.lvs.report new file mode 100644 index 0000000..20c162e --- /dev/null +++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_m.sp ('sky130_fd_sc_lp__a32o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_m.spice ('sky130_fd_sc_lp__a32o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:27:58 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32o_m sky130_fd_sc_lp__a32o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a32o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice index a39f461..0425673 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_m.pex.spice -* Created: Fri Aug 28 10:01:23 2020 +* Created: Wed Sep 2 09:28:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice index 1cfe5a6..dc21efd 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_m.pxi.spice -* Created: Fri Aug 28 10:01:23 2020 +* Created: Wed Sep 2 09:28:01 2020 * x_PM_SKY130_FD_SC_LP__A32O_M%A_84_153# N_A_84_153#_M1007_d N_A_84_153#_M1002_d + N_A_84_153#_M1001_g N_A_84_153#_M1006_g N_A_84_153#_c_71_n N_A_84_153#_c_72_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.spice b/cells/a32o/sky130_fd_sc_lp__a32o_m.spice index 7c800ef..695209e 100644 --- a/cells/a32o/sky130_fd_sc_lp__a32o_m.spice +++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32o_m.spice -* Created: Fri Aug 28 10:01:23 2020 +* Created: Wed Sep 2 09:28:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.lvs.report new file mode 100644 index 0000000..20a25e6 --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_0.sp ('sky130_fd_sc_lp__a32oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice ('sky130_fd_sc_lp__a32oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32oi_0 sky130_fd_sc_lp__a32oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice index d93b899..5f21012 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_0.pex.spice -* Created: Fri Aug 28 10:01:30 2020 +* Created: Wed Sep 2 09:28:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice index 5b84e7e..02b4a41 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_0.pxi.spice -* Created: Fri Aug 28 10:01:30 2020 +* Created: Wed Sep 2 09:28:08 2020 * x_PM_SKY130_FD_SC_LP__A32OI_0%B2 N_B2_M1001_g N_B2_M1005_g N_B2_c_71_n + N_B2_c_72_n B2 B2 B2 N_B2_c_74_n PM_SKY130_FD_SC_LP__A32OI_0%B2
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice index 6cd7de9..2dd2a12 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_0.spice -* Created: Fri Aug 28 10:01:30 2020 +* Created: Wed Sep 2 09:28:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.lvs.report new file mode 100644 index 0000000..44948bc --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_1.sp ('sky130_fd_sc_lp__a32oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice ('sky130_fd_sc_lp__a32oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:11 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32oi_1 sky130_fd_sc_lp__a32oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice index 7bddeb9..6c4f609 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_1.pex.spice -* Created: Fri Aug 28 10:01:37 2020 +* Created: Wed Sep 2 09:28:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice index 5b5a7d9..4a0f375 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_1.pxi.spice -* Created: Fri Aug 28 10:01:37 2020 +* Created: Wed Sep 2 09:28:14 2020 * x_PM_SKY130_FD_SC_LP__A32OI_1%B2 N_B2_c_50_n N_B2_M1006_g N_B2_M1000_g B2 B2 + N_B2_c_53_n PM_SKY130_FD_SC_LP__A32OI_1%B2
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice index ce86ec4..37f0c75 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_1.spice -* Created: Fri Aug 28 10:01:37 2020 +* Created: Wed Sep 2 09:28:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.lvs.report new file mode 100644 index 0000000..9c225a0 --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_2.sp ('sky130_fd_sc_lp__a32oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice ('sky130_fd_sc_lp__a32oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32oi_2 sky130_fd_sc_lp__a32oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice index 84b5856..fc60a52 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_2.pex.spice -* Created: Fri Aug 28 10:01:53 2020 +* Created: Wed Sep 2 09:28:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice index 1ea6be7..efb5e47 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_2.pxi.spice -* Created: Fri Aug 28 10:01:53 2020 +* Created: Wed Sep 2 09:28:21 2020 * x_PM_SKY130_FD_SC_LP__A32OI_2%B2 N_B2_c_91_n N_B2_M1012_g N_B2_M1005_g + N_B2_c_93_n N_B2_M1013_g N_B2_M1011_g N_B2_c_95_n B2 B2 N_B2_c_97_n
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice index f4b2e60..5b99089 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_2.spice -* Created: Fri Aug 28 10:01:53 2020 +* Created: Wed Sep 2 09:28:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.lvs.report new file mode 100644 index 0000000..773ed4d --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_4.sp ('sky130_fd_sc_lp__a32oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice ('sky130_fd_sc_lp__a32oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32oi_4 sky130_fd_sc_lp__a32oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice index ae9a31b..5e48cf4 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_4.pex.spice -* Created: Fri Aug 28 10:02:01 2020 +* Created: Wed Sep 2 09:28:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice index 2108e89..3d99d5d 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_4.pxi.spice -* Created: Fri Aug 28 10:02:01 2020 +* Created: Wed Sep 2 09:28:28 2020 * x_PM_SKY130_FD_SC_LP__A32OI_4%B2 N_B2_c_134_n N_B2_M1002_g N_B2_M1006_g + N_B2_c_136_n N_B2_M1013_g N_B2_M1020_g N_B2_c_138_n N_B2_M1016_g N_B2_M1021_g
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice index 29cf9c2..c0b35b6 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_4.spice -* Created: Fri Aug 28 10:02:01 2020 +* Created: Wed Sep 2 09:28:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.lvs.report new file mode 100644 index 0000000..16cf462 --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_lp.sp ('sky130_fd_sc_lp__a32oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice ('sky130_fd_sc_lp__a32oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32oi_lp sky130_fd_sc_lp__a32oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice index c201716..753d05c 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_lp.pex.spice -* Created: Fri Aug 28 10:02:08 2020 +* Created: Wed Sep 2 09:28:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice index 656d27b..1d4ad5b 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_lp.pxi.spice -* Created: Fri Aug 28 10:02:08 2020 +* Created: Wed Sep 2 09:28:34 2020 * x_PM_SKY130_FD_SC_LP__A32OI_LP%B2 N_B2_M1008_g N_B2_c_68_n N_B2_M1005_g + N_B2_c_69_n B2 B2 N_B2_c_71_n PM_SKY130_FD_SC_LP__A32OI_LP%B2
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice index a3c8d17..274a18b 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_lp.spice -* Created: Fri Aug 28 10:02:08 2020 +* Created: Wed Sep 2 09:28:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.lvs.report new file mode 100644 index 0000000..589031f --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a32oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_m.sp ('sky130_fd_sc_lp__a32oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice ('sky130_fd_sc_lp__a32oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a32oi_m sky130_fd_sc_lp__a32oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice index c9bd445..cc968da 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_m.pex.spice -* Created: Fri Aug 28 10:02:15 2020 +* Created: Wed Sep 2 09:28:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice index 6b0e149..a7175e2 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_m.pxi.spice -* Created: Fri Aug 28 10:02:15 2020 +* Created: Wed Sep 2 09:28:41 2020 * x_PM_SKY130_FD_SC_LP__A32OI_M%B2 N_B2_c_71_n N_B2_c_72_n N_B2_c_73_n + N_B2_M1000_g N_B2_M1009_g N_B2_c_75_n N_B2_c_80_n B2 B2 B2 B2 B2 N_B2_c_77_n
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice index ecbf7c6..fd0b9d7 100644 --- a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice +++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a32oi_m.spice -* Created: Fri Aug 28 10:02:15 2020 +* Created: Wed Sep 2 09:28:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_0.lvs.report new file mode 100644 index 0000000..8d77600 --- /dev/null +++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41o_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_0.sp ('sky130_fd_sc_lp__a41o_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_0.spice ('sky130_fd_sc_lp__a41o_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:45 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41o_0 sky130_fd_sc_lp__a41o_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a41o_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice index 506c887..27263f9 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_0.pex.spice -* Created: Fri Aug 28 10:02:23 2020 +* Created: Wed Sep 2 09:28:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice index 1bc7286..9f83fcf 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_0.pxi.spice -* Created: Fri Aug 28 10:02:23 2020 +* Created: Wed Sep 2 09:28:48 2020 * x_PM_SKY130_FD_SC_LP__A41O_0%A_80_309# N_A_80_309#_M1006_d N_A_80_309#_M1008_s + N_A_80_309#_c_100_n N_A_80_309#_M1001_g N_A_80_309#_M1002_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.spice b/cells/a41o/sky130_fd_sc_lp__a41o_0.spice index af3146a..afc1e24 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_0.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_0.spice -* Created: Fri Aug 28 10:02:23 2020 +* Created: Wed Sep 2 09:28:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_1.lvs.report new file mode 100644 index 0000000..16cfda2 --- /dev/null +++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_1.sp ('sky130_fd_sc_lp__a41o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_1.spice ('sky130_fd_sc_lp__a41o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41o_1 sky130_fd_sc_lp__a41o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a41o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice index b2e75dd..64f2803 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_1.pex.spice -* Created: Fri Aug 28 10:02:30 2020 +* Created: Wed Sep 2 09:28:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice index 127f848..4b96962 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_1.pxi.spice -* Created: Fri Aug 28 10:02:30 2020 +* Created: Wed Sep 2 09:28:55 2020 * x_PM_SKY130_FD_SC_LP__A41O_1%A_113_237# N_A_113_237#_M1010_d + N_A_113_237#_M1011_s N_A_113_237#_M1008_g N_A_113_237#_c_62_n
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.spice b/cells/a41o/sky130_fd_sc_lp__a41o_1.spice index 0c60f0f..40371d2 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_1.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_1.spice -* Created: Fri Aug 28 10:02:30 2020 +* Created: Wed Sep 2 09:28:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_2.lvs.report new file mode 100644 index 0000000..17a329b --- /dev/null +++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_2.sp ('sky130_fd_sc_lp__a41o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_2.spice ('sky130_fd_sc_lp__a41o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:28:58 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41o_2 sky130_fd_sc_lp__a41o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a41o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice index a98f4e5..b97adef 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_2.pex.spice -* Created: Fri Aug 28 10:02:38 2020 +* Created: Wed Sep 2 09:29:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice index bf2bb64..682cf42 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_2.pxi.spice -* Created: Fri Aug 28 10:02:38 2020 +* Created: Wed Sep 2 09:29:01 2020 * x_PM_SKY130_FD_SC_LP__A41O_2%A_90_53# N_A_90_53#_M1002_s N_A_90_53#_M1003_d + N_A_90_53#_M1005_s N_A_90_53#_c_79_n N_A_90_53#_M1008_g N_A_90_53#_M1004_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.spice b/cells/a41o/sky130_fd_sc_lp__a41o_2.spice index 29cd873..8033149 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_2.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_2.spice -* Created: Fri Aug 28 10:02:38 2020 +* Created: Wed Sep 2 09:29:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_4.lvs.report new file mode 100644 index 0000000..932a300 --- /dev/null +++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_4.sp ('sky130_fd_sc_lp__a41o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_4.spice ('sky130_fd_sc_lp__a41o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41o_4 sky130_fd_sc_lp__a41o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a41o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice index f3d1c6a..6d509b9 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_4.pex.spice -* Created: Fri Aug 28 10:02:54 2020 +* Created: Wed Sep 2 09:29:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice index cdb082d..c6a7bb8 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_4.pxi.spice -* Created: Fri Aug 28 10:02:54 2020 +* Created: Wed Sep 2 09:29:08 2020 * x_PM_SKY130_FD_SC_LP__A41O_4%A_100_23# N_A_100_23#_M1013_d N_A_100_23#_M1017_s + N_A_100_23#_M1007_d N_A_100_23#_M1002_g N_A_100_23#_M1000_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.spice b/cells/a41o/sky130_fd_sc_lp__a41o_4.spice index 396442e..5279ea3 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_4.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_4.spice -* Created: Fri Aug 28 10:02:54 2020 +* Created: Wed Sep 2 09:29:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_lp.lvs.report new file mode 100644 index 0000000..7534753 --- /dev/null +++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41o_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_lp.sp ('sky130_fd_sc_lp__a41o_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice ('sky130_fd_sc_lp__a41o_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41o_lp sky130_fd_sc_lp__a41o_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a41o_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MP(PHIGHVT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A4 A3 A2 A1 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice index 3f43698..172082f 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_lp.pex.spice -* Created: Fri Aug 28 10:03:02 2020 +* Created: Wed Sep 2 09:29:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice index 6ab654c..e465b09 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_lp.pxi.spice -* Created: Fri Aug 28 10:03:02 2020 +* Created: Wed Sep 2 09:29:15 2020 * x_PM_SKY130_FD_SC_LP__A41O_LP%A4 N_A4_M1002_g N_A4_M1010_g N_A4_c_82_n + N_A4_c_83_n A4 N_A4_c_84_n N_A4_c_85_n PM_SKY130_FD_SC_LP__A41O_LP%A4
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice b/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice index 52aeb3f..b0b56c7 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_lp.spice -* Created: Fri Aug 28 10:03:02 2020 +* Created: Wed Sep 2 09:29:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_m.lvs.report new file mode 100644 index 0000000..5f2501d --- /dev/null +++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41o_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_m.sp ('sky130_fd_sc_lp__a41o_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_m.spice ('sky130_fd_sc_lp__a41o_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41o_m sky130_fd_sc_lp__a41o_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_m +SOURCE CELL NAME: sky130_fd_sc_lp__a41o_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NSHORT) + 1 1 0 0 MP(PHIGHVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice index d03ca9e..3b81360 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_m.pex.spice -* Created: Fri Aug 28 10:03:09 2020 +* Created: Wed Sep 2 09:29:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice index a937403..45fee84 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_m.pxi.spice -* Created: Fri Aug 28 10:03:09 2020 +* Created: Wed Sep 2 09:29:21 2020 * x_PM_SKY130_FD_SC_LP__A41O_M%A_80_153# N_A_80_153#_M1004_d N_A_80_153#_M1002_s + N_A_80_153#_c_93_n N_A_80_153#_M1009_g N_A_80_153#_c_87_n N_A_80_153#_M1010_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.spice b/cells/a41o/sky130_fd_sc_lp__a41o_m.spice index 53e91e9..898d8d8 100644 --- a/cells/a41o/sky130_fd_sc_lp__a41o_m.spice +++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41o_m.spice -* Created: Fri Aug 28 10:03:09 2020 +* Created: Wed Sep 2 09:29:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.lvs.report new file mode 100644 index 0000000..5c416e3 --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41oi_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_0.sp ('sky130_fd_sc_lp__a41oi_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice ('sky130_fd_sc_lp__a41oi_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41oi_0 sky130_fd_sc_lp__a41oi_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_0 +SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice index 5c24aa4..8ce4e3c 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_0.pex.spice -* Created: Fri Aug 28 10:03:16 2020 +* Created: Wed Sep 2 09:29:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice index 4156809..212f4f1 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_0.pxi.spice -* Created: Fri Aug 28 10:03:16 2020 +* Created: Wed Sep 2 09:29:28 2020 * x_PM_SKY130_FD_SC_LP__A41OI_0%B1 N_B1_M1006_g N_B1_c_72_n N_B1_M1001_g + N_B1_c_77_n B1 B1 N_B1_c_74_n PM_SKY130_FD_SC_LP__A41OI_0%B1
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice index bf35b9e..a84b18f 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_0.spice -* Created: Fri Aug 28 10:03:16 2020 +* Created: Wed Sep 2 09:29:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.lvs.report new file mode 100644 index 0000000..d3baf16 --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_1.sp ('sky130_fd_sc_lp__a41oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice ('sky130_fd_sc_lp__a41oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:32 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41oi_1 sky130_fd_sc_lp__a41oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_1 +SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice index cc35acf..537efdc 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_1.pex.spice -* Created: Fri Aug 28 10:03:23 2020 +* Created: Wed Sep 2 09:29:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice index 2b37251..fd81372 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_1.pxi.spice -* Created: Fri Aug 28 10:03:23 2020 +* Created: Wed Sep 2 09:29:34 2020 * x_PM_SKY130_FD_SC_LP__A41OI_1%B1 N_B1_c_54_n N_B1_M1007_g N_B1_M1001_g + N_B1_c_56_n N_B1_c_57_n B1 PM_SKY130_FD_SC_LP__A41OI_1%B1
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice index 635817c..0b14355 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_1.spice -* Created: Fri Aug 28 10:03:23 2020 +* Created: Wed Sep 2 09:29:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.lvs.report new file mode 100644 index 0000000..cc95920 --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_2.sp ('sky130_fd_sc_lp__a41oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice ('sky130_fd_sc_lp__a41oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41oi_2 sky130_fd_sc_lp__a41oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_2 +SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice index 087a3d6..8c3c208 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_2.pex.spice -* Created: Fri Aug 28 10:03:30 2020 +* Created: Wed Sep 2 09:29:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice index e603ba9..b4f3dbe 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_2.pxi.spice -* Created: Fri Aug 28 10:03:30 2020 +* Created: Wed Sep 2 09:29:41 2020 * x_PM_SKY130_FD_SC_LP__A41OI_2%B1 N_B1_c_94_n N_B1_M1011_g N_B1_M1001_g + N_B1_c_96_n N_B1_M1012_g N_B1_M1007_g B1 B1 N_B1_c_99_n
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice index d65f819..17cb724 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_2.spice -* Created: Fri Aug 28 10:03:30 2020 +* Created: Wed Sep 2 09:29:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.lvs.report new file mode 100644 index 0000000..12b3dbb --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_4.sp ('sky130_fd_sc_lp__a41oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice ('sky130_fd_sc_lp__a41oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:45 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41oi_4 sky130_fd_sc_lp__a41oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_4 +SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice index dd597dc..3af9b5f 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_4.pex.spice -* Created: Fri Aug 28 10:03:38 2020 +* Created: Wed Sep 2 09:29:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice index ccf15ad..305cdc4 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_4.pxi.spice -* Created: Fri Aug 28 10:03:38 2020 +* Created: Wed Sep 2 09:29:48 2020 * x_PM_SKY130_FD_SC_LP__A41OI_4%B1 N_B1_c_156_n N_B1_M1014_g N_B1_M1007_g + N_B1_c_158_n N_B1_M1021_g N_B1_M1013_g N_B1_c_160_n N_B1_M1022_g N_B1_M1023_g
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice index 6e5b36d..ac478ba 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_4.spice -* Created: Fri Aug 28 10:03:38 2020 +* Created: Wed Sep 2 09:29:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.lvs.report new file mode 100644 index 0000000..7cd11bf --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41oi_lp.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_lp.sp ('sky130_fd_sc_lp__a41oi_lp') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice ('sky130_fd_sc_lp__a41oi_lp') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41oi_lp sky130_fd_sc_lp__a41oi_lp + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_lp +SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_lp + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 12 11 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A4 A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice index 6b1f40b..86f1eec 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_lp.pex.spice -* Created: Fri Aug 28 10:03:45 2020 +* Created: Wed Sep 2 09:29:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice index cc6ac1b..1e32970 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_lp.pxi.spice -* Created: Fri Aug 28 10:03:45 2020 +* Created: Wed Sep 2 09:29:55 2020 * x_PM_SKY130_FD_SC_LP__A41OI_LP%A4 N_A4_M1003_g N_A4_M1010_g A4 A4 N_A4_c_72_n + PM_SKY130_FD_SC_LP__A41OI_LP%A4
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice index 5a11503..e616511 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_lp.spice -* Created: Fri Aug 28 10:03:45 2020 +* Created: Wed Sep 2 09:29:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.lvs.report new file mode 100644 index 0000000..ff2f2fa --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__a41oi_m.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_m.sp ('sky130_fd_sc_lp__a41oi_m') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice ('sky130_fd_sc_lp__a41oi_m') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:29:58 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__a41oi_m sky130_fd_sc_lp__a41oi_m + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_m +SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_m + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice index b443735..974d4bd 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_m.pex.spice -* Created: Fri Aug 28 10:04:01 2020 +* Created: Wed Sep 2 09:30:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice index 103bdf0..fc389b8 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_m.pxi.spice -* Created: Fri Aug 28 10:04:01 2020 +* Created: Wed Sep 2 09:30:01 2020 * x_PM_SKY130_FD_SC_LP__A41OI_M%B1 N_B1_c_80_n N_B1_c_81_n N_B1_M1007_g + N_B1_M1008_g N_B1_c_83_n N_B1_c_84_n N_B1_c_89_n N_B1_c_90_n N_B1_c_91_n B1 B1
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice index 8b81e11..062fdcc 100644 --- a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice +++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__a41oi_m.spice -* Created: Fri Aug 28 10:04:01 2020 +* Created: Wed Sep 2 09:30:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_0.lvs.report new file mode 100644 index 0000000..a6ba7fc --- /dev/null +++ b/cells/and2/sky130_fd_sc_lp__and2_0.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__and2_0.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_0.sp ('sky130_fd_sc_lp__and2_0') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_0.spice ('sky130_fd_sc_lp__and2_0') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:30:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__and2_0 sky130_fd_sc_lp__and2_0 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_lp__and2_0 +SOURCE CELL NAME: sky130_fd_sc_lp__and2_0 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NSHORT) + 3 3 0 0 MP(PHIGHVT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice index bbbc53c..e109219 100644 --- a/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice +++ b/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__and2_0.pex.spice -* Created: Fri Aug 28 10:04:09 2020 +* Created: Wed Sep 2 09:30:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice index e8df69c..4d1ba2e 100644 --- a/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice +++ b/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__and2_0.pxi.spice -* Created: Fri Aug 28 10:04:09 2020 +* Created: Wed Sep 2 09:30:08 2020 * x_PM_SKY130_FD_SC_LP__AND2_0%A N_A_c_47_n N_A_M1003_g N_A_M1000_g N_A_c_53_n A A + A N_A_c_50_n PM_SKY130_FD_SC_LP__AND2_0%A
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.spice b/cells/and2/sky130_fd_sc_lp__and2_0.spice index 0168806..3bfac15 100644 --- a/cells/and2/sky130_fd_sc_lp__and2_0.spice +++ b/cells/and2/sky130_fd_sc_lp__and2_0.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_lp__and2_0.spice -* Created: Fri Aug 28 10:04:09 2020 +* Created: Wed Sep 2 09:30:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2/sky130_fd_sc_lp__and2_1.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_1.lvs.report new file mode 100644 index 0000000..dc08c04 --- /dev/null +++ b/cells/and2/sky130_fd_sc_lp__and2_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_lp__and2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_1.sp ('sky130_fd_sc_lp__and2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_1.spice ('sky130_fd_sc_lp__and2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 09:30:11 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_lp__and2_1 sky130_fd_sc_lp__and2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + +