| commit | 9d32f7b11b25243603baf558eec2ff7f0353c915 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | b6ed921baa302e1a1fe0c08037475f2d69858775 | |
| parent | 9d1b5257cf0440540926107ddb19a3079ce02de2 [diff] | |
| parent | c530f5c8557df2b64da02b904902b6c7c4335b44 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>