)]}'
{
  "commit": "9d32f7b11b25243603baf558eec2ff7f0353c915",
  "tree": "b6ed921baa302e1a1fe0c08037475f2d69858775",
  "parents": [
    "9d1b5257cf0440540926107ddb19a3079ce02de2",
    "c530f5c8557df2b64da02b904902b6c7c4335b44"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}