| { |
| "area": 23.976, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01314, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| } |
| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.71979, |
| "min_pulse_width_low": 0.71979, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00233, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| ] |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.125, |
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| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| 0.0625, |
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| 0.25, |
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| 0.75, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 1.50344 |
| ], |
| [ |
| 0.04934, |
| 0.32774, |
| 0.38381, |
| 0.45179, |
| 0.53252, |
| 0.63063, |
| 0.74745, |
| 0.88833, |
| 1.05758, |
| 1.25914, |
| 1.50349 |
| ], |
| [ |
| 0.04943, |
| 0.32776, |
| 0.38421, |
| 0.45166, |
| 0.5328, |
| 0.63013, |
| 0.74789, |
| 0.88842, |
| 1.05701, |
| 1.26003, |
| 1.50127 |
| ], |
| [ |
| 0.04954, |
| 0.32793, |
| 0.38392, |
| 0.45148, |
| 0.53242, |
| 0.63056, |
| 0.74713, |
| 0.88847, |
| 1.05649, |
| 1.26015, |
| 1.50342 |
| ], |
| [ |
| 0.05057, |
| 0.32833, |
| 0.38455, |
| 0.45197, |
| 0.53347, |
| 0.63058, |
| 0.74733, |
| 0.88847, |
| 1.0573, |
| 1.2596, |
| 1.5033 |
| ], |
| [ |
| 0.05182, |
| 0.3295, |
| 0.3852, |
| 0.4525, |
| 0.5331, |
| 0.6308, |
| 0.7482, |
| 0.8883, |
| 1.0572, |
| 1.2603, |
| 1.5032 |
| ], |
| [ |
| 0.0538, |
| 0.3312, |
| 0.3869, |
| 0.4544, |
| 0.5351, |
| 0.6321, |
| 0.7491, |
| 0.8895, |
| 1.0564, |
| 1.2597, |
| 1.5032 |
| ], |
| [ |
| 0.0567, |
| 0.3325, |
| 0.3887, |
| 0.4558, |
| 0.5365, |
| 0.6334, |
| 0.7508, |
| 0.8907, |
| 1.0583, |
| 1.26, |
| 1.5036 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
