| { |
| "area": 23.976, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.0131, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
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| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.82526, |
| "min_pulse_width_low": 0.82526, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00239, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| ] |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.125, |
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| 0.75, |
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| ], |
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| 0.75, |
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| ], |
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| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
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| 0.75, |
| 1.0, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.0625, |
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| 0.75, |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x11": { |
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| 0.01, |
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| 0.38851, |
| 0.45573, |
| 0.53658, |
| 0.63431, |
| 0.75048, |
| 0.89115, |
| 1.05954, |
| 1.26075, |
| 1.50351 |
| ], |
| [ |
| 0.05508, |
| 0.3327, |
| 0.3887, |
| 0.45611, |
| 0.53653, |
| 0.63419, |
| 0.75018, |
| 0.89089, |
| 1.05912, |
| 1.25849, |
| 1.50352 |
| ], |
| [ |
| 0.05522, |
| 0.33281, |
| 0.38865, |
| 0.45603, |
| 0.53665, |
| 0.6333, |
| 0.74989, |
| 0.89101, |
| 1.05896, |
| 1.25795, |
| 1.5034 |
| ], |
| [ |
| 0.05584, |
| 0.33314, |
| 0.38878, |
| 0.45643, |
| 0.53702, |
| 0.63385, |
| 0.75052, |
| 0.8911, |
| 1.0587, |
| 1.2578, |
| 1.5032 |
| ], |
| [ |
| 0.0572, |
| 0.3341, |
| 0.3895, |
| 0.4567, |
| 0.5373, |
| 0.6344, |
| 0.7512, |
| 0.8909, |
| 1.0586, |
| 1.2611, |
| 1.5024 |
| ], |
| [ |
| 0.0589, |
| 0.3359, |
| 0.3918, |
| 0.4582, |
| 0.5387, |
| 0.6351, |
| 0.7514, |
| 0.8911, |
| 1.0583, |
| 1.2608, |
| 1.5032 |
| ], |
| [ |
| 0.0616, |
| 0.3374, |
| 0.3934, |
| 0.4603, |
| 0.5407, |
| 0.6372, |
| 0.7533, |
| 0.8928, |
| 1.0604, |
| 1.2616, |
| 1.5021 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
