| commit | 37fac29d86a9b340bb679e5dd5e00f5a34d06b21 | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 64f7219de393ac0110e9d5849b5132b1913a668a | |
| parent | c530f5c8557df2b64da02b904902b6c7c4335b44 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>