| commit | 8cd81a6e4b2c8863e2dd7cea9219de3046697f5c | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | 863705935aa5ff52f7fdfbd58188ae98b19bd505 | |
| parent | 9d32f7b11b25243603baf558eec2ff7f0353c915 [diff] | |
| parent | 37fac29d86a9b340bb679e5dd5e00f5a34d06b21 [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>