cells/clkdlybuf4s18/definition.json

{
 "description": "Clock Delay Buffer 4-stage 0.18um length inner stage gates.",
 "file_prefix": "sky130_fd_sc_lp__clkdlybuf4s18",
 "library": "sky130_fd_sc_lp",
 "name": "clkdlybuf4s18",
 "parameters": [],
 "ports": [
  [
   "signal",
   "X",
   "output",
   ""
  ],
  [
   "signal",
   "A",
   "input",
   ""
  ],
  [
   "power",
   "VPWR",
   "input",
   "supply1"
  ],
  [
   "power",
   "VGND",
   "input",
   "supply0"
  ],
  [
   "power",
   "VPB",
   "input",
   "supply1"
  ],
  [
   "power",
   "VNB",
   "input",
   "supply0"
  ]
 ],
 "type": "cell",
 "verilog_name": "sky130_fd_sc_lp__clkdlybuf4s18"
}