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| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
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| "voltage_name": "VPWR" |
| }, |
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| }, |
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| 0.7073, |
| 0.8462, |
| 1.0115, |
| 1.2133, |
| 1.4552, |
| 1.7427 |
| ], |
| [ |
| 0.0398, |
| 0.087, |
| 0.0953, |
| 0.1057, |
| 0.1186, |
| 0.1346, |
| 0.1546, |
| 0.1794, |
| 0.2098, |
| 0.2476, |
| 0.293, |
| 0.3489, |
| 0.4152, |
| 0.495, |
| 0.5915, |
| 0.708, |
| 0.8468, |
| 1.0128, |
| 1.2122, |
| 1.4529, |
| 1.7409 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
