verilog: Fixing power pins usage in non-powerpin mode.
Previously even when `USE_POWER_PIN` was not defined, the drive strength
wrappers where still defining the power pins as ports.
Fixes https://github.com/google/skywater-pdk/issues/181
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/cells/a21o/sky130_fd_sc_hvl__a21o_1.v b/cells/a21o/sky130_fd_sc_hvl__a21o_1.v
index 90da894..a6c2e4f 100644
--- a/cells/a21o/sky130_fd_sc_hvl__a21o_1.v
+++ b/cells/a21o/sky130_fd_sc_hvl__a21o_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hvl__a21o_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.v b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.v
index 362f9ac..8fcb071 100644
--- a/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.v
+++ b/cells/a21oi/sky130_fd_sc_hvl__a21oi_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hvl__a21oi_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22o/sky130_fd_sc_hvl__a22o_1.v b/cells/a22o/sky130_fd_sc_hvl__a22o_1.v
index 5ed82b2..d1e990d 100644
--- a/cells/a22o/sky130_fd_sc_hvl__a22o_1.v
+++ b/cells/a22o/sky130_fd_sc_hvl__a22o_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hvl__a22o_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.v b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.v
index a083707..8fb961c 100644
--- a/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.v
+++ b/cells/a22oi/sky130_fd_sc_hvl__a22oi_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hvl__a22oi_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and2/sky130_fd_sc_hvl__and2_1.v b/cells/and2/sky130_fd_sc_hvl__and2_1.v
index d9cf3a4..146e90c 100644
--- a/cells/and2/sky130_fd_sc_hvl__and2_1.v
+++ b/cells/and2/sky130_fd_sc_hvl__and2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hvl__and2_1 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/and3/sky130_fd_sc_hvl__and3_1.v b/cells/and3/sky130_fd_sc_hvl__and3_1.v
index 8ff4438..8b9357d 100644
--- a/cells/and3/sky130_fd_sc_hvl__and3_1.v
+++ b/cells/and3/sky130_fd_sc_hvl__and3_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hvl__and3_1 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_1.v b/cells/buf/sky130_fd_sc_hvl__buf_1.v
index e0586ca..5ea57fe 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_1.v
+++ b/cells/buf/sky130_fd_sc_hvl__buf_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__buf_1 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_16.v b/cells/buf/sky130_fd_sc_hvl__buf_16.v
index c980ab5..78bc1a3 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_16.v
+++ b/cells/buf/sky130_fd_sc_hvl__buf_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__buf_16 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_2.v b/cells/buf/sky130_fd_sc_hvl__buf_2.v
index 118fec3..e74c9c3 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_2.v
+++ b/cells/buf/sky130_fd_sc_hvl__buf_2.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__buf_2 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_32.v b/cells/buf/sky130_fd_sc_hvl__buf_32.v
index 584f8de..b61fd88 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_32.v
+++ b/cells/buf/sky130_fd_sc_hvl__buf_32.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__buf_32 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_4.v b/cells/buf/sky130_fd_sc_hvl__buf_4.v
index c5d6dcf..62980d5 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_4.v
+++ b/cells/buf/sky130_fd_sc_hvl__buf_4.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__buf_4 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/buf/sky130_fd_sc_hvl__buf_8.v b/cells/buf/sky130_fd_sc_hvl__buf_8.v
index 182c3f4..590b44f 100644
--- a/cells/buf/sky130_fd_sc_hvl__buf_8.v
+++ b/cells/buf/sky130_fd_sc_hvl__buf_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__buf_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/conb/sky130_fd_sc_hvl__conb_1.v b/cells/conb/sky130_fd_sc_hvl__conb_1.v
index 6431c6c..f17bcc2 100644
--- a/cells/conb/sky130_fd_sc_hvl__conb_1.v
+++ b/cells/conb/sky130_fd_sc_hvl__conb_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__conb_1 (
- HI ,
- LO ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ HI,
+ LO
);
- output HI ;
- output LO ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output HI;
+ output LO;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_4.v b/cells/decap/sky130_fd_sc_hvl__decap_4.v
index f5217f7..4d569b9 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_4.v
+++ b/cells/decap/sky130_fd_sc_hvl__decap_4.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hvl__decap_4 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hvl__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/decap/sky130_fd_sc_hvl__decap_8.v b/cells/decap/sky130_fd_sc_hvl__decap_8.v
index 9ce70b3..49fb91e 100644
--- a/cells/decap/sky130_fd_sc_hvl__decap_8.v
+++ b/cells/decap/sky130_fd_sc_hvl__decap_8.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hvl__decap_8 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hvl__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.v b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.v
index b0ecdeb..6ce64ff 100644
--- a/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.v
+++ b/cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.v
@@ -82,11 +82,7 @@
Q_N ,
CLK ,
D ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -94,10 +90,6 @@
input CLK ;
input D ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.v b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.v
index 2a66eee..3f13f74 100644
--- a/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.v
+++ b/cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.v b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.v
index 5a65c0a..e83ec69 100644
--- a/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.v
+++ b/cells/dfsbp/sky130_fd_sc_hvl__dfsbp_1.v
@@ -82,11 +82,7 @@
Q_N ,
CLK ,
D ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -94,10 +90,6 @@
input CLK ;
input D ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.v b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.v
index d42d078..839d2b3 100644
--- a/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.v
+++ b/cells/dfstp/sky130_fd_sc_hvl__dfstp_1.v
@@ -78,21 +78,13 @@
Q ,
CLK ,
D ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.v b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.v
index 7bcd488..4f292a0 100644
--- a/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.v
+++ b/cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hvl__dfxbp_1 (
- Q ,
- Q_N ,
- CLK ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ Q_N,
+ CLK,
+ D
);
- output Q ;
- output Q_N ;
- input CLK ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.v b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.v
index 3b22e97..de6ad29 100644
--- a/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.v
+++ b/cells/dfxtp/sky130_fd_sc_hvl__dfxtp_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hvl__dfxtp_1 (
- Q ,
- CLK ,
- D ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ CLK,
+ D
);
- output Q ;
- input CLK ;
- input D ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ input CLK;
+ input D ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/diode/sky130_fd_sc_hvl__diode_2.v b/cells/diode/sky130_fd_sc_hvl__diode_2.v
index 6d4ce0a..0b1723b 100644
--- a/cells/diode/sky130_fd_sc_hvl__diode_2.v
+++ b/cells/diode/sky130_fd_sc_hvl__diode_2.v
@@ -66,18 +66,10 @@
`celldefine
module sky130_fd_sc_hvl__diode_2 (
- DIODE,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ DIODE
);
input DIODE;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.v b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.v
index f325e3f..9fd0faa 100644
--- a/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.v
+++ b/cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
- CLK ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ CLK
);
output GCLK;
input GATE;
input CLK ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.v b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.v
index 75f9319..87ee5c1 100644
--- a/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.v
+++ b/cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.v
@@ -79,21 +79,13 @@
Q ,
RESET_B,
D ,
- GATE ,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.v b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.v
index e67034e..0d692e7 100644
--- a/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.v
+++ b/cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hvl__dlxtp_1 (
Q ,
D ,
- GATE,
- VPWR,
- VGND,
- VPB ,
- VNB
+ GATE
);
output Q ;
input D ;
input GATE;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvn/sky130_fd_sc_hvl__einvn_1.v b/cells/einvn/sky130_fd_sc_hvl__einvn_1.v
index 3c41d9f..f3b8606 100644
--- a/cells/einvn/sky130_fd_sc_hvl__einvn_1.v
+++ b/cells/einvn/sky130_fd_sc_hvl__einvn_1.v
@@ -74,20 +74,12 @@
module sky130_fd_sc_hvl__einvn_1 (
Z ,
A ,
- TE_B,
- VPWR,
- VGND,
- VPB ,
- VNB
+ TE_B
);
output Z ;
input A ;
input TE_B;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/einvp/sky130_fd_sc_hvl__einvp_1.v b/cells/einvp/sky130_fd_sc_hvl__einvp_1.v
index 881fb3b..b77e926 100644
--- a/cells/einvp/sky130_fd_sc_hvl__einvp_1.v
+++ b/cells/einvp/sky130_fd_sc_hvl__einvp_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hvl__einvp_1 (
- Z ,
- A ,
- TE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Z ,
+ A ,
+ TE
);
- output Z ;
- input A ;
- input TE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Z ;
+ input A ;
+ input TE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_1.v b/cells/fill/sky130_fd_sc_hvl__fill_1.v
index b86db9c..03b13f7 100644
--- a/cells/fill/sky130_fd_sc_hvl__fill_1.v
+++ b/cells/fill/sky130_fd_sc_hvl__fill_1.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hvl__fill_1 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hvl__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_2.v b/cells/fill/sky130_fd_sc_hvl__fill_2.v
index f36e6c4..844f4ff 100644
--- a/cells/fill/sky130_fd_sc_hvl__fill_2.v
+++ b/cells/fill/sky130_fd_sc_hvl__fill_2.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hvl__fill_2 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hvl__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_4.v b/cells/fill/sky130_fd_sc_hvl__fill_4.v
index 645be9f..9f06d8b 100644
--- a/cells/fill/sky130_fd_sc_hvl__fill_4.v
+++ b/cells/fill/sky130_fd_sc_hvl__fill_4.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hvl__fill_4 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hvl__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/fill/sky130_fd_sc_hvl__fill_8.v b/cells/fill/sky130_fd_sc_hvl__fill_8.v
index 8dd5702..5989678 100644
--- a/cells/fill/sky130_fd_sc_hvl__fill_8.v
+++ b/cells/fill/sky130_fd_sc_hvl__fill_8.v
@@ -62,18 +62,7 @@
/*********************************************************/
`celldefine
-module sky130_fd_sc_hvl__fill_8 (
- VPWR,
- VGND,
- VPB ,
- VNB
-);
-
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
-
+module sky130_fd_sc_hvl__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_1.v b/cells/inv/sky130_fd_sc_hvl__inv_1.v
index 487d93d..faf4e0c 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_1.v
+++ b/cells/inv/sky130_fd_sc_hvl__inv_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__inv_1 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_16.v b/cells/inv/sky130_fd_sc_hvl__inv_16.v
index 5b41a54..953a73f 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_16.v
+++ b/cells/inv/sky130_fd_sc_hvl__inv_16.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__inv_16 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_2.v b/cells/inv/sky130_fd_sc_hvl__inv_2.v
index 7d2b41a..36a6b68 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_2.v
+++ b/cells/inv/sky130_fd_sc_hvl__inv_2.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__inv_2 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_4.v b/cells/inv/sky130_fd_sc_hvl__inv_4.v
index d2041b4..8935690 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_4.v
+++ b/cells/inv/sky130_fd_sc_hvl__inv_4.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__inv_4 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/inv/sky130_fd_sc_hvl__inv_8.v b/cells/inv/sky130_fd_sc_hvl__inv_8.v
index 80865a5..48c66e6 100644
--- a/cells/inv/sky130_fd_sc_hvl__inv_8.v
+++ b/cells/inv/sky130_fd_sc_hvl__inv_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__inv_8 (
- Y ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A
);
- output Y ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.v b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.v
index a03f5ad..e649079 100644
--- a/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.v
+++ b/cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.v
@@ -73,22 +73,12 @@
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl_1 (
- X ,
- A ,
- VPWR ,
- VGND ,
- LOWHVPWR,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR ;
- input VGND ;
- input LOWHVPWR;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.v b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.v
index e48cbc1..0f0fa69 100644
--- a/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.v
+++ b/cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh_1.v
@@ -73,22 +73,12 @@
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh_1 (
- X ,
- A ,
- VPWR ,
- VGND ,
- LOWHVPWR,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR ;
- input VGND ;
- input LOWHVPWR;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.v b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.v
index f30f591..7ef9903 100644
--- a/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.v
+++ b/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.v
@@ -72,22 +72,12 @@
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_1 (
- X ,
- A ,
- VPWR ,
- VGND ,
- LVPWR,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR ;
- input VGND ;
- input LVPWR;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.v b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.v
index af5207a..f87a846 100644
--- a/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.v
+++ b/cells/lsbufhv2lv_simple/sky130_fd_sc_hvl__lsbufhv2lv_simple_1.v
@@ -74,22 +74,12 @@
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple_1 (
- X ,
- A ,
- VPWR ,
- VGND ,
- LVPWR,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR ;
- input VGND ;
- input LVPWR;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.v b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.v
index 7bdbf37..ace0f13 100644
--- a/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.v
+++ b/cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.v
@@ -73,22 +73,12 @@
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_1 (
- X ,
- A ,
- VPWR ,
- VGND ,
- LVPWR,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR ;
- input VGND ;
- input LVPWR;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.v b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.v
index 04a73e1..3e47926 100644
--- a/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.v
+++ b/cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3.v
@@ -81,22 +81,12 @@
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3 (
X ,
A ,
- SLEEP_B,
- VPWR ,
- VGND ,
- LVPWR ,
- VPB ,
- VNB
+ SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
- input VPWR ;
- input VGND ;
- input LVPWR ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.v b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.v
index b74ff64..fa87646 100644
--- a/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.v
+++ b/cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.v
@@ -80,22 +80,12 @@
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1 (
X ,
A ,
- SLEEP_B,
- VPWR ,
- VGND ,
- LVPWR ,
- VPB ,
- VNB
+ SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
- input VPWR ;
- input VGND ;
- input LVPWR ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.v b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.v
index 4b7217a..5e52787 100644
--- a/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.v
+++ b/cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.v
@@ -73,22 +73,12 @@
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
- X ,
- A ,
- VPWR ,
- VGND ,
- LVPWR,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR ;
- input VGND ;
- input LVPWR;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR ;
diff --git a/cells/mux2/sky130_fd_sc_hvl__mux2_1.v b/cells/mux2/sky130_fd_sc_hvl__mux2_1.v
index d4adeca..a6444c3 100644
--- a/cells/mux2/sky130_fd_sc_hvl__mux2_1.v
+++ b/cells/mux2/sky130_fd_sc_hvl__mux2_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hvl__mux2_1 (
- X ,
- A0 ,
- A1 ,
- S ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ S
);
- output X ;
- input A0 ;
- input A1 ;
- input S ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input S ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/mux4/sky130_fd_sc_hvl__mux4_1.v b/cells/mux4/sky130_fd_sc_hvl__mux4_1.v
index b99ce75..315d71e 100644
--- a/cells/mux4/sky130_fd_sc_hvl__mux4_1.v
+++ b/cells/mux4/sky130_fd_sc_hvl__mux4_1.v
@@ -84,30 +84,22 @@
`celldefine
module sky130_fd_sc_hvl__mux4_1 (
- X ,
- A0 ,
- A1 ,
- A2 ,
- A3 ,
- S0 ,
- S1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A0,
+ A1,
+ A2,
+ A3,
+ S0,
+ S1
);
- output X ;
- input A0 ;
- input A1 ;
- input A2 ;
- input A3 ;
- input S0 ;
- input S1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input S0;
+ input S1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand2/sky130_fd_sc_hvl__nand2_1.v b/cells/nand2/sky130_fd_sc_hvl__nand2_1.v
index eb6b45b..70dd72d 100644
--- a/cells/nand2/sky130_fd_sc_hvl__nand2_1.v
+++ b/cells/nand2/sky130_fd_sc_hvl__nand2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hvl__nand2_1 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nand3/sky130_fd_sc_hvl__nand3_1.v b/cells/nand3/sky130_fd_sc_hvl__nand3_1.v
index e777b9e..af6235d 100644
--- a/cells/nand3/sky130_fd_sc_hvl__nand3_1.v
+++ b/cells/nand3/sky130_fd_sc_hvl__nand3_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hvl__nand3_1 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor2/sky130_fd_sc_hvl__nor2_1.v b/cells/nor2/sky130_fd_sc_hvl__nor2_1.v
index 8988358..0a7d40b 100644
--- a/cells/nor2/sky130_fd_sc_hvl__nor2_1.v
+++ b/cells/nor2/sky130_fd_sc_hvl__nor2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hvl__nor2_1 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/nor3/sky130_fd_sc_hvl__nor3_1.v b/cells/nor3/sky130_fd_sc_hvl__nor3_1.v
index 327bf4b..fba7973 100644
--- a/cells/nor3/sky130_fd_sc_hvl__nor3_1.v
+++ b/cells/nor3/sky130_fd_sc_hvl__nor3_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hvl__nor3_1 (
- Y ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B,
+ C
);
- output Y ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21a/sky130_fd_sc_hvl__o21a_1.v b/cells/o21a/sky130_fd_sc_hvl__o21a_1.v
index 97bfc46..7de9359 100644
--- a/cells/o21a/sky130_fd_sc_hvl__o21a_1.v
+++ b/cells/o21a/sky130_fd_sc_hvl__o21a_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hvl__o21a_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.v b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.v
index b2e3c13..e8ab238 100644
--- a/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.v
+++ b/cells/o21ai/sky130_fd_sc_hvl__o21ai_1.v
@@ -77,24 +77,16 @@
`celldefine
module sky130_fd_sc_hvl__o21ai_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22a/sky130_fd_sc_hvl__o22a_1.v b/cells/o22a/sky130_fd_sc_hvl__o22a_1.v
index 3bfd961..f2c6204 100644
--- a/cells/o22a/sky130_fd_sc_hvl__o22a_1.v
+++ b/cells/o22a/sky130_fd_sc_hvl__o22a_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hvl__o22a_1 (
- X ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output X ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.v b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.v
index 9df67cf..bb2652d 100644
--- a/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.v
+++ b/cells/o22ai/sky130_fd_sc_hvl__o22ai_1.v
@@ -80,26 +80,18 @@
`celldefine
module sky130_fd_sc_hvl__o22ai_1 (
- Y ,
- A1 ,
- A2 ,
- B1 ,
- B2 ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y ,
+ A1,
+ A2,
+ B1,
+ B2
);
- output Y ;
- input A1 ;
- input A2 ;
- input B1 ;
- input B2 ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y ;
+ input A1;
+ input A2;
+ input B1;
+ input B2;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or2/sky130_fd_sc_hvl__or2_1.v b/cells/or2/sky130_fd_sc_hvl__or2_1.v
index 4de50c2..f63a710 100644
--- a/cells/or2/sky130_fd_sc_hvl__or2_1.v
+++ b/cells/or2/sky130_fd_sc_hvl__or2_1.v
@@ -72,22 +72,14 @@
`celldefine
module sky130_fd_sc_hvl__or2_1 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/or3/sky130_fd_sc_hvl__or3_1.v b/cells/or3/sky130_fd_sc_hvl__or3_1.v
index 90a041c..e306000 100644
--- a/cells/or3/sky130_fd_sc_hvl__or3_1.v
+++ b/cells/or3/sky130_fd_sc_hvl__or3_1.v
@@ -75,24 +75,16 @@
`celldefine
module sky130_fd_sc_hvl__or3_1 (
- X ,
- A ,
- B ,
- C ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B,
+ C
);
- output X ;
- input A ;
- input B ;
- input C ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
+ input C;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.v b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.v
index 080b1f2..05fed41 100644
--- a/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.v
+++ b/cells/probe_p/sky130_fd_sc_hvl__probe_p_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__probe_p_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.v b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.v
index 0a91ab2..429a781 100644
--- a/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.v
+++ b/cells/probec_p/sky130_fd_sc_hvl__probec_p_8.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__probec_p_8 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.v b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.v
index ee4e60a..689a012 100644
--- a/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.v
+++ b/cells/schmittbuf/sky130_fd_sc_hvl__schmittbuf_1.v
@@ -69,20 +69,12 @@
`celldefine
module sky130_fd_sc_hvl__schmittbuf_1 (
- X ,
- A ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A
);
- output X ;
- input A ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.v b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.v
index 0b90d42..6e56f3d 100644
--- a/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.v
+++ b/cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.v
@@ -91,11 +91,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -105,10 +101,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.v b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.v
index 2c47ce7..a91fb1e 100644
--- a/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.v
+++ b/cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- RESET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ RESET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input RESET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.v b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.v
index 69d5cff..b426628 100644
--- a/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.v
+++ b/cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp_1.v
@@ -91,11 +91,7 @@
D ,
SCD ,
SCE ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -105,10 +101,6 @@
input SCD ;
input SCE ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.v b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.v
index 77fb4c0..709c705 100644
--- a/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.v
+++ b/cells/sdfstp/sky130_fd_sc_hvl__sdfstp_1.v
@@ -87,11 +87,7 @@
D ,
SCD ,
SCE ,
- SET_B,
- VPWR ,
- VGND ,
- VPB ,
- VNB
+ SET_B
);
output Q ;
@@ -100,10 +96,6 @@
input SCD ;
input SCE ;
input SET_B;
- input VPWR ;
- input VGND ;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.v b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.v
index 73b486a..091e9c6 100644
--- a/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.v
+++ b/cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.v
@@ -81,28 +81,20 @@
`celldefine
module sky130_fd_sc_hvl__sdfxbp_1 (
- Q ,
- Q_N ,
- CLK ,
- D ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ Q_N,
+ CLK,
+ D ,
+ SCD,
+ SCE
);
- output Q ;
- output Q_N ;
- input CLK ;
- input D ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ output Q_N;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.v b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.v
index 53f08a8..56a6e3c 100644
--- a/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.v
+++ b/cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp_1.v
@@ -78,26 +78,18 @@
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
- Q ,
- CLK ,
- D ,
- SCD ,
- SCE ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Q ,
+ CLK,
+ D ,
+ SCD,
+ SCE
);
- output Q ;
- input CLK ;
- input D ;
- input SCD ;
- input SCE ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Q ;
+ input CLK;
+ input D ;
+ input SCD;
+ input SCE;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.v b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.v
index fb68709..f08e36e 100644
--- a/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.v
+++ b/cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.v
@@ -78,21 +78,13 @@
GCLK,
SCE ,
GATE,
- CLK ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.v b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.v
index 79ede03..b590e19 100644
--- a/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.v
+++ b/cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.v
@@ -82,11 +82,7 @@
D ,
SCD ,
SCE ,
- GATE,
- VPWR,
- VGND,
- VPB ,
- VNB
+ GATE
);
output Q ;
@@ -94,10 +90,6 @@
input SCD ;
input SCE ;
input GATE;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.v b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.v
index 32828cf..49bf347 100644
--- a/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.v
+++ b/cells/xnor2/sky130_fd_sc_hvl__xnor2_1.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hvl__xnor2_1 (
- Y ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ Y,
+ A,
+ B
);
- output Y ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output Y;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
diff --git a/cells/xor2/sky130_fd_sc_hvl__xor2_1.v b/cells/xor2/sky130_fd_sc_hvl__xor2_1.v
index bf2ef0e..40e31de 100644
--- a/cells/xor2/sky130_fd_sc_hvl__xor2_1.v
+++ b/cells/xor2/sky130_fd_sc_hvl__xor2_1.v
@@ -74,22 +74,14 @@
`celldefine
module sky130_fd_sc_hvl__xor2_1 (
- X ,
- A ,
- B ,
- VPWR,
- VGND,
- VPB ,
- VNB
+ X,
+ A,
+ B
);
- output X ;
- input A ;
- input B ;
- input VPWR;
- input VGND;
- input VPB ;
- input VNB ;
+ output X;
+ input A;
+ input B;
// Voltage supply signals
supply1 VPWR;
