blob: f08c5f25b6cdded1bc8cbf5b156cb68b0f7d7edc [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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"voltage_name": "VNB"
},
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"pg_pin VPWR": {
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},
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0.5,
0.75,
1.0,
1.25,
1.5
],
"values": [
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],
[
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],
[
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],
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[
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],
[
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]
]
},
"related_pin": "CLK",
"rise_constraint sethold_template_rise10x10": {
"index_1": [
0.01,
0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
"index_2": [
0.01,
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0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
"values": [
[
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0.01933,
0.02518,
0.03104,
0.03397,
0.0369,
0.03104,
0.02518,
0.0164,
0.00761
],
[
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0.01347,
0.0164,
0.02225,
0.02811,
0.02811,
0.02518,
0.01933,
0.01054,
0.00175
],
[
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0.00468,
0.01054,
0.0164,
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0.00761,
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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],
[
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]
]
},
"timing_type": "hold_rising"
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}