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| "clear_preset_var1": "H", | |
| "clear_preset_var2": "L", | |
| "clocked_on": "CLK", | |
| "next_state": "(D&!SCE) | (SCD&SCE)", | |
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| }, | |
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| } | |
| ], | |
| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin,CLK": { | |
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| "clock": "true", | |
| "direction": "input", | |
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| } | |
| }, | |
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| "related_power_pin": "VPWR" | |
| }, | |
| "pin,D": { | |
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| "clock": "false", | |
| "direction": "input", | |
| "internal_power": { | |
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| } | |
| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "timing": [ | |
| { | |
| "fall_constraint,sethold_template_fall10x10": { | |
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| 0.23047, | |
| 0.25391 | |
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| 0.26172, | |
| 0.28125, | |
| 0.30078 | |
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| 0.30859, | |
| 0.32422, | |
| 0.33984 | |
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| 0.36719, | |
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| 0.40625, | |
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| 0.42969, | |
| 0.44531, | |
| 0.46094 | |
| ] | |
| ] | |
| }, | |
| "related_pin": "CLK", | |
| "rise_constraint,sethold_template_rise10x10": { | |
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